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document number: 324645-006 intel ? 6 series chipset and intel ? c200 series chipset datasheet may 2011
2 datasheet information in this document is provided in connection with in tel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent , copyright or other intellectual property right. unless otherwise agreed in writing by intel, the intel products are not designed nor intended for any application in which the failure of the intel product could create a situation where personal injury o0r death may occur. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the a bsence or characteristics of any features or instructions marked reserved or undefined. intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to th em. the information here is subject to change without notice. d o not finalize a design with this information. the products described in this document may contain design defect s or errors known as errata which may cause the product to dev iate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. i 2 c is a two-wire communications bus/protocol developed by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, in cluding philips electronics n.v. and north american philips corporation. intel ? anti-theft technology: no system can provide absolute security under all conditions. requires an enabled chipset, bios, firmwa re and software and a subscription with a capable service provider. consult your system manufacturer and service provider for availability and functionality. intel assumes no liability for lost or stolen data and/or systems or any other damages resulting thereof. for more information, visit http://www.intel.com/go/ anti-theft intel ? high definition audio: requires an intel ? hd audio enabled system. consult your pc manufacturer for more information. sound quality will depend on equipment and actual implementation. for more information about intel ? hd audio, refer to http://www.intel.com/design/chipsets/ hdaudio.htm intel ? vpro? technology is sophisticated and requires setup and activation. availability of features and results will depend upon the setup and configuration of your hardware, software and it environment. to learn more visit: http://www.intel.com/technology/vpro intel ? active management technology (intel ? amt) requires activation and a system wi th a corporate network connection, an intel ? amt-enabled chipset, network hardware and software. for notebooks, intel amt ma y be unavailable or limited over a host os-based vpn, when c onnecting wirelessly, on battery power, sleeping, hibernating or powered off. results dependent upon hardware, setup & configuration. for more inform ation, visit http:// www.intel.com/technology/platform-technology/intel-amt intel ? trusted execution technology: no computer system can provide absolute security under all conditions. intel ? trusted execution technology (intel ? txt) requires a computer system with intel ? virtualization technology, an intel txt-enabled processor, chipset, bios, authenticated code modules and an intel txt-compatible measured launched environment (mle). the mle could consist of a virtual machine monitor, an os or an application. in addition, intel txt requires the system to contain a tpm v1.2, as defined by the trusted computing group and specific software for some uses. for more information, see http://www.intel.com/technology/security intel ? virtualization technology requires a computer system with an enabled intel ? processor, bios, virtual machine monitor (vmm). functionality, performance or other benefits will vary depending on hardware an d software configurations. software applications may not be com patible with all operating systems. consult your pc manufacturer. for more information, visit http://www.intel.com/go/virtualization intel, intel vpro and the intel logo are trademarks of intel corporation in the u.s. and other countries. *other names and brands may be claimed as the property of others. copyright ? 2011, intel corporation
datasheet 3 contents 1introduction ............................................................................................................ 41 1.1 about this manual ............................................................................................. 41 1.2 overview ......................................................................................................... 44 1.2.1 capability overview............................................................................. 45 1.3 intel ? 6 series chipset and intel ? c200 series chipset sku definition ..................... 51 2 signal description ................................................................................................... 55 2.1 direct media interface (dmi) to host controller ..................................................... 57 2.2 pci express* .................................................................................................... 57 2.3 pci interface .................................................................................................... 58 2.4 serial ata interface........................................................................................... 60 2.5 lpc interface.................................................................................................... 63 2.6 interrupt interface ............................................................................................ 63 2.7 usb interface ................................................................................................... 64 2.8 power management interface.............................................................................. 65 2.9 processor interface............................................................................................ 69 2.10 smbus interface................................................................................................ 69 2.11 system management interface............................................................................ 69 2.12 real time clock interface ................................................................................... 70 2.13 miscellaneous signals ........................................................................................ 70 2.14 intel ? high definition audio link ......................................................................... 72 2.15 controller link .................................................................................................. 73 2.16 serial peripheral interface (spi) .......................................................................... 73 2.17 thermal signals ................................................................................................ 73 2.18 testability signals ....... .......... ........... .......... ...................... ............ ......... ............ 74 2.19 clock signals .................................................................................................... 74 2.20 lvds signals .................................................................................................... 77 2.21 analog display /vga dac signals ........................................................................ 78 2.22 intel ? flexible display interface (intel ? fdi) ........................................................ 78 2.23 digital display signals........................................................................................ 79 2.24 general purpose i/o signals ............................................................................... 82 2.25 manageability signals ..... .................. .......... ...................... ............ ......... ............ 86 2.26 power and ground signals .................................................................................. 87 2.27 pin straps ........................................................................................................ 89 2.28 external rtc circuitry ........................................................................................ 92 3pch pin states ......................................................................................................... 93 3.1 integrated pull-ups and pull-downs ..................................................................... 93 3.2 output and i/o signals planes and states............................................................. 95 3.3 power planes for input signals .......................................................................... 107 4 pch and system clocks ......................................................................................... 113 4.1 platform clocking requirements ........................................................................ 113 4.2 functional blocks ............................................................................................ 116 4.3 clock configuration access overview ................................................................. 117 4.4 straps related to clock configuration ................................................................ 117 5 functional description ........................................................................................... 119 5.1 dmi-to-pci bridge (d30:f0) ............................................................................. 119 5.1.1 pci bus interface.............................................................................. 119 5.1.2 pci bridge as an initiator................................................................... 120 5.1.2.1 memory reads and writes .................................................. 120 5.1.2.2 i/o reads and writes ......................................................... 120 5.1.2.3 configuration reads and writes ........................................... 120 5.1.2.4 locked cycles ................................................................... 120 5.1.2.5 target / master aborts ....................................................... 120 5.1.2.6 secondary master latency timer ......................................... 120 5.1.2.7 dual address cycle (dac)................................................... 121 5.1.2.8 memory and i/o decode to pci ........................................... 121 5.1.3 parity error detection and generation.................................................. 121 5.1.4 pcirst# ......................................................................................... 122 5.1.5 peer cycles ...................................................................................... 122
4 datasheet 5.1.6 pci-to-pci bridge model ..................................................................... 122 5.1.7 idsel to device number mapping........................................................ 123 5.1.8 standard pci bus configuration mechanism .......................................... 123 5.1.9 pci legacy mode ............................................................................... 123 5.2 pci express* root ports (d28:f0,f1,f2,f3,f4,f5, f6, f7) ..................................... 124 5.2.1 interrupt generation.......................................................................... 124 5.2.2 power management ........................................................................... 125 5.2.2.1 s3/s4/s5 support .............................................................. 125 5.2.2.2 resuming from suspended state.......................................... 125 5.2.2.3 device initiated pm_pme message ........................................ 125 5.2.2.4 smi/sci generation ........................................................... 126 5.2.3 serr# generation............................................................................. 126 5.2.4 hot-plug .......................................................................................... 126 5.2.4.1 presence detection............................................................. 126 5.2.4.2 message generation ........................................................... 127 5.2.4.3 attention button detection .................................................. 127 5.2.4.4 smi/sci generation ........................................................... 127 5.3 gigabit ethernet controller (b0:d25:f0) ............................................................. 128 5.3.1 gbe pci express* bus interface .......................................................... 130 5.3.1.1 transaction layer............................................................... 130 5.3.1.2 data alignment.................................................................. 130 5.3.1.3 configuration request retry status ...................................... 130 5.3.2 error events and error reporting ......................................................... 131 5.3.2.1 data parity error ................................................................ 131 5.3.2.2 completion with unsuccessful completion status.................... 131 5.3.3 ethernet interface ............................................................................. 131 5.3.3.1 82579 lan phy interface .................................................... 131 5.3.4 pci power management...................................................................... 132 5.3.4.1 wake up ........................................................................... 132 5.3.5 configurable leds ............................................................................. 134 5.3.6 function level reset support (flr) ..................................................... 135 5.3.6.1 flr steps ......................................................................... 135 5.4 lpc bridge (with system and management func tions) (d31:f0)............................. 136 5.4.1 lpc interface .................................................................................... 136 5.4.1.1 lpc cycle types................................................................. 137 5.4.1.2 start field definition........................................................... 137 5.4.1.3 cycle type / direction (cyctype + dir) ............................... 138 5.4.1.4 size ................................................................................. 138 5.4.1.5 sync................................................................................ 138 5.4.1.6 sync time-out.................................................................. 139 5.4.1.7 sync error indication ......................................................... 139 5.4.1.8 lframe# usage................................................................. 139 5.4.1.9 i/o cycles......................................................................... 139 5.4.1.10 bus master cycles .............................................................. 140 5.4.1.11 lpc power management ...................................................... 140 5.4.1.12 configuration and pch implications ...................................... 140 5.5 dma operation (d31:f0) .................................................................................. 141 5.5.1 channel priority ................................................................................ 141 5.5.1.1 fixed priority ..................................................................... 141 5.5.1.2 rotating priority................................................................. 142 5.5.2 address compatibility mode .... ................ ............ ........... ........ ............. 142 5.5.3 summary of dma transfer sizes.......................................................... 142 5.5.3.1 address shifting when programmed for 16-bit i/o count by words .......................................................................... 142 5.5.4 autoinitialize..................................................................................... 143 5.5.5 software commands.......................................................................... 143 5.6 lpc dma ........................................................................................................ 144 5.6.1 asserting dma requests..................................................................... 144 5.6.2 abandoning dma requests ................................................................. 145 5.6.3 general flow of dma transfers............................................................ 145 5.6.4 terminal count ................................................................................. 145 5.6.5 verify mode ...................................................................................... 146 5.6.6 dma request deassertion................................................................... 146 5.6.7 sync field / ldrq# rules .................................................................. 147 5.7 8254 timers (d31:f0) ...................................................................................... 147 5.7.1 timer programming ........................................................................... 148 5.7.2 reading from the interval timer.......................................................... 149
datasheet 5 5.7.2.1 simple read ..................................................................... 149 5.7.2.2 counter latch command .................................................... 149 5.7.2.3 read back command ......................................................... 149 5.8 8259 interrupt controllers (pic) (d31:f0) .......................................................... 150 5.8.1 interrupt handling ............................................................................ 151 5.8.1.1 generating interrupts......................................................... 151 5.8.1.2 acknowledging interrupts ................................................... 151 5.8.1.3 hardware/software interrupt sequ ence ................................ 152 5.8.2 initialization command words (icwx) ................................................. 152 5.8.2.1 icw1 ............................................................................... 152 5.8.2.2 icw2 ............................................................................... 153 5.8.2.3 icw3 ............................................................................... 153 5.8.2.4 icw4 ............................................................................... 153 5.8.3 operation command words (ocw) ........... .......................................... 153 5.8.4 modes of operation ........................................................................... 153 5.8.4.1 fully nested mode ............................................................. 153 5.8.4.2 special fully-nested mode .................................................. 154 5.8.4.3 automatic rotation mode (equal priority devices) .................. 154 5.8.4.4 specific rotation mode (specific priority) .............................. 154 5.8.4.5 poll mode.......................................................................... 154 5.8.4.6 cascade mode ................................................................... 155 5.8.4.7 edge and level triggered mode ........................................... 155 5.8.4.8 end of interrupt (eoi) operations ........................................ 155 5.8.4.9 normal end of interrupt ..................................................... 155 5.8.4.10 automatic end of interrupt mode ......................................... 155 5.8.5 masking interrupts ............................................................................ 156 5.8.5.1 masking on an individual interrupt request........................... 156 5.8.5.2 special mask mode............................................................. 156 5.8.6 steering pci interrupts...................................................................... 156 5.9 advanced programmable interrupt controller (apic) (d31:f0) .............................. 157 5.9.1 interrupt handling ............................................................................ 157 5.9.2 interrupt mapping ............................................................................. 157 5.9.3 pci / pci express* message-based interrupts....................................... 158 5.9.4 ioxapic address remapping .............................................................. 158 5.9.5 external interrupt controller support................................................... 158 5.10 serial interrupt (d31:f0) ................................................................................. 159 5.10.1 start frame ..................................................................................... 159 5.10.2 data frames .................................................................................... 160 5.10.3 stop frame ...................................................................................... 160 5.10.4 specific interrupts not supported using serirq ................................... 160 5.10.5 data frame format ........................................................................... 161 5.11 real time clock (d31:f0)................................................................................. 162 5.11.1 update cycles .................................................................................. 162 5.11.2 interrupts ........................................................................................ 163 5.11.3 lockable ram ranges ........................................................................ 163 5.11.4 century rollover ............................................................................... 163 5.11.5 clearing battery-backed rtc ram....................................................... 163 5.12 processor interface (d31:f0) ............................................................................ 165 5.12.1 processor interface signals and vlw messages ..................................... 165 5.12.1.1 a20m# (mask a20) / a20gate ............................................ 165 5.12.1.2 init (initialization) ................ ............................................ 166 5.12.1.3 ferr# (numeric coprocessor error)..................................... 166 5.12.1.4 nmi (non-maskable interrupt)............................................. 167 5.12.1.5 processor power good (procpwrgd) .................................. 167 5.12.2 dual-processor issues ....................................................................... 167 5.12.2.1 usage differences.............................................................. 167 5.12.3 virtual legacy wire (vlw) messages ................................................... 167 5.13 power management ......................................................................................... 168 5.13.1 features .......................................................................................... 168 5.13.2 pch and system power states ............................................................ 168 5.13.3 system power planes ........................................................................ 170 5.13.4 smi#/sci generation ........................................................................ 171 5.13.4.1 pci express* sci............................................................... 173 5.13.4.2 pci express* hot-plug........................................................ 173 5.13.5 c-states .......................................................................................... 173 5.13.6 dynamic pci clock control (mobile only) ............................................. 173 5.13.6.1 conditions for checking the pci clock .................................. 173
6 datasheet 5.13.6.2 conditions for maintaining the pci clock................................ 174 5.13.6.3 conditions for stopping the pci clock ................................... 174 5.13.6.4 conditions for re-starting the pci clock................................ 174 5.13.6.5 lpc devices and clkrun# .................................................. 174 5.13.7 sleep states ..................................................................................... 174 5.13.7.1 sleep state overview ......................................................... 174 5.13.7.2 initiating sleep state ................ .......................................... 175 5.13.7.3 exiting sleep states ........................................................... 175 5.13.7.4 pci express* wake# signal and pme event message.............. 177 5.13.7.5 sx-g3-sx, handling power failures....................................... 178 5.13.7.6 deep s4/s5....................................................................... 179 5.13.8 event input signals and their usage .................................................... 180 5.13.8.1 pwrbtn# (power button) ................................................... 180 5.13.8.2 ri# (ring indicator) ........................................................... 181 5.13.8.3 pme# (pci power management event) .................................. 181 5.13.8.4 sys_reset# signal ........................................................... 182 5.13.8.5 thrmtrip# signal ............................................................. 182 5.13.9 alt access mode ............................................................................... 183 5.13.9.1 write only registers with read paths in alt access mode........ 184 5.13.9.2 pic reserved bits............................................................... 186 5.13.9.3 read only registers with write paths in alt access mode........ 186 5.13.10 system power supplies, planes, and signals ......................................... 187 5.13.10.1 power plane control with slp_s3#, slp_s4#, slp_s5#, slp_a# and slp_lan# ......................... 187 5.13.10.2 slp_s4# and suspend-to-ram sequencing........................... 187 5.13.10.3 pwrok signal ................................................................... 187 5.13.10.4 batlow# (battery low) (mobile only) ................................. 188 5.13.10.5 slp_lan# pin behavior ...................................................... 188 5.13.10.6 rtcrst# and srtcrst#.................................................... 188 5.13.11 clock generators............................................................................... 188 5.13.12 legacy power management theory of operation .................................... 189 5.13.12.1 apm power management (desktop only) ............................... 189 5.13.12.2 mobile apm power management (mobile only)........................ 189 5.13.13 reset behavior.................................................................................. 189 5.14 system management (d31:f0) .......................................................................... 192 5.14.1 theory of operation........................................................................... 192 5.14.1.1 detecting a system lockup ................................................. 192 5.14.1.2 handling an intruder .......................................................... 193 5.14.1.3 detecting improper flash programming ................................ 193 5.14.1.4 heartbeat and event reporting using smlink/smbus............... 193 5.14.2 tco modes ....................................................................................... 194 5.14.2.1 tco legacy/compatible mode.............................................. 194 5.14.2.2 advanced tco mode........................................................... 195 5.15 general purpose i/o (d31:f0) ........................................................................... 196 5.15.1 power wells...................................................................................... 196 5.15.2 smi# sci and nmi routing................................................................. 196 5.15.3 triggering ........................................................................................ 196 5.15.4 gpio registers lockdown ................................................................... 196 5.15.5 serial post codes over gpio.............................................................. 197 5.15.5.1 theory of operation ........................................................... 197 5.15.5.2 serial message format........................................................ 198 5.16 sata host controller (d31:f2, f5)..................................................................... 199 5.16.1 sata 6 gb/s support ......................................................................... 200 5.16.2 sata feature support........................................................................ 200 5.16.3 theory of operation........................................................................... 201 5.16.3.1 standard ata emulation ..................................................... 201 5.16.3.2 48-bit lba operation .......................................................... 201 5.16.4 sata swap bay support..................................................................... 201 5.16.5 hot plug operation ............................................................................ 201 5.16.5.1 low power device presence detection................................... 201 5.16.6 function level reset support (flr) ..................................................... 202 5.16.6.1 flr steps ......................................................................... 202 5.16.7 intel ? rapid storage technology configuration ..................................... 202 5.16.7.1 intel ? rapid storage manager raid option rom.................... 203 5.16.8 intel ? smart response technology...................................................... 203 5.16.9 power management operation............................................................. 203 5.16.9.1 power state mappings ........................................................ 203
datasheet 7 5.16.9.2 power state transitions ...................................................... 204 5.16.9.3 smi trapping (apm) ........................................................... 205 5.16.10 sata device presence ....................................................................... 205 5.16.11 sata led ........................................................................................ 206 5.16.12 ahci operation ................................................................................ 206 5.16.13 sgpio signals .................................................................................. 206 5.16.13.1 mechanism ....................................................................... 206 5.16.13.2 message format ................................................................ 207 5.16.13.3 led message type ............................................................. 208 5.16.13.4 sgpio waveform............................................................... 209 5.16.14 external sata .................................................................................. 210 5.17 high precision event timers.............................................................................. 210 5.17.1 timer accuracy................................................................................. 210 5.17.2 interrupt mapping ............................................................................. 211 5.17.3 periodic versus non-periodic modes ....... .............................................. 212 5.17.4 enabling the timers .......................................................................... 212 5.17.5 interrupt levels ................................................................................ 213 5.17.6 handling interrupts ........................................................................... 213 5.17.7 issues related to 64-bit timers with 32-bit processors .......................... 213 5.18 usb ehci host controllers (d29:f0 and d26:f0)................................................. 214 5.18.1 ehc initialization .............................................................................. 214 5.18.1.1 bios initialization.............................................................. 214 5.18.1.2 driver initialization ............................................................ 214 5.18.1.3 ehc resets ....................................................................... 214 5.18.2 data structures in main memory ......................................................... 214 5.18.3 usb 2.0 enhanced host controller dma ............................................... 215 5.18.4 data encoding and bit stuffing ........................................................... 215 5.18.5 packet formats................................................................................. 215 5.18.6 usb 2.0 interrupts and error conditions .............................................. 215 5.18.6.1 aborts on usb 2.0-initiated memory reads ........................... 216 5.18.7 usb 2.0 power management............................................................... 216 5.18.7.1 pause feature ................................................................... 216 5.18.7.2 suspend feature ............................................................... 216 5.18.7.3 acpi device states ............................................................ 216 5.18.7.4 acpi system states ........................................................... 217 5.18.8 usb 2.0 legacy keyboard operation.................................................... 217 5.18.9 usb 2.0 based debug port ................................................................. 217 5.18.9.1 theory of operation .......................................................... 218 5.18.10 ehci caching ................................................................................... 222 5.18.11 intel ? usb pre-fetch based pause ...................................................... 222 5.18.12 function level reset support (flr) ....... .............................................. 222 5.18.12.1 flr steps ......................................................................... 222 5.18.13 usb overcurrent protection................................................................ 223 5.19 integrated usb 2.0 rate matching hub .............................................................. 224 5.19.1 overview ......................................................................................... 224 5.19.2 architecture ..................................................................................... 224 5.20 smbus controller (d31:f3) ............................................................................... 225 5.20.1 host controller ................................................................................. 225 5.20.1.1 command protocols ........................................................... 226 5.20.2 bus arbitration ................................................................................. 229 5.20.3 bus timing....................................................................................... 230 5.20.3.1 clock stretching ................................................................ 230 5.20.3.2 bus time out (the pch as smbus master) ............................ 230 5.20.4 interrupts / smi# ............................................................................. 230 5.20.5 smbalert# ..................................................................................... 231 5.20.6 smbus crc generation and checking ...... ............................................ 231 5.20.7 smbus slave interface....................................................................... 232 5.20.7.1 format of slave write cycle ................................................ 233 5.20.7.2 format of read command .................................................. 234 5.20.7.3 slave read of rtc time bytes ............................................. 236 5.20.7.4 format of host notify command .......................................... 237 5.21 thermal management ...................................................................................... 238 5.21.1 thermal sensor ................................................................................ 238 5.21.1.1 internal thermal sensor operation ...................................... 238 5.21.2 pch thermal throttling...................................................................... 239 5.21.3 thermal reporting over system management link 1 interface (smlink1) . 240 5.21.3.1 supported addresses ......................................................... 241
8 datasheet 5.21.3.2 i 2 c write commands to the intel ? me .................................. 242 5.21.3.3 block read command ......................................................... 242 5.21.3.4 read data format .............................................................. 244 5.21.3.5 thermal data update rate .................................................. 244 5.21.3.6 temperature comparator and alert ...................................... 244 5.21.3.7 bios set up ...................................................................... 246 5.21.3.8 smbus rules ..................................................................... 246 5.21.3.9 case for considerations ...................................................... 247 5.22 intel ? high definition audio overview (d27:f0)..... .............................................. 249 5.22.1 intel ? high definition audio docking (mobile only) ................................ 249 5.22.1.1 dock sequence .................................................................. 249 5.22.1.2 exiting d3/crst# when docked .......................................... 250 5.22.1.3 cold boot/resume from s3 when docked.............................. 251 5.22.1.4 undock sequence............................................................... 251 5.22.1.5 normal undock .................................................................. 251 5.22.1.6 surprise undock ................................................................ 252 5.22.1.7 interaction between dock/undock and power management states .............................................................................. 252 5.22.1.8 relationship between hda_dock_rst# and hda_rst#......... 252 5.23 intel ? me and intel ? me firmware 7.0 ............................................................... 253 5.23.1 intel ? me requirements..................................................................... 254 5.24 serial peripheral interface (spi) ................. ....................................................... 255 5.24.1 spi supported feature overview ......................................................... 255 5.24.1.1 non-descriptor mode .......................................................... 255 5.24.1.2 descriptor mode................................................................. 255 5.24.2 flash descriptor ................................................................................ 256 5.24.2.1 descriptor master region .................................................... 258 5.24.3 flash access ..................................................................................... 259 5.24.3.1 direct access security ........................................................ 259 5.24.3.2 register access security ..................................................... 259 5.24.4 serial flash device compatibility requir ements .......... .......... ........... ...... 260 5.24.4.1 pch spi-based bios requirements ...................................... 260 5.24.4.2 integrated lan firmware spi flash requirements .................. 260 5.24.4.3 intel ? management engine firmware spi flash requirements.. 261 5.24.4.4 hardware sequencing requirements..................................... 261 5.24.5 multiple page write usage model ......................................................... 262 5.24.5.1 soft flash protection........................................................... 263 5.24.5.2 bios range write protection ............................................... 263 5.24.5.3 smi# based global write protection ..................................... 263 5.24.6 flash device configurations ................................................................ 263 5.24.7 spi flash device recommended pinout ................................................ 264 5.24.8 serial flash device package ................................................................ 264 5.24.8.1 common footprint usage model ........................................... 264 5.24.8.2 serial flash device package recommendations ...................... 265 5.24.9 pwm outputs (server/workstation only) .............................................. 265 5.24.10 tach inputs (server/workstation only) ............................................... 265 5.25 feature capability mechanism ...... ............ ........... ............ ........... .......... ............. 265 5.26 pch display interfaces and intel ? flexible display interconnect............................. 266 5.26.1 analog display interface characteristics . .............................................. 266 5.26.1.1 integrated ramdac............................................................ 267 5.26.1.2 ddc (display data channel) ................................................ 267 5.26.2 digital display interfaces.................................................................... 267 5.26.2.1 lvds (mobile only)............................................................. 267 5.26.2.2 high definition multimedia interface ..................................... 270 5.26.2.3 digital video interface (dvi)................................................ 271 5.26.2.4 displayport*...................................................................... 271 5.26.2.5 embedded displayport ........................................................ 272 5.26.2.6 displayport aux channel ..................................................... 272 5.26.2.7 displayport hot-plug detect (hpd) ....................................... 272 5.26.2.8 integrated audio over hdmi and displayport ......................... 272 5.26.2.9 serial digital video out (sdvo) ........................................... 272 5.26.3 mapping of digital display interface signals .......................................... 274 5.26.4 multiple display configurations............................................................ 275 5.26.5 high-bandwidth digital content protection (hdcp) ................................. 275 5.26.6 intel ? flexible display interconnect ..................................................... 276 5.27 intel ? virtualization technology .......................... .............................................. 276 5.27.1 intel ? vt-d objectives ....................................................................... 276
datasheet 9 5.27.2 intel ? vt-d features supported.......................................................... 276 5.27.3 support for function level reset (flr) in pch ...................................... 277 5.27.4 virtualization support for pchs ioxapic .............................................. 277 5.27.5 virtualization support for high precision event timer (hpet) .................. 277 6 ballout definition ................................................................................................... 279 6.1 desktop pch ballout ........................................................................................ 279 6.2 mobile pch ballout .......................................................................................... 290 6.3 mobile sff pch ballout .................................................................................... 302 7 package information ............................................................................................. 307 7.1 desktop pch package ...................................................................................... 307 7.2 mobile pch package......................................................................................... 309 7.3 mobile sff pch package................................................................................... 311 8 electrical characteristics ....................................................................................... 313 8.1 thermal specifications ..................................................................................... 313 8.1.1 desktop storage specifications and thermal design power (tdp) ............ 313 8.1.2 mobile storage specifications and th ermal design power (tdp) .............. 313 8.2 absolute maximum ratings............................................................................... 314 8.3 pch power supply range ................................................................................. 315 8.4 general dc characteristics ............................................................................... 315 8.5 display dc characteristics ......................... ....................................................... 328 8.6 ac characteristics ........................................................................................... 330 8.7 power sequencing and reset signal timings ....................................................... 347 8.8 power management timing diagrams................................................................. 350 8.9 ac timing diagrams ........................................................................................ 355 9 register and memory mapping ............................................................................... 365 9.1 pci devices and functions........................... ..................................................... 366 9.2 pci configuration map ..................................................................................... 367 9.3 i/o map ......................................................................................................... 367 9.3.1 fixed i/o address ranges .................................................................. 367 9.3.2 variable i/o decode ranges ............................................................... 370 9.4 memory map................................................................................................... 371 9.4.1 boot-block update scheme ................................................................ 373 10 chipset configur ation registers ............................................................................. 375 10.1 chipset configuration registers (memory space) ................................................. 375 10.1.1 cir0chipset initialization register 0 ................................................. 377 10.1.2 rpcroot port configuration register ................................................. 377 10.1.3 rpfnroot port function number and hide for pci express* root ports register .............................................................. 378 10.1.4 flrstatfunction level reset pending status register ........................ 379 10.1.5 trsrtrap status register ............................................................... 380 10.1.6 trcrtrapped cycle register ............................................................ 380 10.1.7 twdrtrapped write data register ................................................... 381 10.1.8 iotrni/o trap register (0C3).......................................................... 381 10.1.9 v0ctlvirtual channel 0 resource control register.............................. 382 10.1.10 v0stsvirtual channel 0 resource status register............................... 382 10.1.11 v1ctlvirtual channel 1 resource control register.............................. 383 10.1.12 v1stsvirtual channel 1 resource status register............................... 383 10.1.13 recroot error command register .................................................... 384 10.1.14 lcaplink capabilities regi ster ............. .......... ...................... ............ 384 10.1.15 lctllink control register................................................................ 385 10.1.16 lstslink status register ................................................................ 385 10.1.17 dlctl2dmi link control 2 register .................................................. 385 10.1.18 dmicdmi control register ............................................................... 386 10.1.19 tctltco configuration register....................................................... 386 10.1.20 d31ipdevice 31 interrupt pin register .............................................. 387 10.1.21 d30ipdevice 30 interrupt pin register .............................................. 388 10.1.22 d29ipdevice 29 interrupt pin register .............................................. 388 10.1.23 d28ipdevice 28 interrupt pin register .............................................. 388 10.1.24 d27ipdevice 27 interrupt pin register .............................................. 390 10.1.25 d26ipdevice 26 interrupt pin register .............................................. 390 10.1.26 d25ipdevice 25 interrupt pin register .............................................. 390 10.1.27 d22ipdevice 22 interrupt pin register .............................................. 391 10.1.28 d31irdevice 31 interrupt route register .......................................... 392
10 datasheet 10.1.29 d29irdevice 29 interrupt route register........................................... 393 10.1.30 d28irdevice 28 interrupt route register........................................... 394 10.1.31 d27irdevice 27 interrupt route register........................................... 395 10.1.32 d26irdevice 26 interrupt route register........................................... 396 10.1.33 d25irdevice 25 interrupt route register........................................... 397 10.1.34 d22irdevice 22 interrupt route register........................................... 398 10.1.35 oicother interrupt control register .................................................. 399 10.1.36 prstspower and reset status register ............................................. 400 10.1.37 pm_cfgpower management configuration register ............................. 401 10.1.38 deep_s4_poldeep s4/s5 from s4 power policies register ........................................................................................... 402 10.1.39 deep_s5_poldeep s4/s5 from s5 power policies register ........................................................................................... 402 10.1.40 pmsync_cfgpmsync configuration regist er ..................................... 403 10.1.41 rcrtc configuration register .......................................................... 404 10.1.42 hptchigh precision timer configuration register ................................ 404 10.1.43 gcsgeneral control and status register ............................................ 405 10.1.44 bucbacked up control register ........................................................ 407 10.1.45 fdfunction disable register ............... .............................................. 407 10.1.46 cgclock gating register .................................................................. 409 10.1.47 fdswfunction disable sus well register.. ......................................... 410 10.1.48 dispbdfdisplay bus, device and function initialization register ......................................................................... 411 10.1.49 fd2function disable 2 register ........................................................ 411 10.1.50 miscctlmiscellaneous control register ............................................. 412 10.1.51 usbocm1overcurrent map register 1 ............................................... 413 10.1.52 usbocm2overcurrent map register 2 ............................................... 414 10.1.53 rmhwkctlrate matching hub wake control register.......................... 415 11 pci-to-pci bridge registers (d30:f0) .................................................................... 417 11.1 pci configuration registers (d30:f0) ................................................................. 417 11.1.1 vid vendor identification register (pci-pcid30:f0) ......................... 418 11.1.2 did device identification register (pci-pcid30:f0).......................... 418 11.1.3 pcicmdpci command (pci-pcid30:f0).......................................... 418 11.1.4 pstspci status register (pci-pcid30:f0)....................................... 419 11.1.5 ridrevision identification register (pci-pcid30:f0) ........................ 421 11.1.6 ccclass code register (pci-pcid30:f0) ......................................... 421 11.1.7 pmltprimary master latency timer register (pci-pcid30:f0) ............................................................................ 422 11.1.8 headtypheader type register (pci-pcid30:f0) .............................. 422 11.1.9 bnumbus number register (pci-pcid30:f0) ................................... 422 11.1.10 smltsecondary master latency timer register (pci-pcid30:f0) ............................................................................ 423 11.1.11 iobase_limiti/o base and limit register (pci-pcid30:f0) ............................................................................ 423 11.1.12 secstssecondary status register (pci-pcid30:f0) ......................... 424 11.1.13 membase_limitmemory base and limit register (pci-pcid30:f0) ............................................................................ 425 11.1.14 pref_mem_base_limitprefetchable memory base and limit register (pci-pcid30:f0) .................................................. 425 11.1.15 pmbu32prefetchable memory base upper 32 bits register (pci-pcid30:f0) ................................................................ 426 11.1.16 pmlu32prefetchable memory limit upper 32 bits register (pci-pcid30:f0) ................................................................ 426 11.1.17 cappcapability list poin ter register (pci-pcid30:f0 ) ............. .......... 426 11.1.18 intrinterrupt information register (pci-pcid30:f0)........................ 426 11.1.19 bctrlbridge control register (pci-pcid30:f0) ............................... 427 11.1.20 spdhsecondary pci device hiding register (pci-pcid30:f0) ............................................................................ 428 11.1.21 dtcdelayed transaction control register (pci-pcid30:f0) ............................................................................ 429 11.1.22 bpsbridge proprietary status register (pci-pcid30:f0) ............................................................................ 430 11.1.23 bpcbridge policy configuration register (pci-pcid30:f0) ............................................................................ 431 11.1.24 svcapsubsystem vendor capability register (pci-pcid30:f0) ............................................................................ 432
datasheet 11 11.1.25 svidsubsystem vendor ids register (pci-pcid30:f0) ..................... 433 12 gigabit lan configuration registers ...................................................................... 435 12.1 gigabit lan configuration registers (gigabit lan d25:f0)................................................................................... 435 12.1.1 vidvendor identification register (gigabit land25:f0) ...................................................................... 436 12.1.2 diddevice identification register (gigabit land25:f0) ...................................................................... 436 12.1.3 pcicmdpci command register (gigabit land25:f0) ...................................................................... 437 12.1.4 pcistspci status register (gigabit land25:f0) ...................................................................... 438 12.1.5 ridrevision identification register (gigabit land25:f0) ...................................................................... 439 12.1.6 ccclass code register (gigabit land25:f0) ...................................................................... 439 12.1.7 clscache line size register (gigabit land25:f0) ...................................................................... 439 12.1.8 pltprimary latency timer register (gigabit land25:f0) ...................................................................... 439 12.1.9 headtypheader type register (gigabit land25:f0) ...................................................................... 439 12.1.10 mbaramemory base address register a (gigabit land25:f0) ...................................................................... 440 12.1.11 mbarbmemory base address register b (gigabit land25:f0) ...................................................................... 440 12.1.12 mbarcmemory base address register c (gigabit land25:f0) ...................................................................... 441 12.1.13 svidsubsystem vendor id register (gigabit land25:f0) ...................................................................... 441 12.1.14 sidsubsystem id register (gigabit land25:f0) ...................................................................... 441 12.1.15 erbaexpansion rom base address register (gigabit land25:f0) ...................................................................... 441 12.1.16 cappcapabilities list pointer register (gigabit land25:f0) ...................................................................... 442 12.1.17 intrinterrupt information register (gigabit land25:f0) ...................................................................... 442 12.1.18 mlmgmaximum latency/minimum grant register (gigabit land25:f0) ...................................................................... 442 12.1.19 clist1capabilities list register 1 (gigabit land25:f0) ...................................................................... 442 12.1.20 pmcpci power management capabilities register (gigabit land25:f0) ...................................................................... 443 12.1.21 pmcspci power management control and status register (gigabit land25:f0) .......................................................... 444 12.1.22 drdata register (gigabit land25:f0) ...................................................................... 445 12.1.23 clist2capabilities list register 2 (gigabit land25:f0) ...................................................................... 445 12.1.24 mctlmessage control register (gigabit land25:f0) ...................................................................... 445 12.1.25 maddlmessage address low register (gigabit land25:f0) ...................................................................... 446 12.1.26 maddhmessage address high register (gigabit land25:f0) ...................................................................... 446 12.1.27 mdatmessage data register (gigabit land25:f0) ...................................................................... 446 12.1.28 flrcapfunction level reset capability (gigabit land25:f0) ...................................................................... 446 12.1.29 flrclvfunction level reset capability length and version register (gigabit land25:f0)..... .......................................... 447 12.1.30 devctrldevice control register (gigabit land25:f0) ..................... 447
12 datasheet 13 lpc interface bridge registers (d31:f0) ............................................................... 449 13.1 pci configuration registers (lpc i/fd31:f0) .................................................... 449 13.1.1 vidvendor identification register (lpc i/fd31:f0) ........................... 450 13.1.2 diddevice identification register (lpc i/fd31:f0) ........................... 450 13.1.3 pcicmdpci command register (lpc i/fd31:f0) ............................. 451 13.1.4 pcistspci status register (lpc i/fd31:f0) .................................... 451 13.1.5 ridrevision identification register (lpc i/fd31:f0) ......................... 452 13.1.6 piprogramming interface register (lpc i/fd31:f0) .......................... 452 13.1.7 sccsub class code register (lpc i/fd31:f0) .................................. 453 13.1.8 bccbase class code register (lpc i/fd31:f0)................................. 453 13.1.9 pltprimary latency timer register (lpc i/fd31:f0)......................... 453 13.1.10 headtypheader type register (lpc i/fd31:f0)............................... 453 13.1.11 sssub system identifiers register (lpc i/fd31:f0).......................... 454 13.1.12 pmbaseacpi base address register (lpc i/fd31:f0) ....................... 454 13.1.13 acpi_cntlacpi control register (lpc i/f d31:f0) .......................... 455 13.1.14 gpiobasegpio base address register (lpc i/f d31:f0) .................. 455 13.1.15 gcgpio control register (lpc i/f d31:f0) ..................................... 456 13.1.16 pirq[n]_routpirq[a,b,c, d] routing control register (lpc i/fd31:f0) ............................................................................. 457 13.1.17 sirq_cntlserial irq control register (lpc i/fd31:f0) ............................................................................. 458 13.1.18 pirq[n]_routpirq[e,f,g,h] routing control register (lpc i/fd31:f0) ............................................................................. 459 13.1.19 lpc_ibdfioxapic bus:device:function (lpc i/fd31:f0) ............................................................................. 459 13.1.20 lpc_hnbdfhpet n bus:device:function (lpc i/fd31:f0) ............................................................................. 460 13.1.21 lpc_i/o_deci/o decode ranges register (lpc i/fd31:f0) ............................................................................. 461 13.1.22 lpc_enlpc i/f enables register (lpc i/fd31:f0)............................. 462 13.1.23 gen1_declpc i/f generic decode range 1 register (lpc i/fd31:f0) ............................................................................. 463 13.1.24 gen2_declpc i/f generic decode range 2 register (lpc i/fd31:f0) ............................................................................. 463 13.1.25 gen3_declpc i/f generic decode range 3 register (lpc i/fd31:f0) ............................................................................. 464 13.1.26 gen4_declpc i/f generic decode range 4 register (lpc i/fd31:f0) ............................................................................. 464 13.1.27 ulkmc usb legacy keyboard / mouse control register (lpc i/fd31:f0)...................................................... 465 13.1.28 lgmr lpc i/f generic memory range register (lpc i/fd31:f0) ............................................................................. 466 13.1.29 bios_sel1bios select 1 register (lpc i/fd31:f0) ............................................................................. 467 13.1.30 bios_sel2bios select 2 register (lpc i/fd31:f0) ............................................................................. 468 13.1.31 bios_dec_en1bios decode enable register (lpc i/fd31:f0)................................................................. 469 13.1.32 bios_cntlbios control register (lpc i/fd31:f0) ............................................................................. 471 13.1.33 fdcapfeature detect ion capability id register (lpc i/fd31:f0) ............................................................................. 472 13.1.34 fdlenfeature detection capability length register (lpc i/fd31:f0) ............................................................................. 472 13.1.35 fdverfeature detection version register (lpc i/fd31:f0) ............................................................................. 472 13.1.36 fvecidxfeature vector index register (lpc i/fd31:f0) ............................................................................. 472 13.1.37 fvecdfeature vector data register (lpc i/fd31:f0) ............................................................................. 473 13.1.38 feature vector space ......................................................................... 473 13.1.38.1 fvec0feature vector register 0 ........................................ 473 13.1.38.2 fvec1feature vector register 1 ........................................ 474 13.1.38.3 fvec2feature vector register 2 ........................................ 474 13.1.38.4 fvec3feature vector register 3 ........................................ 475 13.1.39 rcbaroot complex base address register (lpc i/fd31:f0) ............................................................................. 475
datasheet 13 13.2 dma i/o registers........................................................................................... 476 13.2.1 dmabase_cadma base and current address registers ....................... 477 13.2.2 dmabase_ccdma base and current count registers.......................... 478 13.2.3 dmamem_lpdma memory low page registers ................................... 478 13.2.4 dmacmddma command register ..................................................... 479 13.2.5 dmastadma status register ........................................................... 479 13.2.6 dma_wrsmskdma write single mask register .................................. 480 13.2.7 dmach_modedma channel mode register........................................ 480 13.2.8 dma clear byte pointer register ......................................................... 481 13.2.9 dma master clear register ................................................................. 481 13.2.10 dma_clmskdma clear mask register ............................................... 481 13.2.11 dma_wrmskdma write all mask register ......................................... 482 13.3 timer i/o registers ......................................................................................... 482 13.3.1 tcwtimer control word register ..................................................... 483 13.3.2 sbyte_fmtinterval timer status byte format register ....................... 485 13.3.3 counter access ports register............................................................. 486 13.4 8259 interrupt controller (pic) registers ........................................................... 486 13.4.1 interrupt controller i/o map............................................................... 486 13.4.2 icw1initialization command word 1 regi ster .................................... 487 13.4.3 icw2initialization command word 2 regi ster .................................... 488 13.4.4 icw3master controller initialization command word 3 register................................................................................ 488 13.4.5 icw3slave controller initialization command word 3 register................................................................................ 489 13.4.6 icw4initialization command word 4 regi ster .................................... 489 13.4.7 ocw1operational control word 1 (interrupt mask) register........................................................................................... 490 13.4.8 ocw2operational control word 2 regist er ........................................ 490 13.4.9 ocw3operational control word 3 regist er ........................................ 491 13.4.10 elcr1master controller edge/level triggered register ........................ 492 13.4.11 elcr2slave controller edge/level triggered register.......................... 493 13.5 advanced programmable interrupt controller (apic)............................................ 494 13.5.1 apic register map ............................................................................ 494 13.5.2 indindex register.......................................................................... 494 13.5.3 datdata register........................................................................... 495 13.5.4 eoireoi register ........................................................................... 495 13.5.5 ididentification register.................. ................................................ 496 13.5.6 verversion register ....................................................................... 496 13.5.7 redir_tblredirection table register ............................................... 497 13.6 real time clock registers................................................................................. 499 13.6.1 i/o register address map .................................................................. 499 13.6.2 indexed registers ............................................................................. 500 13.6.2.1 rtc_regaregister a ....................................................... 501 13.6.2.2 rtc_regbregister b (general configuration) ..................... 502 13.6.2.3 rtc_regcregister c (flag register) ................................. 503 13.6.2.4 rtc_regdregister d (flag register) ................................. 503 13.7 processor interface registers ............................................................................ 504 13.7.1 nmi_scnmi status and control register ........................................... 504 13.7.2 nmi_ennmi enable (and real time clock index) register........................................................................................... 505 13.7.3 port92fast a20 and init register .................................................... 505 13.7.4 coproc_errcoprocessor error register ........................................... 505 13.7.5 rst_cntreset control register ....................................................... 506 13.8 power management registers ........................................................................... 507 13.8.1 power management pci configuration registers (pmd31:f0)................................................................................... 507 13.8.1.1 gen_pmcon_1general pm configuration 1 register (pmd31:f0) ................................................................... 508 13.8.1.2 gen_pmcon_2general pm configuration 2 register (pmd31:f0) ................................................................... 509 13.8.1.3 gen_pmcon_3general pm configuration 3 register (pmd31:f0) ................................................................... 510 13.8.1.4 gen_pmcon_lockgeneral power management configuration lock register................................................. 514 13.8.1.5 cir4chipset initialization register 4 (pmd31:f0).............. 514 13.8.1.6 bm_break_en_2 register #2 (pmd31:f0)......................... 514 13.8.1.7 bm_break_en register (pmd31:f0) ................................. 515
14 datasheet 13.8.1.8 pmirpower management initialization register (pmd31:f0) 516 13.8.1.9 gpio_routgpio routing control register (pmd31:f0).................................................................... 516 13.8.2 apm i/o decode register.................................................................... 517 13.8.2.1 apm_cntadvanced power management control port register............................................................................ 517 13.8.2.2 apm_stsadvanced power management status port register............................................................................ 517 13.8.3 power management i/o registers ........................................................ 518 13.8.3.1 pm1_stspower management 1 status register ................... 519 13.8.3.2 pm1_enpower management 1 enable register..................... 521 13.8.3.3 pm1_cntpower management 1 control register .................. 522 13.8.3.4 pm1_tmrpower management 1 timer register .................... 523 13.8.3.5 gpe0_stsgeneral purpose event 0 status register.............. 524 13.8.3.6 gpe0_engeneral purpose event 0 enables register ............. 527 13.8.3.7 smi_ensmi control and enable register............................. 529 13.8.3.8 smi_stssmi status register ............................................ 531 13.8.3.9 alt_gp_smi_enalternate gpi smi enable register.............. 533 13.8.3.10 alt_gp_smi_stsalternate gpi smi status register ............ 534 13.8.3.11 gpe_cntlgeneral purpose control register ........................ 534 13.8.3.12 devact_sts device activity status register ..................... 535 13.8.3.13 pm2_cntpower management 2 control register .................. 535 13.9 system management tco registers ................................................................... 536 13.9.1 tco_rldtco timer reload and current value register ....................... 536 13.9.2 tco_dat_intco data in register .................................................... 537 13.9.3 tco_dat_outtco data out register ............................................... 537 13.9.4 tco1_ststco1 status register ....................................................... 537 13.9.5 tco2_ststco2 status register ....................................................... 539 13.9.6 tco1_cnttco1 control register ...................................................... 540 13.9.7 tco2_cnttco2 control register ...................................................... 541 13.9.8 tco_message1 and tco_message2 registers .................................... 541 13.9.9 tco_wdcnttco watchdog control register ...................................... 542 13.9.10 sw_irq_gensoftware irq generation register ................................. 542 13.9.11 tco_tmrtco timer initial value register.......................................... 542 13.10 general purpose i/o registers ........................................................................... 543 13.10.1 gpio_use_selgpio use select register ........................................... 544 13.10.2 gp_io_selgpio input/output select register .................................... 544 13.10.3 gp_lvlgpio level for input or output register .................................. 545 13.10.4 gpo_blinkgpo blink enable register ............................................... 545 13.10.5 gp_ser_blinkgp serial blink register.............................................. 546 13.10.6 gp_sb_cmdstsgp serial blink command status register ................................................................................. 546 13.10.7 gp_sb_datagp serial blink data register ......................................... 547 13.10.8 gpi_nmi_engpi nmi enable register ................................................ 547 13.10.9 gpi_nmi_stsgpi nmi status register............................................... 547 13.10.10 gpi_invgpio signal invert register.................................................. 548 13.10.11 gpio_use_sel2gpio use select 2 register ....................................... 548 13.10.12 gp_io_sel2gpio input/output select 2 register ............................... 549 13.10.13 gp_lvl2gpio level for input or output 2 register.............................. 549 13.10.14 gpio_use_sel3gpio use select 3 register ....................................... 550 13.10.15 gpio_sel3gpio input/output select 3 register ................................. 550 13.10.16 gp_lvl3gpio level for input or output 3 register.............................. 551 13.10.17 gp_rst_sel1gpio reset select register........................................... 551 13.10.18 gp_rst_sel2gpio reset select register........................................... 552 13.10.19 gp_rst_sel3gpio reset select register........................................... 552 14 sata controller registers (d31:f2) ....................................................................... 553 14.1 pci configuration registers (sataCd31:f2) ........................................................ 553 14.1.1 vidvendor identification register (satad31:f2).............................. 555 14.1.2 diddevice identification register (satad31:f2) .............................. 555 14.1.3 pcicmdpci command register (sataCd31:f2) .................................. 555 14.1.4 pcists pci status register (sataCd31:f2) ...................................... 556 14.1.5 ridrevision identification register (satad31:f2) ............................ 557 14.1.6 piprogramming interface register (sataCd31:f2) .............................. 557 14.1.6.1 when sub class code register (d31:f2:offset 0ah) = 01h...... 557 14.1.6.2 when sub class code register (d31:f2:offset 0ah) = 04h...... 557 14.1.6.3 when sub class code register (d31:f2:offset 0ah) = 06h...... 558
datasheet 15 14.1.7 sccsub class code register (sataCd31:f2) ..................................... 558 14.1.8 bccbase class code register (sataCd31:f2sataCd31:f2) ............................................................. 558 14.1.9 pmltprimary master latency timer register (sataCd31:f2) ................................................................................ 559 14.1.10 htypeheader type register (sataCd31:f2) ................................................................................ 559 14.1.11 pcmd_barprimary command block base address register (sataCd31:f2) .................................................................... 559 14.1.12 pcnl_barprimary control block base address register (sataCd31:f2) ................................................................................ 560 14.1.13 scmd_barsecondary command block base address register (sata d31:f2)..................................................................... 560 14.1.14 scnl_barsecondary control block base address register (sata d31:f2)..................................................................... 560 14.1.15 barlegacy bus master base address register (sataCd31:f2) ................................................................................ 561 14.1.16 abar/sidpba1ahci base address register/serial ata index data pair base address (sataCd31:f2) ...................................... 561 14.1.16.1 when scc is not 01h ......................................................... 561 14.1.16.2 when scc is 01h ............................................................... 562 14.1.17 svidsubsystem vendor identification register (sataCd31:f2) ................................................................................ 562 14.1.18 sidsubsystem identification register (sataCd31:f2)......................... 562 14.1.19 capcapabilities pointer register (sat aCd31:f2) ............. ......... .......... 562 14.1.20 int_lninterrupt line register (sataC d31:f2) ................................... 563 14.1.21 int_pninterrupt pin register (sataCd31:f2) .................................... 563 14.1.22 ide_timide timing register (sataCd31:f2) ..................................... 563 14.1.23 pidpci power management capability identification register (sataCd31:f2) .................................................................... 563 14.1.24 pcpci power management capabilities register (sataCd31:f2) ................................................................................ 564 14.1.25 pmcspci power management control and status register (sataCd31:f2) .................................................................... 565 14.1.26 msicimessage signal ed interrupt capability identification register (sataCd31:f2) ................................................. 566 14.1.27 msimcmessage signaled interrupt message control register (sataCd31:f2) ......................................................... 566 14.1.28 msima message signaled interrupt message address register (sataCd31:f2) ........................................................ 568 14.1.29 msimdmessage signaled interrupt message data register (sataCd31:f2) ............................................................ 568 14.1.30 mapaddress map register (sataCd31:f2)......................................... 569 14.1.31 pcsport control and status register (sataCd31:f2) .......................... 570 14.1.32 sclkcgsata clock gating control regist er ....................................... 572 14.1.33 sclkgcsata clock general configuration register............................. 572 14.1.34 satacr0sata capability register 0 (s ataCd31:f2)........... .......... ...... 573 14.1.35 satacr1sata capability register 1 (s ataCd31:f2)........... .......... ...... 574 14.1.36 flrcidflr capability id register (sataCd31:f2) .............................. 574 14.1.37 flrclvflr capability length and version register (sataCd31:f2) ................................................................................ 575 14.1.38 flrcflr control register (sataCd31:f2) ......................................... 575 14.1.39 atcapm trapping control register (sataCd31:f2)............................. 576 14.1.40 atsapm trapping status register (sataCd31:f2) .............................. 576 14.1.41 sp scratch pad register (sataCd31:f2) .............................................. 576 14.1.42 bfcsbist fis control/status register (sataCd31:f2)........................ 577 14.1.43 bftd1bist fis transmit data1 regist er (sataCd31:f2)..................... 579 14.1.44 bftd2bist fis transmit data2 regist er (sataCd31:f2)..................... 579 14.2 bus master ide i/o registers (d31:f2) .............................................................. 580 14.2.1 bmic[p,s]bus master ide command register (d31:f2)....................... 581 14.2.2 bmis[p,s]bus master ide status register (d31:f2) ............................ 582 14.2.3 bmid[p,s]bus master ide descriptor table pointer register (d31:f2) ............................................................................. 583 14.2.4 airahci index register (d31:f2) .................................................... 583 14.2.5 aidrahci index data register (d31:f2) ........................................... 583 14.3 serial ata index/data pair superset registers ... ................................................. 584 14.3.1 sindxserial ata index register (d31:f2) ......................................... 584
16 datasheet 14.3.2 sdataserial ata data register (d31:f2)........................................... 585 14.3.2.1 pxsstsserial ata status register (d31:f2)........................ 585 14.3.2.2 pxsctlserial ata control register (d31:f2) ....................... 586 14.3.2.3 pxserrserial ata error register (d31:f2).......................... 587 14.4 ahci registers (d31:f2) .................................................................................. 588 14.4.1 ahci generic host control registers (d31:f2) ...................................... 589 14.4.1.1 caphost capabilities register (d 31:f2) ........ .............. ........ 590 14.4.1.2 ghcglobal pch control register (d31:f2) .......................... 592 14.4.1.3 isinterrupt status register (d31:f2) ................................. 593 14.4.1.4 piports implemented register (d31:f2) ............................. 594 14.4.1.5 vsahci version register (d31:f2) .................................... 595 14.4.1.6 em_locenclosure management location register (d31:f2) .. 595 14.4.1.7 em_ctrlenclosure management control register (d31:f2) .. 596 14.4.1.8 cap2hba capa bilities extended register .... .............. .......... 597 14.4.1.9 vspvendor specific register (d31:f2)................................ 597 14.4.1.10 rstfintel ? rst feature capabilities regi ster...................... 598 14.4.2 port registers (d31:f2) ..................................................................... 599 14.4.2.1 pxclbport [5:0] command list base address register (d31:f2) .......................................................................... 602 14.4.2.2 pxclbuport [5:0] command list base address upper 32-bits register (d31:f2) ................................................... 602 14.4.2.3 pxfbport [5:0] fis base address register (d31:f2) ............. 602 14.4.2.4 pxfbuport [5:0] fis base address upper 32-bits register (d31:f2) .............................................................. 603 14.4.2.5 pxisport [5:0] interrupt status register (d31:f2) ............... 603 14.4.2.6 pxieport [5:0] interrupt enable register (d31:f2) ............... 605 14.4.2.7 pxcmdport [5:0] command register (d31:f2) .................... 606 14.4.2.8 pxtfdport [5:0] task file data register (d31:f2) ............... 609 14.4.2.9 pxsigport [5:0] signature register (d31:f2) ...................... 609 14.4.2.10 pxsstsport [5:0] serial ata status register (d31:f2) ......... 610 14.4.2.11 pxsctl port [5:0] serial ata control register (d31:f2) ...... 611 14.4.2.12 pxserrport [5:0] serial ata error register (d31:f2) ........... 612 14.4.2.13 pxsactport [5:0] serial ata active register (d31:f2) ......... 614 14.4.2.14 pxciport [5:0] command issue register (d31:f2) ............... 614 15 sata controller registers (d31:f5) ....................................................................... 615 15.1 pci configuration registers (sataCd31:f5) ........................................................ 615 15.1.1 vidvendor identification register (satad31:f5).............................. 616 15.1.2 diddevice identification register (satad31:f5) .............................. 616 15.1.3 pcicmdpci command register (sataCd31:f5) .................................. 617 15.1.4 pcists pci status register (sataCd31:f5) ...................................... 618 15.1.5 ridrevision identification register (satad31:f5) ............................ 618 15.1.6 piprogramming interface register (sataCd31:f5) .............................. 619 15.1.7 sccsub class code register (sataCd31:f5)...................................... 619 15.1.8 bccbase class code register (sataCd31:f5sataCd31:f5) ............................................................. 619 15.1.9 pmltprimary master latency timer register (sataCd31:f5)................................................................................. 620 15.1.10 pcmd_barprimary command block base address register (sataCd31:f5) .................................................................... 620 15.1.11 pcnl_barprimary control block base address register (sataCd31:f5)................................................................................. 620 15.1.12 scmd_barsecondary command block base address register (sata d31:f5) ..................................................................... 621 15.1.13 scnl_barsecondary control block base address register (sata d31:f5) ..................................................................... 621 15.1.14 barlegacy bus master base address register (sataCd31:f5)................................................................................. 622 15.1.15 sidpbasata index/data pair base address register (sataCd31:f5)................................................................................. 622 15.1.16 svidsubsystem vendor identification register (sataCd31:f5)................................................................................. 623 15.1.17 sidsubsystem identification register (sataCd31:f5) ......................... 623 15.1.18 capcapabilities pointer register (sat aCd31:f5)........ .......... ........... .... 623 15.1.19 int_lninterrupt line register (sataCd31:f5) ................................... 623 15.1.20 int_pninterrupt pin register (sataCd31:f5)..................................... 623 15.1.21 ide_timide timing register (sataCd31:f5) ..................................... 624
datasheet 17 15.1.22 pidpci power management capability identification register (sataCd31:f5) .................................................................... 624 15.1.23 pcpci power management capabilities register (sataCd31:f5) ................................................................................ 624 15.1.24 pmcspci power management control and status register (sataCd31:f5) .................................................................... 625 15.1.25 mapaddress map register (sataCd31:f5)......................................... 626 15.1.26 pcsport control and status register (sataCd31:f5) .......................... 627 15.1.27 satacr0 sata capability register 0 (sataCd31:f5)......... ........... ...... 628 15.1.28 satacr1 sata capability register 1 (sataCd31:f5)......... ........... ...... 628 15.1.29 flrcid flr capability id register (s ataCd31:f5) ..... .............. .......... 628 15.1.30 flrclv flr capability length and value register (sataCd31:f5) ........................................................... 629 15.1.31 flrctrl flr control register (sataCd31:f5) ................................... 629 15.1.32 atcapm trapping control register (sataCd31:f5)............................. 630 15.1.33 atcapm trapping control register (sataCd31:f5)............................. 630 15.2 bus master ide i/o registers (d31:f5) .............................................................. 631 15.2.1 bmic[p,s]bus master ide command register (d31:f5)....................... 632 15.2.2 bmis[p,s]bus master ide status register (d31:f5) ............................ 633 15.2.3 bmid[p,s]bus master ide descriptor table pointer register (d31:f5) ............................................................................. 633 15.3 serial ata index/data pair superset registers ... ................................................. 634 15.3.1 sindxsata index register (d31:f5) ................................................ 634 15.3.2 sdatasata index data register (d31:f5) ........................................ 634 15.3.2.1 pxsstsserial ata status register (d31:f5) ....................... 635 15.3.2.2 pxsctlserial ata control register (d31:f5) ...................... 636 15.3.2.3 pxserrserial ata error register (d31:f5) ......................... 637 16 ehci controller regist ers (d29:f0, d26:f0) .......................................................... 639 16.1 usb ehci configuration registers (usb ehcid29:f0, d26:f0) ........................................................................... 639 16.1.1 vidvendor identification register (usb ehcid29:f0, d26:f0)............................................................. 641 16.1.2 diddevice identification register (usb ehcid29:f0, d26:f0)............................................................. 641 16.1.3 pcicmdpci command register (usb ehcid29:f0, d26:f0)............................................................. 641 16.1.4 pcistspci status register (usb ehcid29:f0, d26:f0)............................................................. 643 16.1.5 ridrevision identification register (usb ehcid29:f0, d26:f0)............................................................. 644 16.1.6 piprogramming interface register (usb ehcid29:f0, d26:f0)............................................................. 644 16.1.7 sccsub class code register (usb ehcid29:f0, d26:f0)............................................................. 644 16.1.8 bccbase class code register (usb ehcid29:f0, d26:f0)............................................................. 644 16.1.9 pmltprimary master latency timer register (usb ehcid29:f0, d26:f0)............................................................. 645 16.1.10 headtypheader type register (usb ehcid29:f0, d26:f0)............................................................. 645 16.1.11 mem_basememory base address register (usb ehcid29:f0, d26:f0)............................................................. 645 16.1.12 svidusb ehci subsystem vendor id register (usb ehcid29:f0, d26:f0)............................................................. 646 16.1.13 sidusb ehci subsystem id register (usb ehcid29:f0, d26:f0)............................................................. 646 16.1.14 cap_ptrcapabilities pointer register (usb ehcid29:f0, d26:f0)............................................................. 646 16.1.15 int_lninterrupt line register (usb ehcid29:f0, d26:f0)............................................................. 646 16.1.16 int_pninterrupt pin register (usb ehcid29:f0, d26:f0)............................................................. 647 16.1.17 pwr_capidpci power management capability id register (usb ehcid29:f0, d26:f0) ................................................ 647 16.1.18 nxt_ptr1next item pointer #1 register (usb ehcid29:f0, d26:f0)............................................................. 647
18 datasheet 16.1.19 pwr_cappower management capabilities register (usb ehcid29:f0, d26:f0) ............................................................. 648 16.1.20 pwr_cntl_stspower management control/ status register (usb ehcid29:f0, d26:f0) ....................................... 649 16.1.21 debug_capiddebug port capability id register (usb ehcid29:f0, d26:f0) ............................................................. 650 16.1.22 nxt_ptr2next item pointer #2 register (usb ehcid29:f0, d26:f0) ............................................................. 650 16.1.23 debug_basedebug port base offset register (usb ehcid29:f0, d26:f0) ............................................................. 650 16.1.24 usb_relnumusb release number register (usb ehcid29:f0, d26:f0) ............................................................. 650 16.1.25 fl_adjframe length adjustment register (usb ehcid29:f0, d26:f0) ............................................................. 651 16.1.26 pwake_capport wa ke capability register (usb ehcid29:f0, d26:f0) ............................................................. 652 16.1.27 leg_ext_capusb ehci legacy support extended capability register (usb ehcid29:f0, d 26:f0) ......... .......... ........... .... 653 16.1.28 leg_ext_csusb ehci legacy support extended control / status register (usb ehcid29:f0, d26:f0) .......................... 654 16.1.29 special_smiintel specific usb 2.0 smi register (usb ehcid29:f0, d26:f0) ............................................................. 656 16.1.30 access_cntlaccess control register (usb ehcid29:f0, d26:f0) ............................................................. 657 16.1.31 ehciir1ehci initialization register 1 (usb ehcid29:f0, d26:f0) ............................................................. 658 16.1.32 ehciir2ehci initialization register 2 (usb ehcid29:f0, d26:f0) ...... 658 16.1.33 flr_cidfunction level reset capability id register (usb ehcid29:f0, d26:f0) ............................................................. 659 16.1.34 flr_nextfunction level reset next capability pointer register (usb ehcid29:f0, d26:f0) ...................................... 659 16.1.35 flr_clvfunction level reset capability length and version register (usb ehcid29:f0, d26:f0)...................................... 660 16.1.36 flr_ctrlfunction level reset control register (usb ehcid29:f0, d26:f0) ............................................................. 660 16.1.37 flr_stsfunction level reset status register (usb ehcid29:f0, d26:f0) ............................................................. 661 16.1.38 ehciir3ehci initialization register 3 (usb ehcid29:f0, d26:f0) ...... 661 16.1.39 ehciir4ehci initialization register 4 (usb ehcid29:f0, d26:f0) ...... 661 16.2 memory-mapped i/o registers .......................................................................... 662 16.2.1 host controller capability registers ......... ............ ........... ........ ............. 662 16.2.1.1 caplengthcap ability registers length register.................. 663 16.2.1.2 hciversionhost controller interface version number register............................................................................ 663 16.2.1.3 hcsparamshost controller stru ctural parameters register... 663 16.2.1.4 hccparamshost contro ller capability parameters register............................................................................ 664 16.2.2 host controller operational registers ................................................... 665 16.2.2.1 usb2.0_cmdusb 2.0 command register ........................... 666 16.2.2.2 usb2.0_stsusb 2.0 status register.................................. 669 16.2.2.3 usb2.0_intrusb 2.0 interrupt enable register .................. 671 16.2.2.4 frindexframe index register .......................................... 672 16.2.2.5 ctrldssegmentcontrol data structure segment register............................................................................ 673 16.2.2.6 periodiclistbaseperiodic frame list base address register............................................................................ 673 16.2.2.7 asynclistaddrcurrent asynchronous list address register............................................................................ 674 16.2.2.8 configflagconfigure flag register .................................. 674 16.2.2.9 portscport n status and contro l register ......................... 675 16.2.3 usb 2.0-based debug port registers ................................................... 680 16.2.3.1 cntl_stscontrol/status register...................................... 681 16.2.3.2 usbpidusb pids register ................................................ 683 16.2.3.3 databuf[7:0]data buffer bytes[7:0] register .................... 683 16.2.3.4 configconfiguration register........................................... 683
datasheet 19 17 integrated intel ? high definition audio controller registers ................................. 685 17.1 intel ? high definition audio controller registers (d27:f0).................................... 685 17.1.1 intel ? high definition audio pci configuration space (intel ? high definition audio d27:f0) ............................................... 685 17.1.1.1 vidvendor identification register (intel ? high definition audio controllerd27:f0) .................. 687 17.1.1.2 diddevice identification register (intel ? high definition audio controllerd27:f0) .................. 687 17.1.1.3 pcicmdpci command register (intel ? high definition audio controllerd27:f0) .................. 688 17.1.1.4 pcistspci status register (intel ? high definition audio controllerd27:f0) .................. 689 17.1.1.5 ridrevision identification register (intel ? high definition audio controllerd27:f0) .................. 689 17.1.1.6 piprogramming interface register (intel ? high definition audio controllerd27:f0) .................. 689 17.1.1.7 sccsub class code register (intel ? high definition audio controllerd27:f0) .................. 690 17.1.1.8 bccbase class code register (intel ? high definition audio controllerd27:f0) .................. 690 17.1.1.9 clscache line size register (intel ? high definition audio controllerd27:f0) .................. 690 17.1.1.10 ltlatency timer register (intel ? high definition audio controllerd27:f0) .................. 690 17.1.1.11 headtypheader type register (intel ? high definition audio controllerd27:f0) .................. 690 17.1.1.12 hdbarlintel ? high definition audio lower base address register (intel ? high definition audiod27:f0) .................... 691 17.1.1.13 hdbaruintel ? high definition audio upper base address register (intel ? high definition audio controllerd27:f0)...... 691 17.1.1.14 svidsubsystem vendor identification register (intel ? high definition audio controllerd27:f0) .................. 691 17.1.1.15 sidsubsystem identification register (intel ? high definition audio controllerd27:f0) .................. 692 17.1.1.16 capptrcapabilities pointer register (intel ? high definition audio controllerd27:f0) .................. 692 17.1.1.17 intlninterrupt line register (intel ? high definition audio controllerd27:f0) .................. 692 17.1.1.18 intpninterrupt pin register (intel ? high definition audio controllerd27:f0) .................. 692 17.1.1.19 hdctlintel ? high definition audio control register (intel ? high definition audio controllerd27:f0) .................. 693 17.1.1.20 hdinit1intel ? high definition audio initialization register 1 (intel ? high definition audio controllerd27:f0) .................. 693 17.1.1.21 dckctldocking control register (mobile only) (intel ? high definition audio controllerd27:f0) .................. 693 17.1.1.22 dckstsdocking stat us register (mobile only) (intel ? high definition audio controllerd27:f0) .................. 694 17.1.1.23 pidpci power management capability id register (intel ? high definition audio controllerd27:f0) .................. 694 17.1.1.24 pcpower management capabilities register (intel ? high definition audio controllerd27:f0) .................. 695 17.1.1.25 pcspower management control and status register (intel ? high definition audio controllerd27:f0) .................. 695 17.1.1.26 midmsi capability id register (intel ? high definition audio controllerd27:f0) .................. 696 17.1.1.27 mmcmsi message control register (intel ? high definition audio controllerd27:f0) .................. 696 17.1.1.28 mmlamsi message lower address register (intel ? high definition audio controllerd27:f0) .................. 697 17.1.1.29 mmuamsi message upper address register (intel ? high definition audio controllerd27:f0) .................. 697 17.1.1.30 mmdmsi message data register (intel ? high definition audio controllerd27:f0) .................. 697 17.1.1.31 pxidpci express* capability id register (intel ? high definition audio controllerd27:f0) .................. 697
20 datasheet 17.1.1.32 pxcpci express* capabilities register (intel ? high definition audio controllerd27:f0) .................. 698 17.1.1.33 devcapdevice capabilities register (intel ? high definition audio controllerd27:f0) .................. 698 17.1.1.34 devcdevice control register (intel ? high definition audio controllerd27:f0) .................. 699 17.1.1.35 devsdevice status register (intel ? high definition audio controllerd27:f0) .................. 700 17.1.1.36 vccapvirtual channel enhanced capability header (intel ? high definition audio controllerd27:f0) .................. 700 17.1.1.37 pvccap1port vc capability register 1 (intel ? high definition audio controllerd27:f0) .................. 701 17.1.1.38 pvccap2 port vc capability register 2 (intel ? high definition audio controllerd27:f0) .................. 701 17.1.1.39 pvcctl port vc control register (intel ? high definition audio controllerd27:f0) .................. 701 17.1.1.40 pvcstsport vc status register (intel ? high definition audio controllerd27:f0) .................. 702 17.1.1.41 vc0capvc0 resource capability register (intel ? high definition audio controllerd27:f0) .................. 702 17.1.1.42 vc0ctlvc0 resource control register (intel ? high definition audio controllerd27:f0) .................. 703 17.1.1.43 vc0stsvc0 resource status register (intel ? high definition audio controllerd27:f0) .................. 703 17.1.1.44 vcicapv ci resource capability register (intel ? high definition audio controllerd27:f0) .................. 704 17.1.1.45 vcictlvci resource control register (intel ? high definition audio controllerd27:f0) .................. 704 17.1.1.46 vcistsvci resource status register (intel ? high definition audio controllerd27:f0) .................. 705 17.1.1.47 rccaproot complex link declaration enhanced capability header register (intel ? high definition audio controllerd27:f0) .................. 705 17.1.1.48 esdelement self description register (intel ? high definition audio controllerd27:f0) .................. 705 17.1.1.49 l1desclink 1 description register (intel ? high definition audio controllerd27:f0) .................. 706 17.1.1.50 l1addllink 1 lower address register (intel ? high definition audio controllerd27:f0) .................. 706 17.1.1.51 l1addulink 1 upper address register (intel ? high definition audio controllerd27:f0) .................. 706 17.1.2 intel ? high definition audio memory mapped configuration registers (intel ? high definition audio d27:f0) .................................................. 707 17.1.2.1 gcapglobal capabilities register (intel ? high definition audio controllerd27:f0) .................. 711 17.1.2.2 vminminor version register (intel ? high definition audio controllerd27:f0) .................. 711 17.1.2.3 vmajmajor version register (intel ? high definition audio controllerd27:f0) .................. 711 17.1.2.4 outpayoutp ut payload capability register (intel ? high definition audio controllerd27:f0) .................. 712 17.1.2.5 inpayinput payload capability register (intel ? high definition audio controllerd27:f0) .................. 712 17.1.2.6 gctlglobal control register (intel ? high definition audio controllerd27:f0) .................. 713 17.1.2.7 wakeenwake enable register (intel ? high definition audio controllerd27:f0) .................. 714 17.1.2.8 statestsstate change status register (intel ? high definition audio controllerd27:f0) .................. 714 17.1.2.9 gstsglobal status register (intel ? high definition audio controllerd27:f0) .................. 715 17.1.2.10 outstr mpayoutput stream payload capability (intel ? high definition audio controllerd27:f0) .................. 715 17.1.2.11 instrmpayinput stream payload capability (intel ? high definition audio controllerd27:f0) .................. 715 17.1.2.12 intctlinterrupt control register (intel ? high definition audio controllerd27:f0) .................. 716
datasheet 21 17.1.2.13 intstsinterrupt status register (intel ? high definition audio controllerd27:f0) .................. 717 17.1.2.14 walclkwall clock counter register (intel ? high definition audio controllerd27:f0) .................. 717 17.1.2.15 ssyncstream synchronization register (intel ? high definition audio controllerd27:f0) .................. 718 17.1.2.16 corblbasecorb lowe r base address register (intel ? high definition audio controllerd27:f0) .................. 718 17.1.2.17 corbubasecorb uppe r base address register (intel ? high definition audio controllerd27:f0) .................. 719 17.1.2.18 corbwpcorb write pointer register (intel ? high definition audio controllerd27:f0) .................. 719 17.1.2.19 corbrpcorb read pointer register (intel ? high definition audio controllerd27:f0) .................. 719 17.1.2.20 corbctlcorb control register (intel ? high definition audio controllerd27:f0) .................. 720 17.1.2.21 corbstcorb status register (intel ? high definition audio controllerd27:f0) .................. 720 17.1.2.22 corbsizecorb size register intel ? high definition audio controllerd27:f0) ................... 720 17.1.2.23 rirblbaserirb lowe r base address register (intel ? high definition audio controllerd27:f0) .................. 721 17.1.2.24 rirbubaserirb upper base address register (intel ? high definition audio controllerd27:f0) .................. 721 17.1.2.25 rirbwprirb write pointer register (intel ? high definition audio controllerd27:f0) .................. 721 17.1.2.26 rintcntresponse interrupt count register (intel ? high definition audio controllerd27:f0) .................. 722 17.1.2.27 rirbctlrirb control register (intel ? high definition audio controllerd27:f0) .................. 722 17.1.2.28 rirbstsrirb status register (intel ? high definition audio controllerd27:f0) .................. 723 17.1.2.29 rirbsizerirb size register (intel ? high definition audio controllerd27:f0) .................. 723 17.1.2.30 icimmediate command register (intel ? high definition audio controllerd27:f0) .................. 723 17.1.2.31 irimmediate response register (intel ? high definition audio controllerd27:f0) .................. 724 17.1.2.32 icsimmediate command status register (intel ? high definition audio controllerd27:f0) .................. 724 17.1.2.33 dplbasedma position lower base address register (intel ? high definition audio controllerd27:f0) .................. 725 17.1.2.34 dpubasedma position upper base address register (intel ? high definition audio controllerd27:f0) .................. 725 17.1.2.35 sdctlstream descriptor control register (intel ? high definition audio controllerd27:f0) .................. 726 17.1.2.36 sdstsstream descriptor status register (intel ? high definition audio controllerd27:f0) .................. 727 17.1.2.37 sdlpibstream descriptor link position in buffer register (intel ? high definition audio controllerd27:f0)...... 728 17.1.2.38 sdcblstream descriptor cy clic buffer length register (intel ? high definition audio controllerd27:f0) .................. 728 17.1.2.39 sdlvistream descripto r last valid index register (intel ? high definition audio controllerd27:f0) .................. 729 17.1.2.40 sdfifowstream descriptor fifo watermark register (intel ? high definition audio controllerd27:f0) .................. 729 17.1.2.41 sdfifosstream descriptor fifo size register C input streams (intel ? high definition audio controllerd27:f0)...... 730 17.1.2.42 sdfifosstream descriptor fifo size register C output streams (intel ? high definition audio controllerd27:f0)...... 730 17.1.2.43 sdfmtstream descriptor format register (intel ? high definition audio controllerd27:f0) .................. 731 17.1.2.44 sdbdplstream descrip tor buffer descriptor list pointer lower base address register (intel ? high definition audio controllerd27:f0) .................. 732
22 datasheet 17.1.2.45 sdbdpustream descriptor buffer descriptor list pointer upper base address register (intel ? high definition audio controllerd27:f0) .................. 732 17.2 integrated digital display audio registers and verb ids ........................................ 733 17.2.1 configuration default register............... .............................................. 733 18 smbus controller registers (d31:f3) ..................................................................... 739 18.1 pci configuration registers (smbusd31:f3) ..................................................... 739 18.1.1 vidvendor identification register (smbusd31:f3)............................ 739 18.1.2 diddevice identification register (smbusd31:f3) ............................ 740 18.1.3 pcicmdpci command register (smbusd31:f3) ............................... 740 18.1.4 pcistspci status register (smbusd31:f3) ..................................... 741 18.1.5 ridrevision identification register (smbusd31:f3) .......................... 741 18.1.6 piprogramming interface register (smbusd31:f3) ........................... 742 18.1.7 sccsub class code register (smbusd31:f3)................................... 742 18.1.8 bccbase class code register (smbusd31:f3) ................................. 742 18.1.9 smbmbar0d31_f3_smbus memory base address 0 register (smbusd31:f3) ................................................................. 742 18.1.10 smbmbar1d31_f3_smbus memory base address 1 register (smbusd31:f3) ................................................................. 743 18.1.11 smb_basesmbus base address register (smbusd31:f3).............................................................................. 743 18.1.12 svidsubsystem vendor identification register (smbusd31:f2/f4) ......................................................................... 743 18.1.13 sidsubsystem identification register (smbusd31:f2/f4) ......................................................................... 744 18.1.14 int_lninterrupt line register (smbusd31:f3) ................................ 744 18.1.15 int_pninterrupt pin register (smbusd31:f3).................................. 744 18.1.16 hostchost configuration register (smbusd31:f3) .......................... 745 18.2 smbus i/o and memory mapped i/o registers ..................................................... 746 18.2.1 hst_stshost status register (smbusd31:f3) ................................. 747 18.2.2 hst_cnthost control register (smbusd31:f3) ............................... 748 18.2.3 hst_cmdhost command register (smbusd31:f3)........................... 750 18.2.4 xmit_slvatransmit slave address register (smbusd31:f3).............................................................................. 750 18.2.5 hst_d0host data 0 register (smbusd31:f3) .................................. 750 18.2.6 hst_d1host data 1 register (smbusd31:f3) .................................. 750 18.2.7 host_block_dbhost block data byte register (smbusd31:f3).............................................................................. 751 18.2.8 pecpacket error check (pec) register (smbusd31:f3).............................................................................. 751 18.2.9 rcv_slvareceive slave address register (smbusd31:f3).............................................................................. 752 18.2.10 slv_datareceive slave data register (smbusd31:f3) .................... 752 18.2.11 aux_stsauxiliary status register (smbusd31:f3) ... .............. .......... 752 18.2.12 aux_ctlauxiliary control register (smbusd31:f3) ......... ........... ...... 753 18.2.13 smlink_pin_ctlsmlink pin control register (smbusd31:f3).............................................................................. 753 18.2.14 smbus_pin_ctlsmbus pin control register (smbusd31:f3).............................................................................. 754 18.2.15 slv_stsslave status register (smbus d31:f3) ................................ 754 18.2.16 slv_cmdslave command register (smbusd31:f3) .......................... 755 18.2.17 notify_daddrnotify device address register (smbusd31:f3).............................................................................. 755 18.2.18 notify_dlownotify data low byte register (smbusd31:f3).............................................................................. 756 18.2.19 notify_dhighnotify data high byte register (smbusd31:f3).............................................................................. 756 19 pci express* conf iguration registers .................................................................... 757 19.1 pci express* configuration registers (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) ................................................... 757 19.1.1 vidvendor identification register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7)............................ 759 19.1.2 diddevice identification register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7)............................ 759
datasheet 23 19.1.3 pcicmdpci command register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 760 19.1.4 pcistspci status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 761 19.1.5 ridrevision identification register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 762 19.1.6 piprogramming interface register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 762 19.1.7 sccsub class code register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 762 19.1.8 bccbase class code register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 762 19.1.9 clscache line size register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 763 19.1.10 pltprimary latency timer register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 763 19.1.11 headtypheader type register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 763 19.1.12 bnumbus number register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 764 19.1.13 sltsecondary latency timer register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 764 19.1.14 iobli/o base and limit register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 764 19.1.15 sstssecondary status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 765 19.1.16 mblmemory base and limit register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 766 19.1.17 pmblprefetchable memory base and limit register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 766 19.1.18 pmbu32prefetchable memory base upper 32 bits register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ............... 767 19.1.19 pmlu32prefetchable memory limit upper 32 bits register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ............... 767 19.1.20 cappcapabilities list pointer register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 767 19.1.21 intrinterrupt information register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 768 19.1.22 bctrlbridge control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) ........................... 769 19.1.23 clistcapabilities list register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 770 19.1.24 xcappci express* capabilities register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 770 19.1.25 dcapdevice capabilities register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 771 19.1.26 dctldevice control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 772 19.1.27 dstsdevice status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 773 19.1.28 lcaplink capabilities register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 774 19.1.29 lctllink control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 776 19.1.30 lstslink status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 777 19.1.31 slcapslot capabilities register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 778 19.1.32 slctlslot control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 779 19.1.33 slstsslot status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 780 19.1.34 rctlroot control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 781 19.1.35 rstsroot status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) .................................... 781
24 datasheet 19.1.36 dcap2device ca pabilities 2 register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 782 19.1.37 dctl2device control 2 register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 782 19.1.38 lctl2link control 2 register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 783 19.1.39 lsts2link status 2 register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 784 19.1.40 midmessage signaled interrupt identifiers register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 784 19.1.41 mcmessage signaled interrupt message control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 784 19.1.42 mamessage signaled interrupt message address register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) ........................ 785 19.1.43 mdmessage signaled interrupt message data register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 785 19.1.44 svcapsubsystem vendor capability register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 785 19.1.45 svidsubsystem vendor identification register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 785 19.1.46 pmcappower management capability register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 786 19.1.47 pmcpci power management capabilities register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 786 19.1.48 pmcspci power management control and status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) ........................ 787 19.1.49 mpc2miscellaneous port configuration register 2 (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 788 19.1.50 mpcmiscellaneous port configuration register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 789 19.1.51 smscssmi/sci status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 791 19.1.52 rpdcgenroot port dynamic clock gating enable register (pci expressd28:f0/f1/f2/f3/f4/f5/f6/f7) .......................... 792 19.1.53 pecr1pci express* configuration register 1 (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 792 19.1.54 pecr3pci express* configuration register 3 (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 793 19.1.55 uesuncorrectable error status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 794 19.1.56 uemuncorrectable error mask register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 795 19.1.57 uev uncorrectable error severity register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 796 19.1.58 ces correctable error status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 797 19.1.59 cem correctable error mask register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 797 19.1.60 aecc advanced error capabilities and control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 798 19.1.61 res root error status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 798 19.1.62 pecr2 pci express* configuration register 2 (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 799 19.1.63 peetm pci express* extended test mode register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 799 19.1.64 pec1 pci express* configuration register 1 (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7)..................................... 799 20 high precision event timer registers ..................................................................... 801 20.1 memory mapped registers ................................................................................ 801 20.1.1 gcap_idgeneral capabilities and identification register ...................... 803 20.1.2 gen_confgeneral configuration register.......................................... 803 20.1.3 gintr_stageneral interrupt status regi ster ..................................... 804 20.1.4 main_cntmain counter value register.............................................. 804 20.1.5 timn_conftimer n configuration and ca pabilities register .. .......... ...... 805 20.1.6 timn_comptimer n comparator value register .................................. 808
datasheet 25 20.1.7 timern_procmsg_routt imer n processor message interrupt rout register ...................................................................... 809 21 serial peripheral interface (spi) ........................................................................... 811 21.1 serial peripheral interface memory mapped configuration registers ....................... 811 21.1.1 bfpr Cbios flash primary region register (spi memory mapped configuration registers)...................................... 813 21.1.2 hsfshardware sequencing flash status register (spi memory mapped configuration registers)...................................... 813 21.1.3 hsfchardware sequencing flash control register (spi memory mapped configuration registers)...................................... 815 21.1.4 faddrflash address register (spi memory mapped configuration registers)...................................... 815 21.1.5 fdata0flash data 0 register (spi memory mapped configuration registers)...................................... 816 21.1.6 fdatanflash data [n] register (spi memory mapped configuration registers)...................................... 816 21.1.7 frapflash regions access permissions register (spi memory mapped configuration registers)...................................... 817 21.1.8 freg0flash region 0 (flash descriptor) register (spi memory mapped configuration registers)...................................... 818 21.1.9 freg1flash region 1 (bios descriptor) register (spi memory mapped configuration registers)...................................... 818 21.1.10 freg2flash region 2 (intel ? me) register (spi memory mapped configuration registers)...................................... 819 21.1.11 freg3flash region 3 (gbe) register (spi memory mapped configuration registers)...................................... 819 21.1.12 freg4flash region 4 (platform data) register (spi memory mapped configuration registers)...................................... 820 21.1.13 pr0protected range 0 register (spi memory mapped configuration registers)...................................... 820 21.1.14 pr1protected range 1 register (spi memory mapped configuration registers)...................................... 821 21.1.15 pr2protected range 2 register (spi memory mapped configuration registers)...................................... 822 21.1.16 pr3protected range 3 register (spi memory mapped configuration registers)...................................... 823 21.1.17 pr4protected range 4 register (spi memory mapped configuration registers)...................................... 824 21.1.18 ssfssoftware sequencing flash status register (spi memory mapped configuration registers)...................................... 825 21.1.19 ssfcsoftware sequencing flash control register (spi memory mapped configuration registers)...................................... 826 21.1.20 preopprefix opcode configuration register (spi memory mapped configuration registers)...................................... 827 21.1.21 optypeopcode type configuration register (spi memory mapped configuration registers)...................................... 827 21.1.22 opmenuopcode menu configuration register (spi memory mapped configuration registers)...................................... 828 21.1.23 bbarbios base address configuration register (spi memory mapped configuration registers)...................................... 829 21.1.24 fdocflash descriptor ob servability control register (spi memory mapped configuration registers)...................................... 829 21.1.25 fdodflash descriptor observability data register (spi memory mapped configuration registers)...................................... 830 21.1.26 afcadditional flash control register (spi memory mapped configuration registers)...................................... 830 21.1.27 lvscc host lower vendor spec ific component capabilities register (spi memory mapped configuration registers)...................................... 830 21.1.28 uvscc host upper vendor specific componen t capabilities register (spi memory mapped configuration registers)...................................... 832 21.1.29 fpb flash partition boundary register (spi memory mapped configuration registers)...................................... 833 21.1.30 srdl soft reset data lock register (spi memory mapped configuration registers)...................................... 834 21.1.31 srdc soft reset data control register (spi memory mapped configuration registers)...................................... 834
26 datasheet 21.1.32 srd soft reset data register (spi memory mapped configuration registers) ...................................... 834 21.2 flash descriptor records................................................................................... 835 21.3 oem section ................................................................................................... 835 21.4 gbe spi flash program registers ....................................................................... 835 21.4.1 glfpr Cgigabit lan flash primary region register (gbe lan memory mapped configuration registers) ............................... 836 21.4.2 hsfshardware sequencing flash status register (gbe lan memory mapped configuration registers) ............................... 836 21.4.3 hsfchardware sequencing flash control register (gbe lan memory mapped configuration registers) ............................... 838 21.4.4 faddrflash address register (gbe lan memory mapped configuration registers) ............................... 838 21.4.5 fdata0flash data 0 register (gbe lan memory mapped configuration registers) ............................... 839 21.4.6 frapflash regions access permissions register (gbe lan memory mapped configuration registers) ............................... 839 21.4.7 freg0flash region 0 (flash descriptor) register (gbe lan memory mapped configuration registers) ............................... 840 21.4.8 freg1flash region 1 (bios descriptor) register (gbe lan memory mapped configuration registers) ............................... 840 21.4.9 freg2flash region 2 (intel ? me) register (gbe lan memory mapped configuration registers) ............................... 840 21.4.10 freg3flash region 3 (gbe) register (gbe lan memory mapped configuration registers) ............................... 841 21.4.11 pr0protected range 0 register (gbe lan memory mapped configuration registers) ............................... 841 21.4.12 pr1protected range 1 register (gbe lan memory mapped configuration registers) ............................... 842 21.4.13 ssfssoftware sequencing flash status register (gbe lan memory mapped configuration registers) ............................... 843 21.4.14 ssfcsoftware sequencing flash control register (gbe lan memory mapped configuration registers) ............................... 844 21.4.15 preopprefix opcode configuration register (gbe lan memory mapped configuration registers) ............................... 845 21.4.16 optypeopcode type configuration register (gbe lan memory mapped configuration registers) ............................... 845 21.4.17 opmenuopcode menu configuration register (gbe lan memory mapped configuration registers) ............................... 846 22 thermal sensor registers (d31:f6) ....................................................................... 847 22.1 pci bus configuration registers......................................................................... 847 22.1.1 vidvendor identification register ..................................................... 848 22.1.2 diddevice identification register...................................................... 848 22.1.3 cmdcommand register ................................................................... 848 22.1.4 stsstatus register ......................................................................... 849 22.1.5 ridrevision identification register...... .............................................. 849 22.1.6 pi programming interface register.................................................... 849 22.1.7 sccsub class code register ............................................................ 850 22.1.8 bccbase class code register ........................................................... 850 22.1.9 clscache line size register ............................................................ 850 22.1.10 ltlatency timer register................................................................. 850 22.1.11 htypeheader type register ............................................................. 850 22.1.12 tbarthermal base register ............................................................. 851 22.1.13 tbarhthermal base high dword register ......................................... 851 22.1.14 svidsubsystem vendor id register .................................................. 851 22.1.15 sidsubsystem id register............................................................... 852 22.1.16 cap_ptrcapabilities pointer register .... ............ ........... ........ ............. 852 22.1.17 intlninterrupt line register............................................................ 852 22.1.18 intpninterrupt pin register ............................................................. 852 22.1.19 tbarbbios assigned thermal base address register .......................... 853 22.1.20 tbarbhbios assigned thermal base high dword register ........................................................................................... 853 22.1.21 pidpci power management capability id register............ ......... .......... 853 22.1.22 pcpower management capabilities regist er ........... ............ ........... ...... 854 22.1.23 pcspower management control and stat us register............................ 854
datasheet 27 22.2 thermal memory mapped configuration registers (thermal sensor C d31:f26) ............................................................................ 855 22.2.1 tsiuthermal sensor in use register .... ............................................ 856 22.2.2 tsethermal sensor enable register.................................................. 856 22.2.3 tssthermal sensor status register ...... ............................................ 856 22.2.4 tstrthermal sensor thermometer read register .............................. 857 22.2.5 tsttpthermal sensor temperature trip point register........................................................................................... 857 22.2.6 tscothermal sensor catastrophic lock-down register........................................................................................... 858 22.2.7 tsesthermal sensor error status regist er ........................................ 859 22.2.8 tsgpenthermal sensor general purpose event enable register ................................................................................ 860 22.2.9 tspcthermal sensor policy control register ...................................... 861 22.2.10 ptapch temperature adjust register................................................ 862 22.2.11 trcthermal reporting control register............................................. 862 22.2.12 aealert enable register................................................................... 863 22.2.13 ptlprocessor temperature limit register .......................................... 863 22.2.14 ptv processor temperature value register ....................................... 863 22.2.15 ttthermal throttling register .......................................................... 864 22.2.16 phlpch hot level register .............................................................. 864 22.2.17 tspienthermal sensor pci interrupt enable register.......................... 865 22.2.18 tslockthermal sensor register lock control register........................ 866 22.2.19 tc2thermal compares 2 register..................................................... 866 22.2.20 dtvdimm temperature values register ............................................ 867 22.2.21 itvinternal temperature values register .......................................... 867 23 intel ? management engine subsys tem registers (d22:f[3:0]) ............................. 869 23.1 first intel ? management engine interface (intel ? mei) configuration registers (intel ? mei 1 d22:f0) ................................................................................. 869 23.1.1 pci configuration registers (intel ? mei 1d22:f0) .............................. 869 23.1.1.1 vidvendor identification register (intel ? mei 1d22:f0)...................................................... 870 23.1.1.2 diddevice identification register (intel ? mei 1d22:f0)...................................................... 870 23.1.1.3 pcicmdpci command register (intel ? mei 1d22:f0)...................................................... 871 23.1.1.4 pcistspci status register (intel ? mei 1d22:f0)...................................................... 871 23.1.1.5 ridrevision identification register (intel ? mei 1d22:f0)...................................................... 872 23.1.1.6 ccclass code register (intel ? mei 1d22:f0)...................................................... 872 23.1.1.7 htypeheader type register (intel ? mei 1d22:f0)...................................................... 872 23.1.1.8 mei0_mbarmei0 mmio base address register (intel ? mei 1d22:f0)...................................................... 872 23.1.1.9 svidsubsystem vendor id register (intel ? mei 1d22:f0)...................................................... 873 23.1.1.10 sidsubsystem id register (intel ? mei 1d22:f0)...................................................... 873 23.1.1.11 cappcapabilities list pointer register (intel ? mei 1d22:f0)...................................................... 873 23.1.1.12 intrinterrupt information register (intel ? mei 1d22:f0)...................................................... 873 23.1.1.13 hfshost firmware status register (intel ? mei 1d22:f0)...................................................... 874 23.1.1.14 me_umaintel ? management engine uma register (intel ? mei 1d22:f0)...................................................... 874 23.1.1.15 gmesgeneral intel ? me status register (intel ? mei 1d22:f0)...................................................... 875 23.1.1.16 h_gshost general status register (intel ? mei 1d22:f0)...................................................... 875 23.1.1.17 pidpci power management capability id register (intel ? mei 1d22:f0)...................................................... 875 23.1.1.18 pcpci power management capabilities register (intel ? mei 1d22:f0)...................................................... 875
28 datasheet 23.1.1.19 pmcspci power management control and status register (intel ? mei 1d22:f0) .......................................... 876 23.1.1.20 midmessage signaled interrupt identifiers register (intel ? mei 1d22:f0) ...................................................... 876 23.1.1.21 mcmessage signaled interrupt message control register (intel ? mei 1d22:f0) ...................................................... 877 23.1.1.22 mamessage signaled interrupt message address register (intel ? mei 1d22:f0) ...................................................... 877 23.1.1.23 muamessage signaled interrupt upper address register (intel ? mei 1d22:f0) ...................................................... 877 23.1.1.24 mdmessage signaled interrupt message data register (intel ? mei 1d22:f0) ...................................................... 877 23.1.1.25 hidmmei interrupt delivery mode register (intel ? mei 1d22:f0) ...................................................... 878 23.1.1.26 heresintel ? mei extend register status (intel ? mei 1d22:f0) ...................................................... 878 23.1.1.27 herxintel ? mei extend register dwx (intel ? mei 1d22:f0) ...................................................... 879 23.1.2 mei0_mbarintel ? mei 1 mmio registers ........................................... 879 23.1.2.1 h_cb_wwhost circular buffer write window register (intel ? mei 1 mmio register) .............................................. 879 23.1.2.2 h_csrhost control status register (intel ? mei 1 mmio register) .............................................. 880 23.1.2.3 me_cb_rwintel ? me circular buffer read window register (intel ? mei 1 mmio register) .............................................. 881 23.1.2.4 me_csr_haintel ? me control status host access register (intel ? mei 1 mmio register) .............................................. 881 23.2 second intel ? management engine interface (intel ? mei 2) configuration registers (intel ? mei 2d22:f1) .................................................................................... 882 23.2.1 pci configuration registers (intel ? mei 2d22:f2)............................... 882 23.2.1.1 vidvendor identification register (intel ? mei 2d22:f1) ...................................................... 883 23.2.1.2 diddevice identification register (intel ? mei 2d22:f1) ...................................................... 883 23.2.1.3 pcicmdpci command register (intel ? mei 2d22:f1) ...................................................... 884 23.2.1.4 pcistspci status register (intel ? mei 2d22:f1) ...................................................... 884 23.2.1.5 ridrevision identification register (intel ? mei 2d22:f1) ...................................................... 885 23.2.1.6 ccclass code register (intel ? mei 2d22:f1) ...................................................... 885 23.2.1.7 htypeheader type register (intel ? mei 2d22:f1) ...................................................... 885 23.2.1.8 mei_mbarintel ? mei mmio base address register (intel ? mei 2d22:f1) ...................................................... 885 23.2.1.9 svidsubsystem vendor id register (intel ? mei 2d22:f1) ...................................................... 886 23.2.1.10 sidsubsystem id register (intel ? mei 2d22:f1) ...................................................... 886 23.2.1.11 cappcapabilities list pointer register (intel ? mei 2d22:f1) ...................................................... 886 23.2.1.12 intrinterrupt information register (intel ? mei 2d22:f1) ...................................................... 886 23.2.1.13 hfshost firmware status register (intel ? mei 2d22:f1) ...................................................... 887 23.2.1.14 gmesgeneral intel ? me status register (intel ? mei 2d22:f1) ...................................................... 887 23.2.1.15 h_gshost general status register (intel ? mei 2d22:f1) ...................................................... 887 23.2.1.16 pidpci power management capability id register (intel ? mei 2d22:f1) ...................................................... 888 23.2.1.17 pcpci power management capabilities register (intel ? mei 2d22:f1) ...................................................... 888 23.2.1.18 pmcspci power management control and status register (intel ? mei 2d22:f1) .......................................... 888
datasheet 29 23.2.1.19 midmessage signaled interrupt identifiers register (intel ? mei 2d22:f1)...................................................... 889 23.2.1.20 mcmessage signaled interrupt message control register (intel ? mei 2d22:f1)...................................................... 889 23.2.1.21 mamessage signaled interrupt message address register (intel ? mei 2d22:f1)...................................................... 889 23.2.1.22 muamessage signaled interrupt upper address register (intel ? mei 2d22:f1)...................................................... 890 23.2.1.23 mdmessage signaled interrupt message data register (intel ? mei 2d22:f1)...................................................... 890 23.2.1.24 hidmintel ? mei interrupt delivery mode register (intel ? mei 2d22:f1)...................................................... 890 23.2.1.25 heresintel ? mei extend register status (intel ? mei 2d22:f1)...................................................... 891 23.2.1.26 herxintel ? mei extend register dwx (intel ? mei 2d22:f1)...................................................... 891 23.2.2 mei1_mbarintel ? mei 2 mmio registers .......................................... 892 23.2.2.1 h_cb_wwhost circular buffer write window (intel ? mei 2 mmio register) ............................................. 892 23.2.2.2 h_csrhost control status register (intel ? mei 2 mmio register) ............................................. 893 23.2.2.3 me_cb_rwintel ? me circular buffer read window register (intel ? mei 2 mmio register) ............................................. 894 23.2.2.4 me_csr_haintel ? me control status host access register (intel ? mei 2 mmio register) ............................................. 894 23.3 ide redirect ider registers (ider d22:f2) .................................................... 895 23.3.1 pci configuration registers (iderd22:f2)......................................... 895 23.3.1.1 vidvendor identification re gister (iderd22:f2) .............. 896 23.3.1.2 diddevice identification register (iderd22:f2)............... 896 23.3.1.3 pcicmd pci command register (iderd22:f2)................. 896 23.3.1.4 pcistspci device status register (iderd22:f2) ............. 897 23.3.1.5 ridrevision identification register (iderd22:f2)............. 897 23.3.1.6 ccclass codes register (iderd22:f2) ............................ 897 23.3.1.7 clscache line size register (iderd22:f2) ..................... 897 23.3.1.8 pcmdbaprimary command block io bar register (iderd22:f2) .................................................... 898 23.3.1.9 pctlbaprimary control block base address register (iderd22:f2) .................................................... 898 23.3.1.10 scmdbasecondary command block base address register (iderd22:f2) .................................................... 898 23.3.1.11 sctlbasecondary control block base address register (iderd22:f2) .................................................... 899 23.3.1.12 lbarlegacy bus master base address register (iderd22:f2) ................................................................ 899 23.3.1.13 svidsubsystem vendor id register (iderd22:f2) ........... 899 23.3.1.14 sidsubsystem id register (iderd22:f2)........................ 899 23.3.1.15 cappcapabilities list pointer register (iderd22:f2) ................................................................ 900 23.3.1.16 intrinterrupt information register (iderd22:f2) ................................................................ 900 23.3.1.17 pidpci power management capability id register (iderd22:f2) ................................................................ 900 23.3.1.18 pcpci power management capabilities register (iderd22:f2) ................................................................ 901 23.3.1.19 pmcspci power management control and status register (iderd22:f2) .................................................... 901 23.3.1.20 midmessage signal ed interrupt capability id register (iderd22:f2) .................................................... 902 23.3.1.21 mcmessage signaled interrupt message control register (iderd22:f2) .................................................... 902 23.3.1.22 mamessage signaled interrupt message address register (iderd22:f2) .................................................... 902 23.3.1.23 maumessage signaled interrupt message upper address register (iderd22:f2) ........................................ 902 23.3.1.24 mdmessage signaled interrupt message data register (iderd22:f2) .................................................... 903 23.3.2 ider bar0 registers ......................................................................... 903
30 datasheet 23.3.2.1 idedataide data register (iderd22:f2)........................ 904 23.3.2.2 ideerd1ide error register dev1 (iderd22:f2)................................................................. 904 23.3.2.3 ideerd0ide error register dev0 (iderd22:f2)................................................................. 905 23.3.2.4 idefride features register (iderd22:f2)................................................................. 905 23.3.2.5 idesciride sector count in register (iderd22:f2)................................................................. 905 23.3.2.6 idescor1ide sector count out register device 1 register (iderd22:f2) .................................................... 906 23.3.2.7 idescor0ide sector count out register device 0 register (iderd22:f2).................................................. 906 23.3.2.8 idesnor0ide sector number out register device 0 register (iderd22:f2)........................................ 906 23.3.2.9 idesnor1ide sector number out register device 1 register (iderd22:f2)........................................ 907 23.3.2.10 idesniride sector number in register (iderd22:f2)................................................................. 907 23.3.2.11 idecliride cylinder low in register (iderd22:f2)................................................................. 907 23.3.2.12 idclor1ide cylinder low out register device 1 register (iderd22:f2) .................................................... 908 23.3.2.13 idclor0ide cylinder low out register device 0 register (iderd22:f2) .................................................... 908 23.3.2.14 idchor0ide cylinder high out register device 0 register (iderd22:f2) .................................................... 908 23.3.2.15 idchor1ide cylinder high out register device 1 register (iderd22:f2) .................................................... 909 23.3.2.16 idechiride cylinder high in register (iderd22:f2)................................................................. 909 23.3.2.17 idedhiride drive/head in register (iderd22:f2)................................................................. 909 23.3.2.18 iddhor1ide drive head out register device 1 register (iderd22:f2) .................................................... 910 23.3.2.19 iddhor0ide drive head out register device 0 register (iderd22:f2) .................................................... 910 23.3.2.20 idesd0ride status device 0 register (iderd22:f2)................................................................. 911 23.3.2.21 idesd1ride status device 1 register (iderd22:f2)................................................................. 912 23.3.2.22 idecride command register (iderd22:f2) .................... 912 23.3.3 ider bar1 registers ......................................................................... 913 23.3.3.1 iddcride device control register (iderd22:f2) ............. 913 23.3.3.2 idasride alternate status register (iderd22:f2) ........... 913 23.3.4 ider bar4 registers ......................................................................... 914 23.3.4.1 idepbmcride primary bus master command register (iderd22:f2) .................................................... 915 23.3.4.2 idepbmds0ride primary bus master device specific 0 register (iderd22:f2) ...................................... 915 23.3.4.3 idepbmsride primary bus master status register (iderd22:f2) .................................................... 916 23.3.4.4 idepbmds1ride primary bus master device specific 1 register (iderd22:f2) ...................................... 916 23.3.4.5 idepbmdtpr0ide primary bus master descriptor table pointer byte 0 register (iderd22:f2) ....................... 916 23.3.4.6 idepbmdtpr1ide primary bus master descriptor table pointer byte 1 register (iderd22:f2) ....................... 917 23.3.4.7 idepbmdtpr2ide primary bus master descriptor table pointer byte 2 register (iderd22:f2) ....................... 917 23.3.4.8 idepbmdtpr3ide primary bus master descriptor table pointer byte 3 register (iderd22:f2) ....................... 917 23.3.4.9 idesbmcride secondary bus master command register (iderd22:f2) .................................................... 918 23.3.4.10 idesbmds0ride secondary bus master device specific 0 register (iderd22:f2) ...................................... 918
datasheet 31 23.3.4.11 idesbmsride secondary bus master status register (iderd22:f2) .................................................... 919 23.3.4.12 idesbmds1ride secondary bus master device specific 1 register (iderd22:f2)...................................... 919 23.3.4.13 idesbmdtpr0ide secondary bus master descriptor table pointer byte 0 register (iderd22:f2) ....................... 919 23.3.4.14 idesbmdtpr1ide secondary bus master descriptor table pointer byte 1 register (iderd22:f2) ....................... 920 23.3.4.15 idesbmdtpr2ide secondary bus master descriptor table pointer byte 2 register (iderd22:f2) ....................... 920 23.3.4.16 idesbmdtpr3ide secondary bus master descriptor table pointer byte 3 register (iderd22:f2) ....................... 920 23.4 serial port for remote keyboard and text (kt) redirection (kt d22:f3) ............................................................................... 921 23.4.1 pci configuration registers (kt d22:f3) .......................................... 921 23.4.1.1 vidvendor identification regi ster (ktd22:f3).................. 922 23.4.1.2 diddevice identification register (ktd22:f3) .................. 922 23.4.1.3 cmdcommand register (ktd22:f3)............ ................... 922 23.4.1.4 stsdevice status register (ktd22:f3) ........................... 923 23.4.1.5 ridrevision id register (ktd22:f3)............................... 923 23.4.1.6 ccclass codes register (ktd22:f3) ............................... 923 23.4.1.7 clscache line size register (ktd22:f3)......................... 924 23.4.1.8 ktibakt io block base address register (ktd22:f3).................................................................... 924 23.4.1.9 ktmbakt memory block base address register (ktd22:f3).................................................................... 924 23.4.1.10 svidsubsystem vendor id register (ktd22:f3) .............. 925 23.4.1.11 sidsubsystem id register (ktd22:f3) ........................... 925 23.4.1.12 capcapabilities pointer regist er (ktd22:f3)..... ........... .... 925 23.4.1.13 intrinterrupt information register (ktd22:f3) ............... 925 23.4.1.14 pidpci power management capability id register (ktd22:f3).................................................................... 926 23.4.1.15 pcpci power management capabilities id register (ktd22:f3).................................................................... 926 23.4.1.16 midmessage signal ed interrupt capability id register (ktd22:f3) ....................................................... 927 23.4.1.17 mcmessage signaled interrupt message control register (ktd22:f3) ....................................................... 927 23.4.1.18 mamessage signaled interrupt message address register (ktd22:f3) ....................................................... 927 23.4.1.19 maumessage signaled interrupt message upper address register (ktd22:f3) ........................................... 928 23.4.1.20 mdmessage signaled interrupt message data register (ktd22:f3) ....................................................... 928 23.4.2 kt io/memory mapped device registers .............................................. 928 23.4.2.1 ktrxbrkt receive buffer register (ktd22:f3) ................ 929 23.4.2.2 ktthrkt transmit holding re gister (ktd22:f3) .............. 929 23.4.2.3 ktdllrkt divisor latch lsb register (ktd22:f3) ............ 929 23.4.2.4 ktierkt interrupt enable register (ktd22:f3) ................ 930 23.4.2.5 ktdlmrkt divisor latch msb register (ktd22:f3)........... 930 23.4.2.6 ktiirkt interrupt identification register (ktd22:f3).................................................................... 931 23.4.2.7 ktfcrkt fifo control register (ktd22:f3)..................... 931 23.4.2.8 ktlcrkt line control register (ktd22:f3) ..................... 932 23.4.2.9 ktmcrkt modem control register (ktd22:f3) ................ 932 23.4.2.10 ktlsrkt line status register (ktd22:f3)....................... 933 23.4.2.11 ktmsrkt modem status register (ktd22:f3).................. 934
32 datasheet figures 2-1 pch interface signals block diagram (not all si gnals are on all skus)..........................56 2-2 example external rtc circuit.................................................................................92 4-1 pch high-level clock diagram ........................ ..................................................... 115 5-1 generation of serr# to platform ......................................................................... 126 5-2 lpc interface diagram ........................................................................................ 136 5-3 pch dma controller............................................................................................ 141 5-4 dma request assertion through ldrq# ................................................................ 144 5-5 tco legacy/compatible mode smbus configuration ................................................ 194 5-6 advanced tco mode ........................................................................................... 195 5-7 serial post over gpio reference circuit ................................................................. 197 5-8 flow for port enable / device present bits.............................................................. 205 5-9 serial data transmitted over the sgpio interface ................................................... 209 5-10 ehci with usb 2.0 with rate matching hub ........................................................... 224 5-11 pch intel ? management engine high-level block diagram ...................................... 254 5-12 flash descriptor sections .................................................................................... 257 5-13 analog port characteristics ......................... ......................................................... 266 5-14 lvds signals and swing voltage .......................................................................... 268 5-15 lvds clock and data relationship ........................................................................ 268 5-16 panel power sequencing ..................................................................................... 269 5-17 hdmi overview.................................................................................................. 270 5-18 displayport overview.......................................................................................... 271 5-19 sdvo conceptual block diagram ..................... ..................................................... 273 6-1 desktop pch ballout (top view - upper left) ......................................................... 279 6-2 desktop pch ballout (top view - lower left) ......................................................... 280 6-3 desktop pch ballout (top view - upper right) ....................................................... 281 6-4 desktop pch ballout (top view - lower right) ....................................................... 282 6-5 mobile pch ballout (top view - upper left)............................................................ 290 6-6 mobile pch ballout (top view - lower left)............................................................ 291 6-7 mobile pch ballout (top view - upper right).......................................................... 292 6-8 mobile pch ballout (top view - lower right).......................................................... 293 6-9 mobile sff pch package (top view C upper left) ................................................... 302 6-10 mobile sff pch package (top view C lower left) ................................................... 303 6-11 mobile sff pch package (top view C upper right) ................................................. 304 6-12 mobile sff pch package (top view C lower right) ................................................. 305 7-1 desktop pch package drawing............................................................................. 308 7-2 mobile pch package drawing ............................................................................... 310 7-3 mobile sff pch package drawing ......................................................................... 312 8-1 g3 w/rtc loss to s4/s5 (with deep s4/s5 support) timing diagram ....................... 350 8-2 g3 w/rtc loss to s4/s5 (without deep s4/s5 support) timing diagram .................. 350 8-3 s5 to s0 timing diagram .................................................................................... 351 8-4 s3/m3 to s0 timing diagram ............................................................................... 352 8-5 s5/moff - s5/m3 timing diagram ......................................................................... 352 8-6 s0 to s5 timing diagram .................................................................................... 353 8-7 s4/s5 to deep s4/s5 to g3 w/ rtc loss timing diagram ........................................ 354 8-8 drampwrok timing diagram.............................................................................. 354 8-9 clock cycle time................................................................................................ 355 8-10 transmitting position (data to strobe) ........... ....................................................... 355 8-11 clock timing...................................................................................................... 355 8-13 setup and hold times......................................................................................... 356 8-14 float delay........................................................................................................ 356 8-15 pulse width ....................................................................................................... 356 8-12 valid delay from rising clock edge ................ ....................................................... 356 8-16 output enable delay........................................................................................... 357 8-17 usb rise and fall times ...................................................................................... 357 8-18 usb jitter ......................................................................................................... 357 8-19 usb eop width .................................................................................................. 358 8-20 smbus transaction ............................................................................................. 358 8-21 smbus timeout.................................................................................................. 358 8-22 spi timings ....................................................................................................... 359 8-23 intel ? high definition audio input and output timings ............................................ 359 8-24 dual channel interface timings............................................................................ 360 8-25 dual channel interface timings............................................................................ 360 8-26 lvds load and transition times .......................................................................... 360 8-27 transmitting position (data to strobe) ........... ....................................................... 361 8-28 pci express transmitter eye................................................................................ 361
datasheet 33 8-29 pci express receiver eye.................................................................................... 362 8-30 measurement points for differential waveforms. .. .................................................. 363 8-31 pch test load ................................................................................................... 364 8-32 controller link receive timings ........................................................................... 364 8-33 controller link receive slew rate ........................................................................ 364 tables 1-1 industry specifications ......................................................................................... 42 1-2 desktop intel ? 6 series chipset skus .................................................................... 51 1-3 mobile intel ? 6 series chipset skus....................................................................... 52 1-4 server/workstation intel ? c200 series chipset skus ............................................... 53 2-1 direct media interface signals ............................................................................... 57 2-2 pci express* signals............................................................................................ 57 2-3 pci interface signals............................................................................................ 58 2-4 serial ata interface signals .................................................................................. 60 2-5 lpc interface signals ........................................................................................... 63 2-6 interrupt signals ................................................................................................. 63 2-7 usb interface signals........................................................................................... 64 2-8 power management interface signals ..................................................................... 65 2-9 processor interface signals ................................................................................... 69 2-10 sm bus interface signals ...................................................................................... 69 2-11 system management interface signals ................................................................... 69 2-12 real time clock interface ..................................................................................... 70 2-13 miscellaneous signals ........................................................................................... 70 2-14 intel ? high definition audio link signals................................................................. 72 2-15 controller link signals.......................................................................................... 73 2-16 serial peripheral interface (spi ) signals.................................................................. 73 2-17 thermal signals................................................................................................... 73 2-18 testability signals................................................................................................ 74 2-19 clock interface signals ......................................................................................... 74 2-20 lvds interface signals ......................................................................................... 77 2-21 analog display interface signals ............................................................................ 78 2-22 intel ? flexible display interface signals.................................................................. 78 2-23 digital display interface signals............................................................................. 79 2-24 general purpose i/o signals.................................................................................. 82 2-25 manageability signals ..... .......... ........... .......... ...................... ............ ......... ............ 86 2-26 power and ground signals .................................................................................... 87 2-27 functional strap definitions..... .............................................................................. 89 3-1 integrated pull-up and pull-down resistors ......... .................................................... 93 3-2 power plane and states for output and i/o signals for desktop configurations ............ 95 3-3 power plane and states for output and i/o signals for mobile configurations ............. 101 3-4 power plane for input signals for desktop configurations ........................................ 107 3-5 power plane for input signals for mobile config urations .......................................... 110 4-1 pch clock inputs ............................................................................................... 113 4-2 clock outputs ................................................................................................... 114 4-3 pch plls .......................................................................................................... 116 4-4 ssc blocks ....................................................................................................... 117 5-1 pci bridge initiator cycle types........................................................................... 120 5-2 type 1 address format....................................................................................... 122 5-3 msi versus pci irq actions................................................................................. 124 5-4 lan mode support ............................................................................................. 131 5-5 lpc cycle types supported ................................................................................. 137 5-6 start field bit definitions ........................... ......................................................... 137 5-7 cycle type bit definitions ................................................................................... 138 5-8 transfer size bit definition.................................................................................. 138 5-9 sync bit definition ............................................................................................ 138 5-10 dma transfer size ............................................................................................. 142 5-11 address shifting in 16-bit i/o dma transfers......................................................... 143 5-12 counter operating modes ................................................................................... 148 5-13 interrupt controller core connections................................................................... 150 5-14 interrupt status registers................................................................................... 151 5-15 content of interrupt vector byte .......................................................................... 151 5-16 apic interrupt mapping1 .................................................................................... 157 5-17 stop frame explanation...................................................................................... 160 5-18 data frame format ............................................................................................ 161 5-19 configuration bits reset by rt crst# assertion ..................................................... 164
34 datasheet 5-20 init# going active............................................................................................. 166 5-21 nmi sources...................................................................................................... 167 5-22 general power states for systems using the pch ................................................... 168 5-23 state transition rules for the pch ................. ....................................................... 169 5-24 system power plane ........................................................................................... 170 5-25 causes of smi and sci ....................................................................................... 171 5-26 sleep types....................................................................................................... 175 5-27 causes of wake events ....................................................................................... 176 5-28 gpi wake events ............................................................................................... 177 5-29 transitions due to power failure .......................................................................... 178 5-30 supported deep s4/s5 policy configurations.......................................................... 179 5-31 deep s4/s5 wake events .................................................................................... 179 5-32 transitions due to power button .......................................................................... 180 5-33 transitions due to ri# signal .............................................................................. 181 5-34 write only registers with read paths in alt access mode........................................ 184 5-35 pic reserved bits return values .......................................................................... 186 5-36 register write accesses in alt access mode .......................................................... 186 5-37 slp_lan# pin behavior ...................................................................................... 188 5-38 causes of host and global resets ......................................................................... 190 5-39 event transitions that cause messages ................................................................. 194 5-40 multi-activity led message type........................................................................... 208 5-41 legacy replacement routing ............................................................................... 211 5-42 debug port behavior........................................................................................... 218 5-43 i 2 c block read................................................................................................... 228 5-44 enable for smbalert# ....................................................................................... 230 5-45 enables for smbus slave write and smbus host events ........................................... 231 5-46 enables for the host notify command ................................................................... 231 5-47 slave write registers.......................................................................................... 233 5-48 command types ................................................................................................ 233 5-49 slave read cycle format..................................................................................... 234 5-50 data values for slave read registers............. ....................................................... 235 5-51 host notify format ............................................................................................. 237 5-52 pch thermal throttle states (t-states) ................................................................. 240 5-53 pch thermal throttling configuration registers... ................................................... 240 5-54 i 2 c write commands to the intel ? me .................................................................. 242 5-55 block read command C byte definition ................................................................. 243 5-56 region size versus erase granularity of flas h components ...................................... 256 5-57 region access control table ................................................................................ 258 5-58 hardware sequencing commands and opcode requirements ................................... 261 5-59 flash protection mechanism summary .................................................................. 263 5-60 recommended pinout for 8-pin serial flash device ................................................. 264 5-61 recommended pinout for 16-pin serial flash devi ce ............................................... 264 5-59 pch supported audio formats over hdmi and displayport* ..................................... 272 5-60 pch digital port pin mapping................................................................................ 274 5-61 display co-existence table .................................................................................. 275 6-1 desktop pch ballout by signal name .................................................................... 283 6-2 mobile pch ballout by signal name ...................................................................... 294 8-1 storage conditions and thermal junction oper ating temperature limits.................... 313 8-2 mobile thermal design power .............................................................................. 314 8-3 pch absolute maximum ratings ........................................................................... 314 8-4 pch power supply range .................................................................................... 315 8-5 measured i cc (desktop only)............................................................................... 315 8-6 measured i cc (mobile only) ................................................................................. 316 8-7 dc characteristic input signal association ......... .................................................... 318 8-8 dc input characteristics ..................................................................................... 320 8-9 dc characteristic output signal association ....... .................................................... 323 8-10 dc output characteristics ............................ ....................................................... 325 8-11 other dc characteristics ..................................................................................... 327 8-12 signal groups .................................................................................................... 328 8-13 crt dac signal group dc characteristics: functional operating range (vccadac = 3.3 v 5%)..................................................................................... 328 8-14 lvds interface: functional operating range (vccalvds = 1.8 v 5%) ..................... 329 8-15 display port auxiliary signal group dc characte ristics............................................. 329 8-16 pci express* interface timings ............................................................................ 330 8-17 hdmi interface timings (ddp[d:b][3:0])timings ................................................... 331 8-18 sdvo interface timings ...................................................................................... 331 8-19 displayport interface timings (ddp[d:b][3:0]) ...................................................... 332
datasheet 35 8-20 displayport aux interface ................................................................................... 333 8-21 ddc characteristics ........................................................................................... 333 8-22 lvds interface ac characteristics at various frequencies ....................................... 334 8-23 crt dac ac characteristics ................................................................................ 336 8-24 clock timings.................................................................................................... 336 8-25 pci interface timing .......................................................................................... 340 8-26 universal serial bus timing ................................................................................. 341 8-27 sata interface timings ...................................................................................... 342 8-28 smbus and smlink timing .................................................................................. 343 8-29 intel ? high definition audio timing ...................................................................... 344 8-30 lpc timing ....................................................................................................... 344 8-31 miscellaneous timings ........................................................................................ 344 8-32 spi timings (20 mhz)......................................................................................... 345 8-33 spi timings (33 mhz)......................................................................................... 345 8-34 spi timings (50 mhz)......................................................................................... 346 8-35 sst timings (server/workstation only) .............. .................................................. 346 8-36 controller link receive timings ........................................................................... 347 8-37 power sequencing and reset signal timings.......................................................... 347 9-1 pci devices and functions .................................................................................. 366 9-2 fixed i/o ranges decoded by pch ....................................................................... 368 9-3 variable i/o decode ranges ................................................................................ 370 9-4 memory decode ranges from processor perspectiv e ............................................... 371 9-5 spi mode address swapping ............................................................................... 373 10-1 chipset configuration register memory map (m emory space) .................................. 375 11-1 pci bridge register address map (pci-pcid30:f0) .............................................. 417 12-1 gigabit lan configuration registers address map (gigabit lan d25:f0) ...................................................................................... 435 13-1 lpc interface pci register address map (lpc i/fd31:f0) ..................................... 449 13-2 dma registers................................................................................................... 476 13-3 pic registers .................................................................................................... 486 13-4 apic direct registers ......................................................................................... 494 13-5 apic indirect registers....................................................................................... 494 13-6 rtc i/o registers .............................................................................................. 499 13-7 rtc (standard) ram bank .................................................................................. 500 13-8 processor interface pci register address map ....................................................... 504 13-9 power management pci register address map (pmd31:f0)................................... 507 13-10 apm register map .............................................................................................. 517 13-11 acpi and legacy i/o register map ....................................................................... 518 13-12 tco i/o register address map............................................................................. 536 13-13 registers to control gpio address map................................................................. 543 14-1 sata controller pci register address map (sataCd31:f2)...................................... 553 14-2 bus master ide i/o register address map ............................................................. 580 14-3 ahci register address map ................................................................................. 588 14-4 generic host controller register address map........................................................ 589 14-5 port [5:0] dma register address map ................................................................... 599 15-1 sata controller pci register address map (sataCd31:f5)...................................... 615 15-2 bus master ide i/o register address map ............................................................. 631 16-1 usb ehci pci register address map (usb ehcid29:f0, d26:f0) .......................... 639 16-2 enhanced host controller capability registers .. ...................... ............ ......... .......... 662 16-3 enhanced host controller operational register address map .................................... 665 16-4 debug port register address map ........................................................................ 680 17-1 intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) .................................................................. 685 17-2 intel ? high definition audio memory mapped configuration registers address map (intel ? high definition audio d27:f0) ................................................ 707 17-3 configuration default ......................................................................................... 733 17-4 configuration data structure ........................ ....................................................... 733 17-5 port connectivity ............................................................................................... 735 17-6 location ........................................................................................................... 735 17-7 default device................................................................................................... 736 17-8 connection type................................................................................................ 736 17-9 color................................................................................................................ 737 17-10 misc ................................................................................................................. 737 18-1 smbus controller pci register address map (smbusd31:f3)................................. 739 18-2 smbus i/o and memory mapped i/o register address map...................................... 746 19-1 pci express* configuration registers address map (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) ..................................................... 757
36 datasheet 20-1 memory-mapped register address map ................................................................. 801 21-1 serial peripheral interface (spi) register address map (spi memory mapped configuration registers) ....................................................... 811 21-2 gigabit lan spi flash program register address map (gbe lan memory mapped configuration registers)................................................ 835 22-1 thermal sensor register address map................................................................... 847 22-2 thermal memory mapped configuration register address map.................................. 855 23-1 intel ? mei 1 configuration registers address map (intel ? mei 1d22:f0) ...................................................................................... 869 23-2 intel ? mei 1 mmio register address map .............................................................. 879 23-3 intel ? mei 2 configuration registers address map (intel ? mei 2d22:f1) ...................................................................................... 882 23-4 intel ? mei 2 mmio register address map .............................................................. 892 23-5 ide redirect function ider register address ma p .................................................. 895 23-6 ider bar0 register address map ......................................................................... 903 23-7 ider bar1 register address map ......................................................................... 913 23-8 ider bar4 register address map ......................................................................... 914 23-9 serial port for remote keyboard and text (kt) redirection register address map...................................................................................................... 921 23-10 kt io/memory mapped device register address map .............................................. 928
datasheet 37 revision history revision description date 001 ? initial release january 2011 002 ? added the intel q67, b65, h61, qm67, um 67, and qs67 chipset ?chapter 1 updated table 1-1 updated following sub-sections in section 1.2.1 - intel ? active management technology (intel? amt) - sol function - kvm (new) - ide-r function ?chapter 5 updated table 5-22, 5-23, and 5-29. ?chapter 6 added sff top view ballout figures in section 6.3. ?chapter 8 updated table 8-1 to add tj for mobile. ?chapter 9 updated table 9-3, variable i/o decode ranges ?chapter 10 updated section 10.1.54, deep_s4_poldeep s4/s5 from s4 power policies updated section 10.1.55, deep_s5_poldeep s4/s5 from s5 power policies updated bits 29:28 in sect ion 10.1.78, cgclock gating ?chapter 13 updated section 13.8.1.8, pmirpower management initialization register (pm d31:f0) ?chapter 17 added section 17.1.1.20, hdinit1intel ? high definition audio initialization register 1 (intel ? high definition audio controllerd27:f0) ?chapter 23 added section 23.1.2, mei0_mbarintel ? mei 1 mmio registers ? updated section 23.2.2.2, cgclock gating february 2011 003 ? added intel q65 chipset april 2011 004 ? added intel c200 series chipset april 2011 005 ? added intel z68 series chipset ? minor updates throughout for clarity may 2011 006 ? minor updates for clarity may 20 1 1
38 datasheet platform controller hub features ? direct media interface new: up to 20 gb/s each direction, full duplex transparent to software ? pci express* up to eight pci express root ports new: supports pci express rev 2.0 running at up to 5.0 gt/s ports 1-4 and 5-8 can independently be configured to support eight x1s, two x4s, two x2s and four x1s, or one x4 and four x1 port widths module based hot-plug supported (that is, expresscard*) ? integrated serial ata host controller up to six sata ports new: data transfer rates up to 6.0 gb/s (600 mb/s) on up to two ports data transfer rates up to 3.0 gb/s (300 mb/s) and up to 1.5 gb/s (150 mb/s) on all ports integrated ahci controller ? external sata support on all ports 3.0 gb/s / 1.5 gb/s support port disable capability ? intel ? rapid storage technology configures the pch sata controller as a raid controller supporting raid 0/1/5/10 ? new: intel ? smart response technology ? intel ? high definition audio interface pci express endpoint independent bus master logic for eight general purpose streams: four input and four output support four external codecs supports variable length stream slots supports multichannel, 32-bit sample depth, 192 khz sample rate output provides mic array support allows for non-48 khz sampling output support for acpi device states low voltage ? eight tach signals and four pwm signals (server and workstation only) ? platform environmental control interface (peci) and simple seri al transport (sst) 1.0 bus (server and workstation only) ? usb two ehci host controllers, supporting up to fourteen external usb 2.0 ports two usb 2.0 rate matching hubs per-port-disable capability includes up to two usb 2.0 high-speed debug ports supports wake-up from sleeping states s1- s4 supports legacy keyboard/mouse software ? integrated gigabit lan controller connection utilizes pci express pins integrated asf management controller network security with system defense supports ieee 802.3 10/100/1000 mbps ethernet support jumbo frame support ? intel ? active management technology with system defense network outbreak containment heuristics ? intel ? i/o virtualization (intel ? vt-d) support ? intel ? trusted execution technology support ? intel ? anti-theft technology ? power management logic supports acpi 4.0a acpi-defined power states (processor driven c states) acpi power management timer smi# generation all registers readable/restorable for proper resume from 0 v core well suspend states support for apm-based legacy power management for non-acpi implementations ? integrated clock controller full featured platform clocking without need for a discrete clock chip ten pcie 2.0 specification compliant clocks, four 33 mhz pci clocks, four flex clocks that can be configured for various crystal replacement frequencies, one 120 mhz clock for embedded displayport* two isolated pcie* 2.0 jitter specification compliant clock domains
datasheet 39 note: not all features are available on all pch skus. see section 1.3 for more details. ? external glue integration integrated pull-down and series resistors on usb ? enhanced dma controller two cascaded 8237 dma controllers supports lpc dma ? pci bus interface (not available on all skus) supports pci rev 2.3 specification at 33 mhz four available pci req/gnt pairs support for 64-bit addressing on pci using dac protocol ? smbus interface speeds of up to 100 kbps flexible smbus/smlink architecture to optimize for asf provides independent manageability bus through smlink interface supports smbus 2.0 specification host interface allows processor to communicate using smbus slave interface allows an internal or external microcontroller to access system resources compatible with most two-wire components that are also i 2 c compatible ? high precision event timers advanced operating system interrupt scheduling ? timers based on 82c54 system timer, refresh request, speaker tone output ? real-time clock 256 byte battery-backed cmos ram integrated oscillator components lower power dc/dc converter implementation ? system tco reduction circuits timers to generate smi# and reset upon detection of system hang timers to detect improper processor reset supports ability to disable external devices ? jtag boundary scan for testing during board manufacturing ? serial peripheral interface (spi) supports up to two spi devices supports 20 mhz, 33 mhz, and 50 mhz spi devices support up to two different erase granularities ? firmware hub i/f supports bios memory size up to 8 mb ? low pin count (lpc) i/f supports two master/dma devices. support for security device (trusted platform module) connected to lpc ? interrupt controller supports up to eight pci interrupt pins supports pci 2.3 message signaled interrupts two cascaded 82c59 with 15 interrupts integrated i/o apic capability with 24 interrupts supports processor system bus interrupt delivery ? 1.05 v operation with 1.5/3.3 v i/o 5 v tolerant buffers on pci, usb and selected legacy signals ? 1.05 v core voltage ? integrated voltage regulators for select power rails ? gpio open-drain, inversion gpio lock down ? analog display (vga) ? digital display three digital ports capable of supporting hdmi/dvi, displayport*, and embedded displayport (edp*) one digital port supporting sdvo lvds integrated displayport/hdmi audio hdcp support ? package 27 mm x 27 mm fcbga (desktop only) 25 mm x 25 mm fcbga (mobile only) 22 mm x 22 mm fcbga (mobile sff only)
40 datasheet
datasheet 41 introduction 1 introduction 1.1 about this manual this document is intended for original equipment manufacturers and bios vendors creating intel ? 6 series chipset and intel ? c200 series chipset based products (see section 1.3 for currently defined skus). note: throughout this document, platform controller hub (pch) is used as a general term and refers to all intel 6 series chipset and intel c200 series chipset skus, unless specifically noted otherwise. note: throughout this document, the terms ?desktop? and ?desktop only? refer to information that is applicable only to the intel ? q67 chipset, intel ? q65 chipset, intel ? b65 chipset, intel ? z68 chipset, intel ? h67 chipset, intel ? p67 chipset, intel ? h61 chipset, intel ? c202 chipset, intel ? c204 chipset, and intel ? c206 chipset, unless specifically noted otherwise. note: throughout this document, the terms ?server/workstation? and ?server/workstation only? refers to information that is applicable only to the intel ? c202 chipset, intel ? c204 chipset, and intel ? c206 chipset, unless specifically noted otherwise. note: throughout this document, the terms ?mobile ? and ?mobile only? refers to information that is applicable only to the intel ? qm67 chipset, intel ? um67 chipset, intel ? hm67 chipset, intel ? hm65 chipset, and intel ? qs67 chipset, unless specifically noted otherwise. note: throughout this document, the terms ?small form factor only? and ?sff only? refers to information that is app licable only to the intel ? qs67 chipset, unless specifically noted otherwise. this manual assumes a working knowledge of the vocabulary and principles of pci express*, usb, ahci, sata, intel ? high definition audio (intel ? hd audio), smbus, pci, acpi and lpc. although some details of these features are described within this manual, refer to the individual in dustry specifications listed in ta b l e 1 - 1 for the complete details. all pci buses, devices and functions in this manual are abbreviated using the following nomenclature; bus:device:function. this manual abbreviates buses as b n , devices as d n and functions as f n . for example device 31 function 0 is abbreviated as d31:f0, bus 1 device 8 function 0 is abbreviated as b1:d8:f0. generally, the bus number will not be used, and can be considered to be bus 0. note that the pch?s external pci bus is typically bus 1, but may be assigned a different number depending upon system configuration.
introduction 42 datasheet chapter 1, introduction chapter 1 introduces the pch and provides information on manual organization and gives a general overview of the pch. chapter 2, signal description chapter 2 provides a block diagram of the pch and a detailed description of each signal. signals are arranged according to interface and details are provided as to the drive characteristics (input/output, open drain, etc.) of all signals. chapter 3, pch pin states chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and thei r logic level before and after reset. chapter 4, pch and system clocks chapter 4 provides a list of each clock domain associated with the pch. table 1-1. industry specifications specification location pci express* base specification, revision 2.0 http://www.pcisig.com/specifications low pin count interface specif ication, revision 1.1 (lpc) http://developer.intel.com/design/chipsets/ industry/lpc.htm system management bus specification, version 2.0 (smbus) http://www.smbus.org/specs/ pci local bus specification, revision 2.3 (pci) http://www.pcisig.com/specifications pci power management specification, revision 1.2 http://www.pcisig.com/specifications universal serial bus specification (usb), revision 2.0 http://www.usb.org/developers/docs advanced configuration and power interface, version 4.0a (acpi) http://www.acpi.info/spec.htm enhanced host controller interfa ce specification for universal serial bus, revision 1.0 (ehci) http://developer.intel.com/technology/usb/ ehcispec.htm serial ata specification, revision 3.0 http://www.serialata.org/ serial ata ii: extensions to serial ata 1.0, revision 1.0 http://www.serialata.org serial ata ii cables and connectors volume 2 gold http://www.serialata.org alert standard format sp ecification, version 1.03 http://www.dmtf.org/standards/asf ieee 802.3 fast ethernet http://standards.ieee.org/getieee802/ at attachment - 6 with packet interface (ata/atapi - 6) http://t13.org (t13 1410d) ia-pc hpet (high precision event timers) specification, revision 1.0a http://www.intel.com/hardwaredesign/ hpetspec_1.pdf tpm specification 1.02, level 2 revision 103 http://www.trustedcomputinggroup.org/specs/ tpm intel ? virtualization technology http://www.intel.com/technology/ virtualization/index.htm sff-8485 specification for serial gpio (sgpio) bus, revision 0.7 http://www.intel.com/technology/ virtualization/index.htm advanced host controller inte rface specification for serial ata, revision 1.3 http://www.intel.com/technology/serialata/ ahci.htm intel? high definition audio specification, revision 1.0a http://www.intel.com/standards/hdaudio/
datasheet 43 introduction chapter 5, functional description chapter 5 provides a detailed description of the functions in the pch. chapter 6, ballout definition chapter 6 provides the ball assignment table an d the ball-map for the desktop, mobile and mobile sff packages. chapter 7, package information chapter 7 provides drawings of the physical dimensions and characteristics of the desktop, mobile and mobile sff packages. chapter 8, electrical characteristics chapter 8 provides all ac and dc characterist ics including detailed timing diagrams. chapter 9, register and memory mapping chapter 9 provides an overview of the registers, fixed i/o ranges, variable i/o ranges and memory ranges decoded by the pch. chapter 10, chipset configuration registers chapter 10 provides a detailed description of regi sters and base functionality that is related to chipset configuration. it contai ns the root complex register block, which describes the behavior of the upstream internal link. chapter 11, pci-to-pci br idge registers (d30:f0) chapter 11 provides a detailed description of registers that reside in the pci-to-pci bridge. this bridge resides at device 30, function 0 (d30:f0). chapter 12, gigabit lan configuration registers chapter 12 provides a detailed description of registers that reside in the pch?s integrated lan controller. the integrated lan controller resides at device 25, function 0 (d25:f0). chapter 13, lpc interface bridge regist ers (d31:f0) chapter 13 provides a detailed description of registers that reside in the lpc bridge. this bridge resides at device 31, function 0 (d31:f0). this function contains registers for many different units within the pch in cluding dma, timers, interrupts, processor interface, gpio, power manageme nt, system management and rtc. chapter 14, sata controller registers (d31:f2) chapter 14 provides a detailed description of registers that reside in the sata controller #1. this controller resides at device 31, function 2 (d31:f2). chapter 15, sata controller registers (d31:f5) chapter 15 provides a detailed description of registers that reside in the sata controller #2. this controller resides at device 31, function 5 (d31:f5). chapter 16, ehci controller registers (d29:f0, d26:f0) chapter 16 provides a detailed description of registers that reside in the two ehci host controllers. these controllers reside at device 29, function 0 (d29:f0) and device 26, function 0 (d26:f0). chapter 17, integrated intel? high definition audio controller registers chapter 17 provides a detailed description of registers that reside in the intel high definition audio controller. this controller resides at device 27, function 0 (d27:f0). chapter 18, smbus controller registers (d31:f3) chapter 18 provides a detailed description of registers that reside in the smbus controller. this controller resides at device 31, function 3 (d31:f3).
introduction 44 datasheet chapter 19, pci express* configuration registers chapter 19 provides a detailed description of regi sters that reside in the pci express controller. this controller resides at device 28, functions 0 to 7 (d28:f0-f7). chapter 20, high precisio n event timer registers chapter 20 provides a detailed description of registers that reside in the multimedia timer memory mapped register space. chapter 21, serial peripheral interface (spi) chapter 21 provides a detailed description of regi sters that reside in the spi memory mapped register space. chapter 22, thermal sensor registers (d31:f6) chapter 22 provides a detailed description of re gisters that reside in the thermal sensors pci configuration space. the registers reside at device 31, function 6 (d31:f6). chapter 23, intel? management engine subsystem registers (d22:f[3:0]) chapter 23 provides a detailed description of registers that reside in the intel me controller. the registers reside at device 22, function 0 (d22:f0). 1.2 overview the pch provides extensive i/o support. functions and capabilities include: ? pci express* base specification, revision 2.0 support for up to eight ports with transfers up to 5 gt/s ? pci local bus specification , revision 2.3 support for 33 mhz pci operations (supports up to four req/gnt pairs) ? acpi power management logic support, revision 4.0a ? enhanced dma controller, interrupt controller, and timer functions ? integrated serial ata host controllers with independent dma operation on up to six ports ? usb host interface with two ehci high-spe ed usb 2.0 host controllers and two rate matching hubs provide support for up to fourteen usb 2.0 ports ? integrated 10/100/1000 gigabit ethernet mac with system defense ? system management bus (smbus) specification , version 2.0 with additional support for i 2 c devices ?supports intel ? high definition audio (intel ? hd audio) ?supports intel ? rapid storage technology (intel ? rst) ?supports intel ? active management technology (intel ? amt) ?supports intel ? virtualization technology for directed i/o (intel ? vt-d) ?supports intel ? trusted execution technology (intel ? txt) ? integrated clock controller ?intel ? flexible display interconnect (intel ? fdi) ? analog and digital display ports ?analog vga ?hdmi ?dvi ? displayport* 1.1, embedded displayport ?sdvo ? lvds (mobile only) ? low pin count (lpc) interface ? firmware hub (fwh) interface support
datasheet 45 introduction ? serial peripheral interface (spi) support ?intel ? anti-theft technology (intel ? at) ? jtag boundary scan support the pch incorporates a variety of pci devices and functions separated into logical devices, as shown in ta b l e 9 - 1 . note: not all functions and capabilities may be available on all skus. please see section 1.3 for details on sku feature availability. 1.2.1 capability overview the following sub-sections provide an overview of the pch capabilities. direct media interface (dmi) direct media interface (dmi) is the chip-to-chip connection between the processor and pch. this high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. base functionality is completely software-transparent, permitting current and legacy software to operate normally. intel ? flexible display interconnect (fdi) intel ? fdi connects the display engine in the processor with the display interfaces on the pch. the display data from the frame bu ffer is processed by the display engine and sent to the pch where it is transcoded and dr iven out on the panel. intel fdi involves two channels ? a and b for display data transfer. intel fdi channel a has 4 lanes and channe l b supports 4 lanes depending on the display configuration. each of the intel fd i channel lanes uses differential signal supporting 2.7 gb/s. for two display configurat ions intel fdi ch a maps to display pipe a while intel ch b maps to the second display pipe b. pch display interface the pch integrates latest display technologi es such as hdmi*, displayport*, embedded displayport (edp*), sdvo, and dvi along with legacy display technologies?analog port (vga) and lvds (mobile only). the anal og port and lvds port are dedicated ports on the pch and the digital ports b, c, and d can be configured to drive hdmi, dvi, or displayport. digital port b can also be conf igured as sdvo while digital port d can be configured as edp. the hdmi interface supp orts the hdmi* 1.4a specification while the displayport interface supports the displaypor t* 1.1a specificatio n. the pch supports high-bandwidth digital content protection for high definition content playback over digital interfaces. the pch also integrates audio codecs for audio support over hdmi and displayport interfaces. the pch receives the display data over intel fdi and transcodes the data as per the display technology protocol and sends th e data through the display interface. pci express* interface the pch provides up to 8 pci expr ess root ports, supporting the pci express base specification, revision 2.0. each root port x1 lane supports up to 5 gb/s bandwidth in each direction (10 gb/s concurrent). pci express root ports 1-4 or ports 5-8 can independently be configured to support four x1s, two x2s, one x2 and two x1s, or one x4 port widths. please see section 1.3 for details on sku feature availability.
introduction 46 datasheet serial ata (sata) controller the pch has two integrated sata host controllers that support independent dma operation on up to six ports and supports data transfer rates of up to 6.0 gb/s (600 mb/s) on up to two ports while all ports support rates up to 3.0 gb/s (300 mb/s) and up to 1.5 gb/s (150 mb/s). the sata controller contains two modes of operation? a legacy mode using i/o space, and an ahci mode using memory space. software that uses legacy mode will not have ahci capabilities. the pch supports the serial ata specification, revision 3.0. the pch also supports several optional sections of the serial ata ii: extensions to serial ata 1.0 specification, revision 1.0 (ahci support is required for some elements). please see section 1.3 for details on sku feature availability. ahci the pch provides hardware support for adva nced host controller interface (ahci), a standardized programming interface for sata host controllers. platforms supporting ahci may take advantage of performance features such as no master/slave designation for sata devices?each device is treated as a master?and hardware- assisted native command queuing. ahci also provides usability enhancements such as hot-plug. ahci requires appropriate software support (such as, an ahci driver) and for some features, hardware support in the sata device or additional platform hardware. please see section 1.3 for details on sku feature availability. intel ? rapid storage technology the pch provides support for intel rapid st orage technology, providing both ahci (see above for details on ahci) and integrated raid functionality. the raid capability provides high-performance raid 0, 1, 5, an d 10 functionality on up to 6 sata ports of the pch. matrix raid support is provided to allow multiple raid levels to be combined on a single set of hard drives, such as ra id 0 and raid 1 on two disks. other raid features include hot spare support, smart al erting, and raid 0 auto replace. software components include an option rom for pre-boot configuration and boot functionality, a microsoft windows* compatible driver, an d a user interface for configuration and management of the raid capability of pch. see section 1.3 for details on sku feature availability. intel ? smart response technology intel? smart response technology is a disk caching solution that can provide improved computer system performance with improved power savings. it allows configuration of a computer systems with the advantage of having hdds for maximum storage capacity with system performance at or near ssd performance levels. see section 1.3 for details on sku feature availability. pci interface the pch pci interface provides a 33 mhz, revision 2.3 implementation. the pch integrates a pci arbiter that supports up to four external pci bus masters in addition to the internal pch requests. this allows for combinations of up to four pci down devices and pci slots. see section 1.3 for details on sku feature availability. low pin count (lpc) interface the pch implements an lpc interface as described in the lpc 1.1 specification . the low pin count (lpc) bridge function of the pch resides in pci device 31:function 0. in addition to the lpc bridge interface functi on, d31:f0 contains other functional units including dma, interrupt controllers, time rs, power management, system management, gpio, and rtc.
datasheet 47 introduction serial peripheral interface (spi) the pch implements an spi interface as an alternative interface for the bios flash device. an spi flash device can be used as a replacement for the fwh, and is required to support gigabit ethernet and intel active management technology. the pch supports up to two spi flash devices with sp eeds up to 50 mhz, using two chip select pins. compatibility modules (dma contro ller, timer/coun ters, interrupt controller) the dma controller incorporates the logic of two 82c37 dma controllers, with seven independently programmable channels. channels 0?3 are hardwired to 8-bit, count-by- byte transfers, and channels 5?7 are hardwired to 16-bit, count-by-word transfers. any two of the seven dma channels can be prog rammed to support fast type-f transfers. channel 4 is reserved as a generic bus master request. the pch supports lpc dma, wh ich is similar to isa dm a, through the pch?s dma controller. lpc dma is handled through the use of the ldrq# lines from peripherals and special encoding on lad[3:0] from the host. single, demand, verify, and increment modes are supported on the lpc interface. the timer/counter block contains three counters that are equivalent in function to those found in one 82c54 programmable interval timer. these three counters are combined to provide the system timer function, and speaker tone. the 14.31818-mhz oscillator input provides the clock source for these three counters. the pch provides an isa-compatible prog rammable interrupt controller (pic) that incorporates the functionality of two, 82c59 interrupt controllers. the two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. in addition, the pch supports a serial interrupt scheme. all of the registers in these modules can be read and restored. this is required to save and restore system state after power has been removed and restored to the platform. advanced programmable interrupt controller (apic) in addition to the standard isa compatib le programmable interrupt controller (pic) described in the previous section, the pc h incorporates the advanced programmable interrupt controller (apic). universal serial bus (usb) controllers the pch contains up to two enhanced host controller interface (ehci) host controllers that support usb high-speed signaling. high-s peed usb 2.0 allows data transfers up to 480 mb/s which is up to 40 times faster than full-speed usb. the pch supports up to fourteen usb 2.0 ports. all ports are high -speed, full-speed, and low-speed capable. please see section 1.3 for details on sku feature availability.
introduction 48 datasheet gigabit ethernet controller the gigabit ethernet controller provides a system interface using a pci function. the controller provides a full memory-mapped or io mapped interface along with a 64 bit address master support for systems using mo re than 4 gb of physical memory and dma (direct memory addressing) mechanisms for high performance data transfers. its bus master capabilities enable the compon ent to process high-level commands and perform multiple operations; this lowe rs processor utilization by off-loading communication tasks from the processor. two large configurable transmit and receive fifos (up to 20 kb each) help prevent data underruns and overruns while waiting for bus accesses. this enables the integrated lan controller to transmit data with minimum interframe spacing (ifs). the lan controller can operate at multiple speeds (10/100/1000 mb/s) and in either full duplex or half duplex mode. in full dupl ex mode the lan controller adheres with the ieee 802.3x flow control specification. half duplex performance is enhanced by a proprietary collision reduction mechanism. see section 5.3 for details. rtc the pch contains a motorola mc146818b-compatible real-time clock with 256 bytes of battery-backed ram. the real-time clock performs two key functions?keeping track of the time of day and storing system data, even when the system is powered down. the rtc operates on a 32.768 khz crystal and a 3 v battery. the rtc also supports two lockable memory ranges. by setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. this prevents unauthorized reading of passwords or other system security information. the rtc also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance. gpio various general purpose inputs and outputs are provided for custom system design. the number of inputs and outputs varies depending on pch configuration. enhanced power management the pch?s power management functions include enhanced clock control and various low-power (suspend) states (such as suspend-to-ram and suspend-to-disk). a hardware-based thermal management circui t permits software-independent entrance to low-power states. the pch contains full support for the advanced configuration and power interface (acpi) specification, revision 4.0a. intel ? active management technology (intel ? amt) intel amt is a fundamental component of intel ? vpro? technology. intel amt is a set of advanced manageability features developed as a direct result of it customer feedback gained through intel market research. with the advent of powerful tools like the intel ? system defense utility, the extensive feature set of intel amt easily integrates into any network environment. please see section 1.3 for details on sku feature availability.
datasheet 49 introduction manageability in addition to intel amt the pch integrates several functions designed to manage the system and lower the total cost of ownership (tco) of the system. these system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller. ? tco timer. the pch?s integrated programmable tco timer is used to detect system locks. the first expiration of the timer generates an smi# that the system can use to recover from a software lock. the second expiration of the timer causes a system reset to recover from a hardware lock. ? processor present indicator. the pch looks for the processor to fetch the first instruction after reset. if the processor do es not fetch the first instruction, the pch will reboot the system. ? ecc error reporting. when detecting an ecc error, the host controller has the ability to send one of several messages to the pch. the host controller can instruct the pch to generate either an sm i#, nmi, serr#, or tco interrupt. ? function disable. the pch provides the ability to disable the following integrated functions: lan, usb, lpc, intel hd au dio, sata, pci express or smbus. once disabled, these functions no longer decode i/o, memory, or pci configuration space. also, no interrupts or power management events are generated from the disabled functions. ? intruder detect. the pch provides an input sign al (intruder#) that can be attached to a switch that is activated by the system case being opened. the pch can be programmed to generate an smi# or tco interrupt due to an active intruder# signal. system management bus (smbus 2.0) the pch contains an smbus host interface that allows the processor to communicate with smbus slaves. this interface is compatible with most i 2 c devices. special i 2 c commands are implemented. the pch?s smbus host controller provides a mechanism for the processor to initiate communications with smbus peripherals (slaves). also, the pch supports slave functionality, including the host notify pr otocol. hence, the host controller supports eight command protocols of the smbus interface (see system management bus (smbus) specification, version 2.0): quick command, send byte, receive byte, write byte/word, read byte/word, process ca ll, block read/write, and host notify. the pch?s smbus also implements hardware-based packet error checking for data robustness and the address resolution protocol (arp) to dynamically provide address to all smbus devices. intel ? high definition audio controller the intel ? high definition audio specification defines a digital interface that can be used to attach different types of codecs, such as audio and modem codecs. the pch intel ? hd audio controller supports up to 4 codecs. the link can operate at either 3.3 v or 1.5 v. with the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 khz, the intel hd audio controller provides audio quality that can deliver ce levels of audio experience. on the input si de, the pch adds support for an array of microphones.
introduction 50 datasheet intel ? virtualization technology fo r directed i/o (intel vt-d) the pch provides hardware support for implementation of intel virtualization technology with directed i/o (intel ? vt-d). intel vt-d technology consists of technology components that support the vi rtualization of platforms based on intel ? architecture processors. intel vt-d technolo gy enables multiple operating systems and applications to run in independent partitions. a partition behaves like a virtual machine (vm) and provides isolation and protection across partitions. each partition is allocated it?s own subset of host physical memory. jtag boundary-scan the pch implements the industry standard jtag interface and enables boundary-scan in place of the xor chains used in previous generations of chipsets. boundary-scan can be used to ensure device connectivity du ring the board manufacturing process. the jtag interface allows system manufacturers to improve efficiency by using industry available tools to test the pch on an assemble d board. since jtag is a serial interface, it eliminates the need to create probe points for every pin in an xor chain. this eases pin breakout and trace routing and simplifie s the interface between the system and a bed-of-nails tester. note: contact your local intel field sales representative for additional information about jtag usage on the pch. integrated clock controller the pch contains a fully integrated clock controller (icc) generating various platform clocks from a 25 mhz crystal source. the icc contains up to eight plls and four spread modulators for generating various clocks suited to the platform needs. the icc supplies up to ten 100 mhz pci express 2.0 specification compliant clocks, one 100 mhz bclk/ dmi to the processor, one 120 mhz for embedded displayport on the processor, four 33 mhz clocks for sio/ec/lpc/tpm devices and four flex clocks that can be configured to various frequencies that include 14.318 mhz, 27 mhz, 33 mhz and 24/48 mhz for use with sio, ec, lpc, and discrete graphics devices. sol function this function supports redirection of keyboa rd and text screens to a terminal window on a remote console. the keyboard and text redirection enables the control of the client machine through the network without the need to be physically near that machine. text and keyboard redirection allows the remote machine to control and configure a client system. the sol function emulates a standard pci device and redirects the data from the serial port to the management console using the integrated lan. kvm kvm provides enhanced capabilities to its predecessor ? sol. in addition to the features set provided by sol, kvm provid es mouse and graphic redirection across the integrated lan. unlike sol, kvm does not appe ar as a host accessible pci device but is instead almost completely performed by intel amt firmware with minimal bios interaction. the kvm feature is only available with internal graphics.
datasheet 51 introduction ide-r function the ide-r function is an ide redirection inte rface that provides client connection to management console ata/atapi devices such as hard disk drives and optical disk drives. a remote machine can setup a diagnostic sw or os installation image and direct the client to boot an ide-r session. the ide-r interface is the same as the ide interface although the device is not physically connected to the system and supports the ata/atapi-6 specification. ide-r does not conflict with any other type of boot and can instead be implemented as a boot device option. the intel amt solution will use ide-r when remote boot is required. the device attached through ide-r is only visible to software during a management boot session. during normal boot session, the ide-r controller does not appear as a pci present device. 1.3 intel ? 6 series chipset and intel ? c200 series chipset sku definition notes: 1. contact your local intel field sales repres entative for currently available pch skus. 2. table above shows feature differences between the pch skus. if a feature is not listed in the table it is considered a base feature that is included in all skus 3. the pch provides hardware support for ahci functionality when enabled by appropriate system configurations and software drivers. 4. sata 6 gb/s support on port 0 and port 1. sata ports 0 and 1 also support 3 gb/s and 1.5 gb/s. 5. sata 6 gb/s support on port 0 only. sata port 0 also supports 3 gb/s and 1.5 gb/s. 6. usb ports 6 and 7 are disabled. 7. usb ports 6, 7, 12 and 13 are disabled. 8. sata ports 2 and 3 are disabled. 9. pcie ports 7 and 8 are disabled. 10. pci legacy mode may option ally be used allowing extern al pci bus support through a pcie-to-pci bridge. see section 5.1.9 for more details. 11. intel rst ssd caching naming is not fina l at this time and is subject to change. table 1-2. desktop intel ? 6 series chipset skus feature set sku name q67 q65 b65 z68 h67 p67 h61 pci express* 2.0 ports 8888886 9 pci interface yes yes yes no 10 no 10 no 10 no 10 usb 2.0 ports 14 14 12 6 14 14 14 10 7 total number of sata ports 6 6 6 6 6 6 4 ? sata ports (6 gb/s, 3 gb/s, and 1.5 gb/s) 2 4 1 5 1 5 2 4 2 4 2 4 0 ? sata ports (3 gb/s and 1.5 gb/s only) 4 5 5 4 4 4 4 8 hdmi/dvi/vga/displayport*/edp* yes yes yes yes yes no yes integrated graphics support with pavp yes yes yes yes yes no yes intel ? rapid storage te c h n o l o g y ahci yesyesyesyesyesyesno 3 raid 0/1/5/10 support yes no no yes yes yes no intel rst ssd caching 11 no no no yes no no no intel ? at yes yes no no no no no intel ? amt 7.0 yesnononononono
introduction 52 datasheet notes: 1. contact your local intel field sales repr esentative for currently available pch skus 2. table above shows feature difference between th e pch skus. if a feature is not listed in the table it is considered a base fe ature that is included in all skus 3. the pch provides hardware support for ahci functionality when enabled by appropriate system configurations and software drivers. 4. sata 6 gb/s support on port 0 and port 1. sata ports 0 and 1 also support 3 gb/s and 1.5 gb/s. 5. usb ports 6 and 7 are disabled on 12 port skus. table 1-3. mobile intel ? 6 series chipset skus feature set sku name qm67 um67 hm67 hm65 qs67 pci express* 2.0 ports 8 8888 pci interface no no no no no usb* 2.0 ports 14 14 14 12 5 14 total number of sata ports 6 6 6 6 6 ? sata ports (6 gb/s, 3 gb/s, and 1.5 gb/s) 2 4 2 4 2 4 2 4 2 4 ? sata ports (3 gb/s and 1.5 gb/s only) 4 4 4 4 4 hdmi/dvi/vga/sdvo/displayport*/edp*/lvds yes yes yes yes yes integrated graphics support with pavp 2.0 yes yes yes yes yes intel ? rapid storage technology ahci yes yes yes yes yes raid 0/1/5/10 support yes no yes no yes intel ? anti-theft yes yes yes yes yes intel ? amt 7.0 yes no no no yes
datasheet 53 introduction notes: 1. contact your local intel field sales repres entative for currently available pch skus. 2. table above shows feature differences between the pch skus. if a feature is not listed in the table it is considered a base feature that is included in all skus 3. the pch provides hardware support for ahci functionality when enabled by appropriate system configurations and software drivers. 4. sata 6 gb/s support on port 0 and port 1. sata ports 0 and 1 also support 3 gb/s and 1.5 gb/s. 5. usb ports 6 and 7 are disabled. table 1-4. server/workstation intel ? c200 series chipset skus feature set sku name c206 c204 c202 pci express* 2.0 ports 88 8 pci interface yes yes yes usb 2.0 ports 14 12 5 12 5 total number of sata ports 6 6 6 ? sata ports (6.0 gb/s & 3.0 gb/s & 1.5 gb/s) 2 4 2 4 0 ? sata ports (3.0 gb/s & 1.5 gb/s only) 4 4 6 hdmi*/dvi*/vga/edp*/displayport* yes no no integrated graphics support with pavp yes no no intel ? rapid storage te c h n ol o g y ahci yes yes yes raid 0/1/5/10 support yes yes yes intel ? anti-theft technology yes no no intel ? active management technology 7.0 yes no no
introduction 54 datasheet
datasheet 55 signal description 2 signal description this chapter provides a detailed description of each signal. the signals are arranged in functional groups according to their associated interface. the ?#? symbol at the end of the signal na me indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is not present, the signal is asserted when at the high voltage level. the following notations are used to describe the signal type: i input pin o output pin od o open drain output pin. i/od bi-directional input/open drain output pin. i/o bi-directional input/output pin. cmos cmos buffers. 1.5 v tolerant. cod cmos open drain buffers. 3.3 v tolerant. hvcmos high voltage cmos buffers. 3.3 v tolerant. a analog reference or output. the ?type? for each signal is indicative of the functional operating mode of the signal. unless otherwise noted in section 3.2 or section 3.3 , a signal is considered to be in the functional operating mode after rtcrst# de asserts for signals in the rtc well, after rsmrst# deasserts for signals in the suspen d well, after pwrok asserts for signals in the core well, after dpwrok asserts for sign als in the deep s4/s5 well, after apwrok asserts for signals in the active sleep well.
signal description 56 datasheet figure 2-1. pch interfac e signals block diagram ( not all signals are on all skus ) ad[31:0] c/be[3:0]# devsel# frame# irdy# trdy# stop# par perr# req0# req1#/gpio50 req2#/gpio52 req3#/gpio54 gnt0# gnt1#/gpio51 gnt2#/gpio53 gnt3#/gpio55 serr# pme# clkin_pciloopback pcirst# plock# pci interface intel ? flexible display interface power mgnt. interrupt interface pmsynch rcin# a20gate thrmptrip# procpwrgd processor interface usb serirq pirq[d:a]# pirq[h:e]#/gpio[5:2] usb[13:0][p,n] oc0#/gpio59; oc1#/gpio40 oc2#/gpio41; oc3#/gpio42 oc4#/gpio43; oc5#/gpio9 oc6#/gpio10; oc7#/gpio14 usbrbias, usbrbias# rtcx1 rtcx2 clkin_dmi_[p,n];clkin_dmi2_[p,n] clkin_sata_[p,n]/cksscd_[p,n] clkin_dot96[p,n] xtal25_in;ref14clkin pcieclkrq0#/gpio73;pcieclkrq1#/gpio18 pcieclkrq2#/gpio20/smi#;pcieclkrq3#/gpio25 pcieclkrq4#/gpio26;pcieclkrq5#/gpio44 pcieclkrq6#/gpio45;pcieclkrq7#/gpio46 peg_a_clkrq#/gpio47;peg_b_clkrq#/gpio56 xclk_rcomp rtc clock inputs misc. signals intvrmen, dswvrmen spkr srtcrst#; rtcrst# init3_3v# tpn gpio35/nmi# gpio24/proc_missing general purpose i/o gpio[72,57,32,28,27,15,8] pwm[3:0] tach7/gpio71;tach6/gpio70; tach5/gpio69;tach4/gpio68 tach3/gpio7; tach2/gpio6; tach1/gpio1;tach0/gpio17 sst peci direct media interface lpc / fwh interface smbus interface intel ? high definition audio system mgnt. lad[3:0]/fwh[3:0] lframe#/fwh4 ldrq0#; ldrq1#/gpio23 serial ata interface pci express* interface spi spi_cs0#; spi_cs1# spi_miso spi_mosi spi_clk jtag controller link fan speed control digital display interface clock outputs clkout_dp_[p,n] clkout_dmi_[p,n] xtal25_out clkout_peg_a_[p,n];clkout_peg_b_[p,n] clkout_pcie[7:0]_[p,n] clkout_itpxdp_[p,n] clkout_pci[4:0] clkoutflex0/gpio64;clkoutflex1/gpio65 clkoutflex2/gpio66;clkoutflex3/gpio67 analog display lvds fdi_rx[p,n][7:4] fdi_rx[p,n[[3:0] fdi_fsync[0:1];fdi_lsync[0:1];fdi_init cl_clk1 ; cl_data1 cl_rst1# pet[p,n][8:1] per[p,n][8:1] sata[5:0]tx[p,n] sata[5:0]rx[p,n] sataicompo, sata3compo sataicompi, sata3compi sata3rbias sataled# sata0gp/gpio21 sata1gp/gpio19 sata2gp/gpio36 sata3gp/gpio37 sata4gp/gpio16 sata5gp/gpio49/temp_alert# sclock/gpio22, sload/gpio38 sdataout0/gpio39, sdataout1/gpio48 suswarn#/sus_pwr_dn_ack/gpio30 dpwrok sys_reset# rsmrst# slp_s3# slp_s4# slp_s5#/gpio63 slp_a# clkrun#/gpio32 pwrok awrok pwrbtn# ri# wake# sus_stat#/gpio61 susclk/gpio62 batlow#/gpio72 pltrst# bmbusy#/gpio0 stp_pci#/gpio34 acpresent/gpio31 drampwrok lan_phy_pwr_ctrl/gpio12 slp_lan#/gpio29 susack# hda_rst# hda_sync hda_bclk hda_sdo hda_sdin[3:0] hda_dock_en#;hda_dock_rst# dmi[3:0]tx[p,n] dmi[3:0]rx[p,n] dmi_zcomp dmi_ircomp smbdata; smbclk smbalert#/gpio11 intruder#; sml[1:0]data;sml[1:0]clk sml0alert#/gpio60 sml1alert#/pchhot#/gpio74 crt_red;crt_green;crt_blue dac_iref crt_hsync;crt_vsync crt_ddc_clk;crt_ddc_data crt_irtn lvds[a:b]_data[3:0] lvds[a:b]_data#[3:0] lvds[a:b]_clk;lvds[a:b]_clk# lvd_vrefh;lvd_vrefl; lvd_vbg lvd_ibg l_ddc_clk;l_ddc_data l_vdden;l_blkten;l_bkltctl ddpb_[3:0][p,n] ddpc_[3:0][p,n] ddpd_[3:0][p,n] ddp[b:d]_aux[p,n] ddp[b:d]_hpd sdvo_ctrlclk;sdvo_ctrldata ddpc_ctrlclk;ddpc_ctrldata ddpd_ctrlclk;ddpd_ctrldata sdvo_int[p,n] sdvo_tvclkin[p,n] sdvo_stall[p,n] jtagtck jtagtms jtagtdi jtagtdo
datasheet 57 signal description 2.1 direct media interface (dmi) to host controller 2.2 pci express* table 2-1. direct me dia interface signals name type description dmi0txp, dmi0txn o direct media interface diff erential transmit pair 0 dmi0rxp, dmi0rxn i direct media interface diff erential receive pair 0 dmi1txp, dmi1txn o direct media interface diff erential transmit pair 1 dmi1rxp, dmi1rxn i direct media interface diff erential receive pair 1 dmi2txp, dmi2txn o direct media interface diff erential transmit pair 2 dmi2rxp, dmi2rxn i direct media interface diff erential receive pair 2 dmi3txp, dmi3txn o direct media interface diff erential transmit pair 3 dmi3rxp, dmi3rxn i direct media interface diff erential receive pair 3 dmi_zcomp i impedance compensation input: determines dmi input impedance. dmi_ircomp o impedance/current compensation output: determines dmi output impedance and bias current. dmi2rbias i/o dmi2rbias: analog connection point for 750 ? 1% external precision resistor. table 2-2. pci express* signals (sheet 1 of 2) name type description petp1, petn1 o pci express* differential transmit pair 1 perp1, pern1 i pci express differential receive pair 1 petp2, petn2 o pci express differential transmit pair 2 perp2, pern2 i pci express differential receive pair 2 petp3, petn3 o pci express differential transmit pair 3 perp3, pern3 i pci express differential receive pair 3 petp4, petn4 o pci express differential transmit pair 4 perp4, pern4 i pci express differential receive pair 4 petp5, petn5 o pci express differential transmit pair 5 perp5, pern5 i pci express differential receive pair 5 petp6, petn6 o pci express differential transmit pair 6 perp6, pern6 i pci express differential receive pair 6 petp7, petn7 o pci express differential transmit pair 7
signal description 58 datasheet 2.3 pci interface note: pci interface is only available on pci in terface-enabled skus. however, certain pci interface signal functionality is available even on pci interface-disabled skus, as described below (see section 1.3 for full details on sku definition). perp7, pern7 i pci express differential receive pair 7 petp8, petn8 o pci express differential transmit pair 8 perp8, pern8 i pci express differential receive pair 8 table 2-3. pci interface signals (sheet 1 of 2) name type description functionality available on pci interface- disabled skus ad[31:0] i/o pci address/data : reserved. no c/ be[3:0]# i/o bus command and byte enables : reserved. no devsel# i/o device select : reserved. no frame# i/o cycle frame: reserved. no irdy# i/o initiator ready : reserved. no trdy# i/o target ready : reserved. no stop# i/o stop : reserved. no par i/o calculated/checked parity: reserved. no perr# i/o parity error : reserved. no req0# req1#/ gpio50 req2#/ gpio52 req3#/ gpio54 i pci requests : req functionality is reserved. req[3:1]# pins can instead be used as gpio. notes: 1. external pull-up resistor is required. when used as native functionality, the pu ll-up resistor may be to either 3.3 v or 5.0 v per pci specification. when used as gpio or not used at all, the pull-up resistor should be to the vcc3_3 rail. no (gpio only) gnt0# gnt1#/ gpio51 gnt2# / gpio53 gnt3# / gpio55 o pci grants : gnt functionality is reserved. gnt[3:1]# pins can instead be used as gpio. pull-up resistors are not requ ired on these signals. if pull-ups are used, they should be tied to the vcc3_3 power rail. notes: 1. gnt[3:1]#/gpio[55,53,51] are sampled as a functional strap. see section 2.27 for details. no (gpio and strap only) table 2-2. pci express* signals (sheet 2 of 2) name type description
datasheet 59 signal description clkin_pci loopback i pci clock : this is a 33 mhz clock feedback input to reduce skew between pch pc i clock and clock observed by connected pci devices. this signal must be connected to one of the pins in the group clkout_pci[4:0] yes pcirst# o pci reset: reserved. no plock# i/o pci lock : reserved. no serr# i/od system error : reserved. no pme# i/od pci power management event : pci peripherals drive pme# to wake the system from low-power states s1? s5. pme# assertion can also be enabled to generate an sci from the s0 state. in some cases the pch may drive pme# active due to an internal wake event. the pch will not drive pme# high, bu t it will be pulled up to vccsus3_3 by an intern al pull-up resistor. can be used with pci legacy mode on platforms using a pcie-to-pci bridge. downst ream pci devices would need to have pme# routed from the connector to the pch pme# pin. yes table 2-3. pci interface signals (sheet 2 of 2) name type description functionality available on pci interface- disabled skus
signal description 60 datasheet 2.4 serial ata interface table 2-4. serial ata interf ace signals (sheet 1 of 3) name type description sata0txp sata0txn o serial ata 0 differenti al transmit pairs: these are outbound high-speed differential signals to port 0. in compatible mode, sata port 0 is the primary master of sata controller 1. supports up to 6 gb/s, 3 gb/s, and 1.5 gb/s. sata0rxp sata0rxn i serial ata 0 differential receive pair: these are inbound high- speed differential si gnals from port 0. in compatible mode, sata port 0 is the primary master of sata controller 1. supports up to 6 gb/s, 3 gb/s, and 1.5 gb/s. sata1txp sata1txn o serial ata 1 differential transmit pair: these are outbound high-speed differentia l signals to port 1. in compatible mode, sata port 1 is the secondary master of sata controller 1. supports up to 6 gb/s, 3 gb/s, and 1.5 gb/s. sata1rxp sata1rxn i serial ata 1 differential receive pair: these are inbound high- speed differential si gnals from port 1. in compatible mode, sata port 1 is the secondary master of sata controller 1. supports up to 6 gb/s, 3 gb/s, and 1.5 gb/s. sata2txp sata2txn o serial ata 2 differential transmit pair: these are outbound high-speed differentia l signals to port 2. in compatible mode, sata port 2 is the primary slave of sata controller 1. supports up to 3 gb/s and 1.5 gb/s. note: sata port 2 may not be available in all pch skus. sata2rxp sata2rxn i serial ata 2 differential receive pair: these are inbound high- speed differential si gnals from port 2. in compatible mode, sata port 2 is the primary slave of sata controller 1 supports up to 3 gb/s and 1.5 gb/s. note: sata port 2 may not be available in all pch skus. sata3txp sata3txn o serial ata 3 differential transmit pair: these are outbound high-speed differentia l signals to port 3 in compatible mode, sata port 3 is the secondary slave of sata controller 1 supports up to 3 gb/s and 1.5 gb/s. note: sata port 3 may not be available in all pch skus.
datasheet 61 signal description sata3rxp sata3rxn i serial ata 3 differential receive pair: these are inbound high- speed differential si gnals from port 3. in compatible mode, sata port 3 is the secondary slave of sata controller 1 supports up to 3 gb/s and 1.5 gb/s. note: sata port 3 may not be available in all pch skus. sata4txp sata4txn o serial ata 4 differential transmit pair: these are outbound high-speed differentia l signals to port 4. in compatible mode, sata port 4 is the primary master of sata controller 2. supports up to 3 gb/s and 1.5 gb/s. sata4rxp sata4rxn i serial ata 4 differential receive pair: these are inbound high- speed differential si gnals from port 4. in compatible mode, sata port 4 is the primary master of sata controller 2. supports up to 3 gb/s and 1.5 gb/s. sata5txp sata5txn o serial ata 5 differential transmit pair: these are outbound high-speed differentia l signals to port 5. in compatible mode, sata port 5 is the secondary master of sata controller 2. supports up to 3 gb/s and 1.5 gb/s. sata5rxp sata5rxn i serial ata 5 differential receive pair: these are inbound high- speed differential si gnals from port 5. in compatible mode, sata port 5 is the secondary master of sata controller 2. supports up to 3 gb/s and 1.5 gb/s. sataicompo o serial ata compensation output: connected to an external precision resistor to vcccore . must be connected to sataicompi on the board. sataicompi i serial ata compensation input: connected to sataicompo on the board. sata0gp / gpio21 i serial ata 0 general purpose: this is an input pin which can be configured as an interlock switch corresponding to sata port 0. when used as an interlock switch status indication, this signal should be drive to ?0? to indicate that the switch is closed and to ?1? to indicate that the switch is open. if interlock switches are not requir ed, this pin can be configured as gpio21. sata1gp / gpio19 i serial ata 1 general purpose: same function as sata0gp, except for sata port 1. if interlock switches are not requir ed, this pin can be configured as gpio19. sata2gp / gpio36 i serial ata 2 general purpose: same function as sata0gp, ex cept for s ata port 2. if interlock switches are not requir ed, this pin can be configured as gpio36. table 2-4. serial ata interf ace signals (sheet 2 of 3) name type description
signal description 62 datasheet sata3gp / gpio37 i serial ata 3 general purpose: same function as sata0gp, except for sata port 3. if interlock switches ar e not required, this pin can be configured as gpio37. sata4gp / gpio16 / i serial ata 4 general purpose: same function as sata0gp, except for sata port 4. if interlock switches ar e not required, this pin can be configured as gpio16 or mpgio9. sata5gp / gpio49 / temp_alert# i serial ata 5 general purpose: same function as sata0gp, except for sata port 5. if interlock switches ar e not required, this pin can be configured as gpio49 or temp_alert#. sataled# od o serial ata led: this signal is an open -drain output pin driven during sata command activity. it is to be connected to external circuitry that can provide the current to drive a platform led. when active, the led is on. when tri-stated, the led is off. an external pull-up resistor to vcc3_3 is required. sclock / gpio22 od o sgpio reference clock: the sata controller uses rising edges of this clock to transmit serial data , and the target uses the falling edge of this clock to latch data. the sclock frequency supported is 32 khz. if sgpio interface is not used, this signal can be used as gpio22. sload /gpio38 od o sgpio load: the controller drives a ?1? at the rising edge of sclock to indicate either the star t or end of a bit stream. a 4-bit vendor specific pattern will be transmitted right after the signal assertion. if sgpio interface is not used, this signal can be used as gpio38. sdataout0 / gpio39 sdataout1 / gpio48 od o sgpio dataout: driven by the controller to indicate the drive status in the following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2... if sgpio interface is not used, th e signals can be used as gpio. sata3rbias i/o sata3 rbias: analog connection point for a 750 ? 1% external precision resistor. sata3compi i impedance compensation input: connected to a 50 ? (1%) precision external pull-up resistor to vccio. sata3rcompo o impedance/current compensation output: connected to a 50 ? (1%) precision external pull-up resistor to vccio table 2-4. serial ata interf ace signals (sheet 3 of 3) name type description
datasheet 63 signal description 2.5 lpc interface 2.6 interrupt interface note: pirq interrupts can only be shared if it is co nfigured as level sensitive. they cannot be shared if configured as edge triggered. table 2-5. lpc interface signals name type description lad[3:0] i/o lpc multiplexed command, address, data: for lad[3:0], internal pull- ups are provided. lframe# o lpc frame: lframe# indicates the start of an lpc cycle, or an abort. ldrq0#, ldrq1# / gpio23 i lpc serial dma/mast er request inputs: ldrq[1:0]# are used to request dma or bus master access. these signals are typically connected to an external super i/o device. an inte rnal pull-up resistor is provided on these signals. ldrq1# may optionally be used as gpio23. table 2-6. interrupt signals name type description serirq i/od serial interrupt request: this pin implements the serial interrupt protocol. pirq[d:a]# i/od pci interrupt requests: in non-apic mode the pirqx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in section 5.8.6 . each pirqx# line has a separate route control register. in apic mode, these signals are connected to the internal i/o apic in the following fashion: pirqa# is connected to irq16, pirqb# to irq17, pirqc# to irq18, and pi rqd# to irq19. this frees the legacy interrupts. these signals are 5 v tolerant. pirq[h:e]# / gpio[5:2] i/od pci interrupt requests: in non-apic mode the pirqx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in section 5.8.6 . each pirqx# line has a separate route control register. in apic mode, these signals are connected to the internal i/o apic in the following fashion: pirqe# is connected to irq20, pirqf# to irq21, pirqg# to irq22, and pirqh# to irq23. this frees the legacy interrupts. if not needed fo r interrupts, thes e signals can be used as gpio. these signals are 5 v tolerant.
signal description 64 datasheet 2.7 usb interface table 2-7. usb interface signals (sheet 1 of 2) name type description usbp0p, usbp0n, usbp1p, usbp1n i/o universal serial bus port [1:0] differential : these differential pairs are used to transmit data/a ddress/command signals for ports 0 and 1. these ports can be routed to ehci controller 1. note: no external resistors are requir ed on these signals. the pch integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no exte rnal series resistor. usbp2p, usbp2n, usbp3p, usbp3n i/o universal serial bus port [3:2] differential : these differential pairs are used to transmit data/a ddress/command signals for ports 2 and 3. these ports can be routed to ehci controller 1. note: no external resistors are requir ed on these signals. the pch integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no exte rnal series resistor. usbp4p, usbp4n, usbp5p, usbp5n i/o universal serial bus port [5:4] differential : these differential pairs are used to transmit data/a ddress/command signals for ports 4 and 5. these ports can be routed to ehci controller 1. note: no external resistors are requir ed on these signals. the pch integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no exte rnal series resistor. usbp6p, usbp6n, usbp7p, usbp7n i/o universal serial bus port [7:6] differential : these differential pairs are used to transmit data/a ddress/command signals for ports 6 and 7. these ports can be routed to ehci controller 1. note: no external resistors are requir ed on these signals. the pch integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no exte rnal series resistor. usbp8p, usbp8n, usbp9p, usbp9n i/o universal serial bus port [9:8] differential : these differential pairs are used to transmit data/a ddress/command signals for ports 8 and 9. these ports can be routed to ehci controller 2. note: no external resistors are requir ed on these signals. the pch integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no exte rnal series resistor. usbp10p, usb p 10n, usbp11p, usbp11n i/o universal serial bus port [11:10] differential : these differential pairs are used to transmit data /address/command signals for ports 10 and 11. these ports can be ro uted to ehci controller 2. note: no external resistors are requir ed on these signals. the pch integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no exte rnal series resistor. usbp12p, usbp12n, usbp13p, usbp13n i/o universal serial bus port [13:12] differential : these differential pairs are used to transmit data /address/command signals for ports 13 and 12. these ports can be ro uted to ehci controller 2. note: no external resistors are requir ed on these signals. the pch integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no exte rnal series resistor.
datasheet 65 signal description 2.8 power management interface oc0# /gpio59 oc1# /gpio40 oc2# /gpio41 oc3# /gpio42 oc4# /gpio43 oc5# /gpio9 oc6# /gpio10 oc7# /gpio14 i overcurrent indicators : these signals set corresponding bits in the usb controllers to indicate that an overcurrent condition has occurred. oc[7:0]# may optionally be used as gpios. notes: 1. oc# pins are not 5 v tolerant. 2. depending on platform configuration, sharing of oc# pins may be required. 3. oc[3:0]# can only be used for ehci controller 1 4. oc[4:7]# can only be used for ehci controller 2 usbrbias o usb resistor bias: analog connection point for an external resistor. used to set transmit currents and internal load resistors. usbrbias# i usb resistor bi as complement: analog connection point for an external resistor. used to set tr ansmit currents and internal load resistors. table 2-8. power management in terface signals (sheet 1 of 4) name type description acpresent / gpio31 i acpresent: this input pin indicates wh en the platform is plugged into ac power or not. in a ddition to the previous intel ? me to ec communication, the pch uses this information to implement the deep s4/s5 policies. for example, the platform may be configured to enter deep s4/s5 when in s4 or s5 and on ly when running on battery. this is powered by deep s4/s5 well. this signal is muxed with gpio31. apwrok i active sleep well (asw) power ok: when asserted, indicates that power to the asw sub- system is stable. batlow# (mobile only) / gpio72 i battery low: an input from the battery to indicate that there is insufficient power to boot the system. assertion will prevent wake from s3?s5 state. this signal can also be enabled to cause an smi# when asserted. note: see ta b l e 2 . 2 4 for desktop implementa tion pin requirements. bmbusy# / gpio0 i bus master busy: generic bus master activity indication driven into the pch. can be configured to set the pm1_sts.bm_sts bit. can also be configured to assert indications transmitted from the pch to the processor using the pmsynch pin. clkrun# (mobile only) / gpio32 (desktop only) i/o pci clock run: used to support pci clkrun protocol. connects to peripherals that need to request cl ock restart or prevention of clock stopping. dpwrok i dpwrok: power ok indication for the vccdsw3_3 voltage rail. this input is tied together with rsmrst # on platforms that do not support deep s4/s5. this signal is in the rtc well. table 2-7. usb interface signals (sheet 2 of 2) name type description
signal description 66 datasheet drampwrok od o dram power ok: this signal should connect to the processor?s sm_drampwrok pin. the pch asserts this pin to indicate when dram power is stable. this pin requires an external pull-up lan_phy_pw r_ctrl / gpio12 o lan phy power control: lan_phy_pwr_ctrl should be connected to lan_disable_n on the phy. pch will drive lan_phy_pwr_ctrl low to put the phy into a low powe r state when functionality is not needed. notes: 1. lan_phy_pwr_ctrl can only be driven low if slp_lan# is deasserted. 2. signal can instead be used as gpio12. pltrst# o platform reset: the pch asserts pltrst# to reset devices on the platform (such as sio, fwh, lan, processor, etc.). the pch asserts pltrst# during power-up and when s/w initiates a hard reset sequence through the rese t control register (i/o register cf9h). the pch drives pltrst# active a minimum of 1 ms when initiated through the reset control register (i/o register cf9h). note: pltrst# is in the vccsus3_3 well. pwrbtn# i power button: the power button will cause smi# or sci to indicate a system request to go to a sleep stat e. if the system is already in a sleep state, this signal will cause a wake event. if pwrbtn# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the s5 state. override will occur even if the system is in the s1-s4 states. this signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input. this signal is in the dsw well. pwrok i power ok: when asserted, pwrok is an indication to the pch that all of its core power rails have been stable for 10 ms. pwrok can be driven asynchronously. when pwro k is negated, the pch asserts pltrst#. notes: 1. it is required that the power rails associated with pci/pcie typically the 3.3 v, 5 v, and 12 v core well rails) have been valid for 99 ms prior to pwrok assertion in order to comply with the 100 ms pci 2.3/pcie 1.1 specification on pltrst# deassertion. 2. pwrok must not glitch, even if rsmrst# is low. ri# i ring indicate: this signal is an input from a modem. it can be enabled as a wake event, and this is preserved across power failures. rsmrst# i resume well reset: this signal is used fo r resetting the resume power plane logic. this signal must be asserted for at least t201 after the suspend power wells are valid. wh en deasserted, this signal is an indication that the suspend power wells are stable. slp_a# o slp_a#: used to control power to the active sleep well (asw) of the pch. table 2-8. power management interface signals (sheet 2 of 4) name type description
datasheet 67 signal description slp_lan# / gpio29 o lan sub-system sleep control: when slp_lan# is deasserted it indicates that the phy device must be powered. when slp_lan# is asserted, power can be shut off to the phy device. slp_lan# will always be deasserted in s0 an d anytime slp_a# is deasserted. a slp_lan#/gpio select soft-strap can be used for systems not using slp_lan# functionality to reve rt to gpio29 usage. when soft- strap is 0 (default), pin function wi ll be slp_lan#. when soft-strap is set to 1, the pin returns to its regular gpio mode. the pin behavior is summarized in section 5.13.10.5 . slp_s3# o s3 sleep control: slp_s3# is for power plane control. this signal shuts off power to all non-critical systems when in s3 (suspend to ram), s4 (suspend to disk), or s5 (soft off) states. slp_s4# o s4 sleep control : slp_s4# is for power plane control. this signal shuts power to all non-critical systems when in the s4 (suspend to disk) or s5 (soft off) state. note: this pin must be used to cont rol the dram power in order to use the pch?s dram power-cy cling feature. refer to chapter 5.13.10.2 for details slp_s5# / gpio63 o s5 sleep control: slp_s5# is for power plane control. this signal is used to shut power off to all non-critical systems when in the s5 (soft off) states. pin may also be used as gpio63. slp_sus# o deep s4/s5 indication: when asserted low, th is signal indicates pch is in deep s4/s5 state where in ternal sus power is shut off for enhanced power saving. if deep s4/s 5 is not supported, then this pin can be left unconnected. this pin is in the dsw power well. stp_pci# / gpio34 o stop pci clock: this signal is an output to the clock generator for it to turn off the pci clock. susack# i susack#: if deep s4/s5 is suppo rted, the ec/motherboard controlling logic must change su sack# to match suswarn# once the ec/motherboard cont rolling logic has comple ted the preparations discussed in the descript ion for the suswarn# pin. note: susack# is only required to change in response to suswarn# if deep s4/s5 is supported by the platform. this pin is in the sus power well. sus_stat# / gpio61 o suspend status: this signal is asserted by the pch to indicate that the system will be entering a lo w power state soon. this can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. it can also be used by other peripherals as an indicati on that they should isolate their outputs that may be going to powered-off planes. p i n may also be used as gpio61. susclk / gpio62 o suspend clock: this clock is an output of the rtc generator circuit to use by other chips for refresh clock. pin may also be used as gpio62. table 2-8. power management in terface signals (sheet 3 of 4) name type description
signal description 68 datasheet suswarn# / suspwrdnack / gpio30 o suswarn#: this pin asserts lo w when the pch is planning to enter the deep s4/s5 power state and remove suspend power (using slp_sus#). the ec/motherboard controlling logic must observe edges on this pin, preparing for sus well power loss on a falling edge and preparing for sus well related activity (host/intel me wakes and runtime events) on a rising edge. susack# must be driven to match suswarn# once the above preparat ion is complete. susack# should be asserted within a minimal amount of time from suswarn# assertion as no wake events are supported if suswarn# is asserted but susack# is not asserted. plat forms supporting deep s4/s5, but not wishing to participate in the ha ndshake during wake and deep s4/ s5 entry may tie susack# to suswarn#. this pin may be muxed with a gpio for use in systems that do not support deep s4/s5. this pin is muxed with suspwrdnack since it is not needed in deep s4/s5 supported platforms. reset type: rsmrst# this signal is multiplexed with gpio30 and suspwrdnack. suspwrdna ck / suswarn# / gpio30 o suspwrdnack: active high. asserted by the pch on behalf of the intel me when it does not requ ire the pch suspend well to be powered. platforms are not expected to use this signal when the pch?s deep s4/ s5 feature is used. this signal is multiplexed with gpio30 and suswarn#. sys_pwrok i system power ok: this generic power good input to the pch is driven and utilized in a platform-s pecific manner. wh ile pwrok always indicates that the core wells of the pch are stable, sys_pwrok is used to inform the pch that power is stable to some other system component(s) and the system is re ady to start the exit from reset. sys_reset# i system reset : this pin forces an in ternal reset after being debounced. the pch will reset immediately if the smbus is idle; otherwise, it will wait up to 25 ms 2 ms for the smbus to idle before forcing a reset on the system. wake# i pci express* wake event: sideband wake signal on pci express asserted by components requesting wake up. table 2-8. power management interface signals (sheet 4 of 4) name type description
datasheet 69 signal description 2.9 processor interface 2.10 smbus interface 2.11 system management interface table 2-9. processor interface signals name type description rcin# i keyboard controller reset processor: the keyboard controller can generate init# to the processor. this saves the external or gate with the pch?s other sources of init#. when the pch detects the assertion of this signal, init# is generated using a vlw message to the processor. note: the pch will ignore rcin# assertion during transitions to the s3, s4, and s5 states. a20gate i a20 gate: a20gate is from the keyboard controller. the signal acts as an alternative method to fo rce the a20m# vlw message to the processor active. procpwrgd o processor power good: this signal should be connected to the processor?s uncorepwrgood input to indicate when the processor power is valid. pmsynch o power management sync: provides state information from the pch to the processor thrmtrip# i thermal trip : when low, this signal indicates that a thermal trip from the processor occurred, and th e pch will immediately transition to a s5 state. the pch will not wait for the processor stop grant cycle since the processor has overheated. table 2-10. sm bus interface signals name type description smbdata i/od smbus data: external pull-up resi stor is required. smbclk i/od smbus clock: external pull-up re sistor is required. smbalert# / gpio11 i smbus alert: this signal is used to wa ke the system or generate smi#. this signal may be used as gpio11. table 2-11. system management in terface signals (sheet 1 of 2) name type description intruder# i intruder detect: this signal can be set to disable the system if box detected open. this signal?s status is readable, so it can be used like a gpi if the intruder detection is not needed. sml0data i/od system management link 0 data: smbus link to external phy. external pull-up is required. sml0clk i/od system management link 0 clock: smbus link to external phy. external pull-up is required. sml0alert# / gpio60 o od smlink alert 0: output of the integrated lan controller to external phy. external pull-up resistor is required. this signal can instead be used as gpio60.
signal description 70 datasheet 2.12 real time clock interface 2.13 miscellaneous signals sml1alert# / pchhot# / gpio74 o od smlink alert 1: alert for the me smbus controller to optional embedded controller or bmc. extern al pull-up resistor is required. this signal can instead be used as pchhot# or gpio74 note: a soft-strap determines the na tive function sml1alert# or pchhot# usage. when soft-strap is 0, function is sml1alert#, when soft-strap is 1, function is pchhot#. sml1clk / gpio58 i/od system management link 1 clock: smbus link to optional embedded controller or bmc. extern al pull-up resistor is required. this signal can instead be used as gpio58 sml1data / gpio75 i/od system management link 1 data: smbus link to optional embedded controller or bmc. extern al pull-up resistor is required. this signal can instead be used as gpio75 table 2-12. real time clock interface name type description rtcx1 special crystal input 1: this signal is connected to the 32.768 khz crystal. if no external crystal is used, then rt cx1 can be driven with the desired clock rate. rtcx2 special crystal input 2: this signal is connected to the 32.768 khz crystal. if no external crystal is used, then rtcx2 should be left floating. table 2-13. miscellaneous signals (sheet 1 of 2) name type description intvrmen i internal voltage regulator enable: this signal enables the internal 1.05 v regulato rs when pulled high. this signal must be al ways pulled-up to vccrtc on desktop platforms and may optionally be pulled low on mobile platforms if using an external vr for the dcpsus rail. note: see vcccore signal description for behavior when intvrmen is sampled low (external vr mode). dswvrmen i deep s4/s5 well internal voltage regulator enable: this signal enables the internal dsw 1.05 v regulators. this signal must be alwa ys pulled-up to vccrtc. spkr o speaker: the spkr signal is the output of counter 2 and is internally ?anded? with port 61h bit 1 to pr ovide speaker data enable. this signal drives an external speaker dr iver device, which in turn drives the system speaker. upon pltr st#, its output state is 0. note: spkr is sampled as a functional strap. see section 2.27 for more details. there is a weak integrated pull-down resistor on spkr pin. table 2-11. system management in terface signals (sheet 2 of 2) name type description
datasheet 71 signal description rtcrst# i rtc reset: when asserted, this signal resets register bits in the rtc well. notes: 1. unless cmos is be ing cleared (only to be done in the g3 power state), the rtcrst# input must always be high when all other rtc power planes are on. 2. in the case where the rtc battery is dead or missing on the platform, the rtcrst# pin must rise before the rsmrst# pin. srtcrst# i secondary rtc reset: this signal resets the manageability register bits in the rtc well when the rtc battery is removed. notes: 1. the srtcrst# input must always be high when all other rtc power planes are on. 2. in the case where the rtc battery is dead or missing on the platform, the srtcrst# pin mu st rise before the rsmrst# pin. sml1alert#/ pchhot# / gpio74 od pchhot# : this signal is used to indicate a pch temperature out of bounds condition to an external ec, when pch temperature is greater than value programmed by bios. an external pull-u p resistor is required on this signal. note: a soft-strap determines the na tive function sml1alert# or pchhot# usage. when soft-s trap is 0, function is sml1alert#, when soft-strap is 1, function is pchhot#. init3_3v# o initialization 3.3 v: init3_3v# is asserted by the pch for 16 pci clocks to reset the processor. this signal is intended for firmware hub. gpio35 / nmi# (server / workstation only) od o nmi#: this is an nmi event indication to an external controller (such as a bmc) on server/w orkstation platforms. when operating as nmi event indica tion pin function (enabled when "nmi smi event native gpio enable" soft strap [pch strp9:bit 16] is set to 1), the pin is od (open drain). pcieclkrq2# / gpio20 / smi# (server / workstation only) od o smi#: this is an smi event indication to an external controller (such as a bmc) on server/w orkstation platforms. when operating as smi event indication pin function (enabled when "nmi smi event native gpio enable" soft strap [pch strp9:bit 16] is set to 1), the pin is od (open drain). table 2-13. miscellaneous signals (sheet 2 of 2) name type description
signal description 72 datasheet 2.14 intel ? high definition audio link table 2-14. intel ? high definition audio link signals name type description hda_rst# o intel ? high definition audio reset: master hardware reset to external codec(s). hda_sync o intel high definition audio sync: 48 khz fixed rate sample sync to the codec(s). also used to encode the stream number. note: this signal is sampled as a functional strap. see section 2.27 for more details. ther e is a weak integrated pull-down resistor on this pin. hda_bclk o intel high definition audio bit clock output: 24.000 mhz serial data clock generated by the intel high definition audio controller (the pch). hda_sdo o intel high definition audio serial data out: serial tdm data output to the codec(s). this seri al output is double-pumped for a bit rate of 48 mb/s for intel high definition audio. note: this signal is sampled as a functional strap. see section 2.27 for more details. ther e is a weak integrated pull-down resistor on this pin. hda_sdin[3:0] i intel high definition audio serial data in [3:0] : serial tdm data inputs from the codecs. the serial input is single-pumped for a bit rate of 24 mb/s for in tel high definition audio. these signals have integrated pull-dow n resistors, which are always enabled. note: during enumeration, the pch wi ll drive this signal. during normal operation, the codec will drive it. hda_dock_en# /gpio33 o intel high definition audio dock enable: this signal controls the external intel hd audio dockin g isolation logic. this is an active low signal. when deasserted the external docking switch is in isolate mode. when asserted the external docking switch electrically connects the intel hd audio dock signals to the corresponding pch signals. this signal can instea d be used as gpio33. hda_dock_rst# / gpio13 o intel high definition audio dock reset: this signal is a dedicated hda_rst# signal for the codec(s) in the docking station. aside from operating independently from the normal hda_rst# signal, it otherwise wo rks similarly to the hda_rst# signal. this signal is shared with gpio13. this signal defaults to gpio13 mode after pltrst#. bios is re sponsible for configuring gpio13 to hda_dock_rst# mode.
datasheet 73 signal description 2.15 controller link 2.16 serial peripheral interface (spi) 2.17 thermal signals table 2-15. controller link signals signal name type description cl_rst1# o controller link reset: controller link reset that connects to a wireless lan device supportin g intel active management te c h n o l o g y. cl_clk1 i/o controller link clock : bi-directional clock that connects to a wireless lan device supportin g intel active management te c h n o l o g y. cl_data1 i/o controller link data: bi-directional data that connects to a wireless lan device supportin g intel active management te c h n o l o g y. table 2-16. serial peripher al interface (spi) signals name type description spi_cs0# o spi chip select 0 : used as the spi bus request signal. spi_cs1# o spi chip select 1 : used as the spi bus request signal. spi_miso i spi master in slave out : data input pin for pch. spi_mosi i/o spi master out slave in : data output pin for pch. spi_clk o spi clock : spi clock signal, du ring idle the bus owner will drive the clock signal low. 17.86 mhz and 31.25 mhz. table 2-17. thermal signals (sheet 1 of 2) signal name type description pwm[3:0] (server/ workstation usage only); not available in mobile & desktop) od o fan pulse width modulation outputs: pulse width modulated duty cycle output signal s used for fan control. these signals are 5 v tolerant. tach0 / gpio17 tach1 / gpio1 tach2 / gpio6 tach3 / gpio7 tach4 / gpio68 tach5 / gpio69 tach6 / gpio70 tach7 / gpio71 (tach* signals used on server/ workstation only; not available in mobile & desktop) i fan tachometer inputs: tachometer pulse input signal that is used to measure fan speed. this signal is connected to the ?sense? signal on the fan. can instead be used as a gpio.
signal description 74 datasheet 2.18 testability signals note: jtag pin definitions are from ieee standard test access port and boundary-scan architecture (ieee std. 1149.1-2001) 2.19 clock signals sst (server/ workstation usage only; not available in mobile & desktop) i/o simple serial transport: single-wire, serial bus. connect to sst compliant devices such as sst thermal sensors or voltage sensors. peci i/o platform environment control interface: single-wire, serial bus. table 2-18. testability signals name type description jtag_tck i test clock input (tck): the test clock input provides the clock for the jtag test logic. jtag_tms i test mode select (tms): the signal is decoded by the test access port (tap) controller to control test operations. jtag_tdi i test data input (tdi): serial test instructions and data are received by the test logic at tdi. jtag_tdo od test data output (tdo): tdo is the serial output for test instructions and data from the test logic defined in this standard. table 2-17. thermal signals (sheet 2 of 2) signal name type description table 2-19. clock interface signals (sheet 1 of 3) name type description clkout_itpxdp_p, clkout_itpxdp_n o 100 mhz differential output to processor xdp/it p connector on platform clkout_dp_p, clkout_dp_n o 120 mhz differential output for displayport reference clkin_dmi_p, clkin_dmi_n i unused. note: external pull-down input termination is required clkout_dmi_p, clkout_dmi_n o 100 mhz pcie gen2 specificatio n jitter tolera nt differential output to processor. clkin_sata_p, clkin_sata_n i unused. note: external pull-down input termination is required clkin_dot96_p, clkin_dot96_n i unused. note: external pull-down input termination is required xtal25_in i connection for 25 mhz crystal to pch oscillator circuit. xtal25_out o connection for 25 mhz crystal to pch oscillator circuit. refclk14in i unused. note: external pull-down input termination is required
datasheet 75 signal description clkout_peg_a_p, clkout_peg_a_n o 100 mhz gen2 pcie specificatio n differential output to pci express* graphics device clkout_peg_b_p, clkout_peg_b_n o 100 mhz gen2 pcie specificat ion differential output to a second pci express graphics device peg_a_clkrq# / gpio47 (mobile only) , peg_b_clkrq# / gpio56 (mobile only) i clock request signals for pcie graphics slots can instead by used as gpios note: external pull-up resistor re quired if used for clkreq# functionality clkout_pcie[7:0] _p, clkout_pcie[7:0] _n o 100 mhz pcie gen2 specification differential output to pci express devices clkin_gnd0_p, clkin_gnd0_n (desktop only) clkin_gnd1_p, clkin_gnd1_n i requires external pull-down termination (can be shared between p and n signals of the differential pair). pcieclkrq0# / gpio73, pcieclkrq1# / gpio18, pcieclkrq3# / gpio25, pcieclkrq4# / gpio26 (all the above clkrq# signals are mobile only) i clock request signals for pci express 100 mhz clocks can instead by used as gpios note: external pull-up resistor re quired if used for clkreq# functionality pcieclkrq2# / gpio20 / smi#, pcieclkrq5# / gpio44, pcieclkrq6# / gpio45, pcieclkrq7# / gpio46 (smi# above is server/workstation only) i clock request signals for pci express 100 mhz clocks can instead by used as gpios note: external pull-up resistor re quired if used for clkreq# functionality clkout_pci[4:0] o single-ended, 33 mhz outputs to pci connectors/devices. one of these signals must be connected to clkin_pciloopback to function as a pci clock loopback. this allows skew control for variable lengths of clkout_pci[4:0] . clkin_pciloopba ck i 33 mhz pci clock feedback input, to reduce skew between pch on-die pci clock and pci clock observed by connected pci devices clkoutflex0 1 / gpio64 o configurable as a gpio or as a programmable output clock which can be configured as one of the following: ? 33 mhz ? 27 mhz (ssc/non-ssc) ? 48/24 mhz ? 14.318 mhz ? dc output logic ?0? table 2-19. clock interface signals (sheet 2 of 3) name type description
signal description 76 datasheet note: 1. it is highly recommended to prioritize 27 /14.318/24/48 mhz clocks on clkoutflex1 and clkoutflex3 outputs. intel does not recommend configuring the 27/14.318/24/48 mhz clocks on clkoutflex0 and clkoutflex2 if more than 2x 33 mhz clocks in addition to the feedback clock are used on the clkout_pci outputs. clkoutflex1 1 / gpio65 o configurable as a gpio or as a programmable output clock which can be configured as one of the following: ? non functional and unsupported clock output value (default) ? 27 mhz (ssc/non-ssc) ? 14.318 mhz output to sio/ec ? 48/24 mhz ? dc output logic ?0? clkoutflex2 1 / gpio66 o configurable as a gpio or as a programmable output clock which can be configured as one of the following: ? 33 mhz ? 25 mhz ? 27 mhz (ssc/non-ssc) ? 48/24 mhz ? 14.318 mhz ? dc output logic ?0? clkoutflex3 1 / gpio67 o configurable as a gpio or as a programmable output clock which can be configured as one of the following: ? 27 mhz (ssc/non ssc) ? 14.318 mhz output to sio ? 48/24 mhz (default) ? dc output logic ?0? xclk_rcomp i/o differential clock buffer impedance compensation : connected to an external precision resistor (90.9 ? 1%) to vccdiffclkn table 2-19. clock interface signals (sheet 3 of 3) name type description
datasheet 77 signal description 2.20 lvds signals all signals are mobile only, except as signals noted otherwise that are available in the desktop package. table 2-20. lvds interface signals name type description lvdsa_data[3:0] o lvds channel a differentia l data output - positive lvdsa_data#[3:0] o lvds channel a differential data output - negative lvdsa_clk o lvds channel a differentia l clock output - positive lvdsa_clk# o lvds channel a differential clock output - negative lvdsb_data[3:0] o lvds channel b differential data output - positive lvdsb_data#[3:0] o lvds channel b differential data output - negative lvdsb_clk o lvds channel b differential clock output - positive lvdsb_clk# o lvds channel b differential clock output - negative l_ddc_clk i/o edid support for flat panel display l_ddc_data i/o edid support for flat panel display l_ctrl_clk i/o control signal (clock) for external ssc clock chip control ? optional l_ctrl_data i/o control signal (data) for exte rnal ssc clock chip control ? optional l_vdd_en (available in desktop) o lvds panel power enable: panel power control enable control for lvds or embedded displayport*. this signal is also called vd d_dbl in the cpis specification and is used to control the vd c source to the panel logic. l_bklten (available in desktop) o lvds backlight enable: panel backlight enable control for lvds or embedded displayport. this signal is also called ena_bl in the cpis specification and is used to gate power into the backlight circuitry. l_bkltctl (available in desktop) o panel backlight brightness control: panel brightness control for lvds or embedded displayport. this signal is also called vary_bl in the cpis specification and is used as the pw m clock input signal. lvds_vrefh o test mode voltage reference. lvds_vrefl o test mode voltage reference. lvd_ibg i lvds reference current. lvd_vbg o test mode voltage reference.
signal description 78 datasheet 2.21 analog display /vga dac signals 2.22 intel ? flexible display interface (intel ? fdi) table 2-21. analog display interface signals name type description vga_red o a red analog video output: this signal is a vga analog video output from the internal color palette dac. vga_green o a green analog video output: this signal is a vga analog video output from the internal color palette dac. vga_blue o a blue analog video output: this signal is a vga analog video output from the internal color palette dac. dac_iref i/o a resistor set: set point resistor for th e internal color palette dac. a 1 k ? 1% resistor is required between dac_iref and motherboard ground. vga_hsync o hvcmos vga horizontal synchronization: this signal is used as the horizontal sync (polarity is programmable) or ?sync interval?. 2.5 v output vga_vsync o hvcmos vga vertical synchronization: this signal is used as the vertical sync (polarity is programmable). 2.5 v output. vga_ddc_clk i/o cod monitor control clock vga_ddc_data i/o cod monitor control data vga_irtn i/o cod monitor interrupt return table 2-22. intel ? flexible display interface signals signal name type description fdi_rxp[3:0] i display link 1 positive data in fdi_rxn[3:0] i display link 1 negative data in fdi_fsync[0] odisplay link 1 frame sync fdi_lsync[0] o display link 1 line sync fdi_rxp[7:4] i display link 2 positive data in fdi_rxn[7:4] i display link 2 negative data in fdi_fsync[1] odisplay link 2 frame sync fdi_lsync[1] o display link 2 line sync fdi_int o used for display interrupts from pch to processor.
datasheet 79 signal description 2.23 digital display signals table 2-23. digital display inte rface signals (sheet 1 of 3) name type description ddpb_[3:0]p o port b: capable of sdvo / hdmi / dvi / displayport sdvo ddpb_[0]p: red ddpb_[1]p: green ddpb_[2]p: blue ddpb_[3]p: clock hdmi / dvi port b data and clock lines ddpb_[0]p: tmdsb_data2 ddpb_[1]p: tmdsb_data1 ddpb_[2]p: tmdsb_data0 ddpb_[3]p: tmdsb_clk displayport port b ddpb_[0]p: display port lane 0 ddpb_[1]p: display port lane 1 ddpb_[2]p: display port lane 2 ddpb_[3]p: display port lane 3 ddpb_[3:0]n o port b: capable of sdvo / hdmi / dvi / displayport sdvo ddpb_[0]n: red complement ddpb_[1]n: green complement ddpb_[2]n: blue complement ddpb_[3]n: clock complement hdmi / dvi port b data and clock line complements ddpb_[0]n: tmdsb_data2b ddpb_[1]n: tmdsb_data1b ddpb_[2]n: tmdsb_data0b ddpb_[3]n: tmdsb_clkb displayport port b ddpb_[0]n: display port lane 0 complement ddpb_[1]n: display port lane 1 complement ddpb_[2]n: display port lane 2 complement ddpb_[3]n: display port lane 3 complement ddpb_auxp i/o port b: displayport aux ddpb_auxn i/o port b: displayport aux complement ddpb_hpd i port b: tmdsb_hpd hot plug detect sdvo_ctrlclk i/o port b: hdmi control clock. shared with port b sdvo
signal description 80 datasheet sdvo_ctrldata i/o port b: hdmi control data. shared with port b sdvo sdvo_intp i sdvo_intp: serial digital video input interrupt sdvo_intn i sdvo_intn: serial digital video inpu t interrupt complement. sdvo_tvclkinp i sdvo_tvclkinp: serial digital video tvout synchronization clock. sdvo_tvclkinn i sdvo_tvclkinn: serial digital video tvout synchronization clock complement. sdvo_stallp i sdvo_stallp : serial digital vi deo field stall. sdvo_stalln i sdvo_stalln: serial digital video fi eld stall complement. ddpc_[3:0]p o port c: capable of hdmi / dvi / dp hdmi / dvi port c data and clock lines ddpc_[0]p: tmdsc_data2 ddpc_[1]p: tmdsc_data1 ddpc_[2]p: tmdsc_data0 ddpc_[3]p: tmdsc_clk displayport port c ddpc_[0]p: display port lane 0 ddpc_[1]p: display port lane 1 ddpc_[2]p: display port lane 2 ddpc_[3]p: display port lane 3 ddpc_[3:0]n o port c: capable of hdmi / dvi / displayport hdmi / dvi port c data and clock line complements ddpc_[0]n: tmdsc_data2b ddpc_[1]n: tmdsc_data1b ddpc_[2]n: tmdsc_data0b ddpc_[3]n: tmdsc_clkb displayport port c complements ddpc_[0]n: lane 0 complement ddpc_[1]n: lane 1 complement ddpc_[2]n: lane 2 complement ddpc_[3]n: lane 3 complement ddpc_auxp i/o port c: display port aux ddpc_auxn i/o port c: display port aux complement ddpc_hpd i port c: tmdsc_hpd hot plug detect ddpc_ctrlclk i/o hdmi port c control clock ddpc_ctrldata i/o hdmi port c control data table 2-23. digital display inte rface signals (sheet 2 of 3) name type description
datasheet 81 signal description ddpd_[3:0]p o port d: capable of hdmi / dvi / dp hdmi / dvi port d data and clock lines ddpd_[0]p: tmdsc_data2 ddpd_[1]p: tmdsc_data1 ddpd_[2]p: tmdsc_data0 ddpd_[3]p: tmdsc_clk displayport port d ddpd_[0]p: display port lane 0 ddpd_[1]p: display port lane 1 ddpd_[2]p: display port lane 2 ddpd_[3]p: display port lane 3 ddpd_[3:0]n o port d: capable of hdmi / dvi / displayport hdmi / dvi port d data and clock line complements ddpd_[0]n: tmdsc_data2b ddpd_[1]n: tmdsc_data1b ddpd_[2]n: tmdsc_data0b ddpd_[3]n: tmdsc_clkb displayport port d complements ddpd_[0]n: lane 0 complement ddpd_[1]n: lane 1 complement ddpd_[2]n: lane 2 complement ddpd_[3]n: lane 3 complement ddpd_auxp i/o port d: displayport aux ddpd_auxn i/o port d: displayport aux complement ddpd_hpd i port d: tmdsd_hpd hot plug detect ddpd_ctrlclk i/o hdmi port d control clock ddpd_ctrldata i/o hdmi port d control data table 2-23. digital display inte rface signals (sheet 3 of 3) name type description
signal description 82 datasheet 2.24 general purpose i/o signals notes: 1. gpio configuration registers within the core well are reset whenever pwrok is deasserted. 2. gpio configuration registers within th e suspend well are reset when rsmrst# is asserted, cf9h reset (06h or 0eh), or sys_reset# is asserted. however, cf9h reset and sys_reset# events can be ma sked from resetting the suspend well gpio by programming appropriate gpio reset select (gpio_rst_sel) registers. 3. gpio24 is an exception to the other gpio signals in the suspend well and is not reset by cf9h reset (06h or 0eh) table 2-24. general purpose i/o signals (sheet 1 of 4) name type tolerance power well default blink capability description gpio75 i/o 3.3 v suspend native no multiplexed with sml1data (note 11) gpio74 i/o 3.3 v suspend native no multiplexed with sml1alert#/ pchhot# (note 11) gpio73 (mobile only) i/o 3.3 v suspend native no multiplexed with pcieclkrq0# gpio72 i/o 3.3 v suspend native (mobile only) no mobile: multiplexed with batlow#. desktop: unmultiplexed; requires pull-up resist or. (note 4) gpio[71:70] i/o 3.3 v core native no desktop: multiplexed with tach[7:6] mobile: used as gpio only gpio[69:68] i/o 3.3 v core gpi no desktop: multiplexed with tach[5:4] mobile: used as gpio only gpio67 i/o 3.3 v core native no multiplexed with clkoutflex3 gpio66 i/o 3.3 v core native no multiplexed with clkoutflex2 gpio65 i/o 3.3 v core native no multiplexed with clkoutflex1 gpio64 i/o 3.3 v core native no multiplexed with clkoutflex0 gpio63 i/o 3.3 v suspend native no multiplexed with slp_s5# gpio62 i/o 3.3 v suspend native no multiplexed with susclk gpio61 i/o 3.3 v suspend native no multiplexed with sus_stat# gpio60 i/o 3.3 v suspend native no multiplexed with sml0alert# gpio59 i/o 3.3 v suspend native no multiplexed with oc0# (note 11) gpio58 i/o 3.3 v suspend native no multiplexed with sml1clk gpio57 i/o 3.3 v suspend gpi no unmultiplexed gpio56 (mobile only) i/o 3.3 v suspend native no mobile: multiplexed with peg_b_clkrq# gpio55 i/o 3.3 v core native no desktop: multiplexed with gnt3# mobile: used as gpio only
datasheet 83 signal description gpio54 i/o 5.0 v core native no desktop: multiplexed with req3#. (note 11) mobile: used as gpio only gpio53 i/o 3.3 v core native no desktop: multiplexed with gnt2# mobile: used as gpio only gpio52 i/o 5.0 v core native no desktop: multiplexed with req2#. (note 11) mobile: used as gpio only gpio51 i/o 3.3 v core native no desktop: multiplexed with gnt1# mobile: used as gpio only gpio50 i/o 5.0 v core native no desktop: multiplexed with req1#. (note 11) mobile: used as gpio only gpio49 i/o 3.3 v core gpi no multiplexed with sata5gp and temp_alert# gpio48 i/o 3.3 v core gpi no multiplexed with sdataout1. gpio47 (mobile only) i/o 3.3 v suspend native no multiplexed with peg_a_clkrq# gpio46 i/o 3.3 v suspend native no multiplexed with pcieclkrq7# gpio45 i/o 3.3 v suspend native no multiplexed with pcieclkrq6# gpio44 i/o 3.3 v suspend native no multiplexed with pcieclkrq5# gpio[43: 40] i/o 3.3 v suspend native no multiplexed with oc[4:1]# (note 11) gpio39 i/o 3.3 v core gpi no multiplexed with sdataout0. gpio38 i/o 3.3 v core gpi no multiplexed with sload. gpio37 i/o 3.3 v core gpi no multiplexed with sata3gp. gpio36 i/o 3.3 v core gpi no multiplexed with sata2gp. gpio35 i/o 3.3 v core gpo no multiplexed with nmi#. gpio34 i/o 3.3 v core gpi no multiplexed with stp_pci# gpio33 i/o 3.3 v core gpo no mobile: multiplexed with hda_dock_en# (mobile only) (note 4) desktop: used as gpio only gpio32 (not available in mobile) i/o 3.3 v core gpo, native (mobile only) no unmultiplexed (desktop only) mobile only: used as clkrun#, unavailable as gpio (note 4) gpio31 i/o 3.3 v dsw gpi yes multiplexed with acpresent(mobile only) (note 6) desktop: used as gpio31 only. unavailable as acpresent table 2-24. general purpose i/o signals (sheet 2 of 4) name type tolerance power well default blink capability description
signal description 84 datasheet gpio30 i/o 3.3 v suspend native yes multiplexed with suspwrdnack, suswarn# desktop: can be configured as suswarn# or gpio30 only. cannot be used as suspwrdnack. mobile: used as suspwrdnack, suswarn#, or gpio30 gpio29 i/o 3.3 v suspend gpi no multiplexed with slp_lan# pin usage as gpio is determined by slp_lan#/gpio select soft-strap. when soft-strap = 1, pin can be used as gpio and defaults to gp input (note 10) gpio28 i/o 3.3 v suspend gpo yes unmultiplexed gpio27 i/o 3.3 v dsw gpi yes unmultiplexed. can be configured as wake input to allow wakes from deep s4/s5. gpio26 (mobile only) i/o 3.3 v suspend native yes mobile: multiplexed with pcieclkrq4# gpio25 (mobile only) i/o 3.3 v suspend native yes mobile: multiplexed with pcieclkrq3# gpio24 i/o 3.3 v suspend gpo yes desktop: can be used as proc_missing configured using intel me firmware. mobile: unmultiplexed note: gpio24 configuration register bits are not cleared by cf9h reset event. gpio23 i/o 3.3 v core native yes multiplexed with ldrq1#. gpio22 i/o 3.3 v core gpi yes multiplexed with sclock gpio21 i/o 3.3 v core gpi yes multiplexed with sata0gp gpio20 i/o 3.3 v core native yes multiplexed with pcieclkrq2#, smi# gpio19 i/o 3.3 v core gpi yes multiplexed with sata1gp gpio18 (mobile only) i/o 3.3 v core native yes (note 7) mobile: multiplexed with pcieclkrq1# gpio17 i/o 3.3 v core gpi yes desktop: multiplexed with tach0. mobile: used as gpio17 only. gpio16 i/o 3.3 v core gpi yes multiplexed with sata4gp gpio15 i/o 3.3 v suspend gpo yes unmultiplexed gpio14 i/o 3.3 v suspend native yes multiplexed with oc7# gpio13 i/o 3.3 v suspend gpi yes multiplexed with hda_dock_rst# (mobile only) (note 4) desktop: used as gpio only table 2-24. general purpose i/o signals (sheet 3 of 4) name type tolerance power well default blink capability description
datasheet 85 signal description notes: 1. all gpios can be configured as either input or output. 2. gpi[15:0] can be configured to cause a smi# or sci. note that a gpi can be routed to either an smi# or an sci, but not both. 3. some gpios exist in the vccsus3_3 power plan e. care must be take n to make sure gpio signals are not driven high into powered-down planes. also, external devices should not be driving powered down gpios high. some gpios may be connected to pins on devices that exist in the core well. if these gpios are outp uts, there is a danger that a loss of core power (pwrok low) or a power bu tton override event will result in the pch driving a pin to a logic 1 to another device that is powered down. 4. the functionality that is multiplexed with the gpio may not be used in desktop configuration. 5. when this signal is configured as gpo the output stage is an open drain. 6. in an intel ? me disabled system, gpio31 may be used as acpresent from the ec. 7. gpio18 will toggle at a frequency of approxim ately 1 hz when the signal is programmed as a gpio (when configured as an output) by bios. 8. for gpios where gpio vs. native mode is configured using spi soft strap, the corresponding gpio_use_sel bits for these gpios have no effect . the gpio_use_sel bits for these gpios may change to reflect th e soft-strap configuration even though gpio lockdown enable (gle) bit is set. 9. these pins are used as functional straps. see section 2.27 for more details. 10. once soft-strap is set to gpio mode, this pin will default to gp input. when soft-strap is slp_lan# usage and if host bios does not co nfigure as gp output for slp_lan# control, slp_lan# behavior will be based on the sett ing of the rtc backed slp_lan# default bit (d31:f0:a4h:bit 8). 11. when the multiplexed gpio is used as gpio functionality, ca re should be taken to ensure the signal is stable in its inactive state of the native functionality, immediately after reset until it is initialized to gpio functionality. gpio12 i/o 3.3 v suspend native yes multiplexed with lan_phy_pwr_ctrl. gpio / native functionality controlled using soft strap (note 8) gpio11 i/o 3.3 v suspend native yes multiplexed with smbalert#. (note 11) gpio10 i/o 3.3 v suspend native yes multiplexed with oc6# (note 11) gpio9 i/o 3.3 v suspend native yes multiplexed with oc5# (note 11) gpio8 i/o 3.3 v suspend gpo yes unmultiplexed gpio[7:6] i/o 3.3 v core gpi yes multiplexed with tach[3:2]. mobile: used as gpio[7:6] only. gpio[5:2] i/od 5 v core gpi yes multiplexed pirq[h:e]# (note 5). gpio1 i/o 3.3 v core gpi yes multiplexed with tach1. mobile: used as gpio1 only. gpio0 i/o 3.3 v core gpi yes multiplexed with bmbusy# table 2-24. general purpose i/o signals (sheet 4 of 4) name type tolerance power well default blink capability description
signal description 86 datasheet 2.25 manageability signals the following signals can be optionally us ed by intel management engine supported applications and appropriately configured by intel management engine firmware. when configured and used as a manageability function, the associated host gpio functionality is no longer available. if the manageability function is not used in a platform, the signal can be used as a host general purpose i/o or a native function. note: slp_lan# may also be configured by intel ? me fw in sx/moff. please refer to slp_lan#/ gpio29 signal description for details. table 2-25. manageability signals name type description suswarn# / suspwrdnack / gpio30 (mobile only) i/o used by intel ? me as either suswarn# in deep s4/s5 state supported platforms or as suspwrdnack in non deep s4/s5 state supported platforms. note: this signal is in th e suspend power well. acpresent / gpio31 (mobile only) i/o input signal from the embedded controller (ec) on mobile systems to indicate ac power source or the system battery. active high indicates ac power. note: this signal is in the deep s4/s5 power well. sata5gp / gpio49 / temp_alert# i/o used as an alert (active low) to indicate to the external controller (such as ec or sio) that temperatures are out of range for the pch or graphics/memory controller or the processor core. note: this signal is in the core power well. gpio24 / proc_missing (desktop only) i/o used to indicate processor missing to the intel management engine. note: this signal is in th e suspend power well.
datasheet 87 signal description 2.26 power and ground signals table 2-26. power and ground signals (sheet 1 of 2) name description dcprtc decoupling: this signal is for rtc decoupli ng only. this signal requires decoupling. dcpsst decoupling: internally generated 1.5 v powe red off of suspend well. this signal requires decoupling. decoupling is required even if this feature is not used. dcpsus 1.05 v suspend well power. internal vr mode (intvrmen sampled high): well ge nerated internally. pins should be left no connect external vr mode (intvrmen sampled low): well supplied externally. pins should be powered by 1.05 suspend po wer supply. decoupli ng capacitors are required. note: external vr mode applies to mobile only. dcpsusbyp internally generated 1.05 v deep s4/s5 well power. this rail should not be supplied externally. note: no decoupling capacitors shou ld be used on this rail. v5ref reference for 5 v tolerance on core well inputs. this power may be shut off in s3, s4, s5 or g3 states. v5ref_sus reference for 5 v tolerance on suspen d well inputs. th is power is not expected to be shut off un less the system is unplugged. vcccore 1.05 v supply for core well logic. this po wer may be shut off in s3, s4, s5 or g3 states. note: in external vr mode (intvrmen sampled low), the voltage level of vcccore may be indeterminate while dcpsus (1.05v suspend well power) supply ramps and prior to pwrok assertion. vcc3_3 3.3 v supply for core well i/o buffers. this power may be shut off in s3, s4, s5 or g3 states. vccasw 1.05 v supply for the active sleep we ll. provides power to the intel ? me and integrated lan. this plane must be on in s0 and ot her times the intel me or integrated lan is used. vccdmi power supply for dmi. 1.05 v or 1.0 v based on the processor vccio voltage. please refer to the respective processor docu mentation to find the a ppropriate voltage level. vccdiffclkn 1.05 v supply for differential clock buffers. this power is supplied by the core well. vccrtc 3.3 v (can drop to 2.0 v min. in g3 st ate) supply for the rt c well. this power is not expected to be shut off unless the rtc battery is removed or completely drained. note: implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. clearing cmos can be done by using a jumper on rtcrst# or gpi. vccio 1.05 v supply for core well i/o buffers. th is power may be shut off in s3, s4, s5 or g3 states. vccsus3_3 3.3 v supply for suspend well i/o buffers . this power is not expected to be shut off unless the system is unplugged. vccsushda suspend supply for intel ? hd audio. this pin can be either 1.5 or 3.3 v.
signal description 88 datasheet vccvrm 1.5 v/1.8 v supply for internal pll and vrms vccdfterm 1.8 v or 3.3 v supply for df_tvs. this pin should be pulled up to 1.8 v or 3.3 v core. vccadplla 1.05 v supply for display pll a analog power. this power is supplied by the core well. vccadpllb 1.05 v supply for display pll b analog power. this power is supplied by the core well. vccadac 3.3 v supply for display dac analog power. this power is supplied by the core well. vss grounds. vccaclk 1.05 v analog power supply for internal clock pll. this po wer is supplied by the core well. note: this pin can be left as no connect vccapllexp 1.05 v analog power for dmi. this power is supplied by the core well. note: this pin can be left as no connect vccaplldmi2 1.05 v analog power for internal pll. this power is supplied by core well. note: this pin can be left as no connect vccafdipll 1.05 v analog power supply for the fdi pll. this power is supplied by core well. note: this pin can be left as no connect vccapllsata 1.05 v analog power supply for sata pll. this power is supplied by core well. this rail requires an lc filter when power is supplied from an external vr. note: this pin can be left as no connect vccalvds (mobile only) 3.3 v analog power supply for lvds, th is power is supplied by core well. vcctxlvds (mobile only) 1.8 v i/o power supply for lvds. this power is supplied by core well. v_proc_io powered by the same supply as the proce ssor i/o voltage. this supply is used to drive the processor interface signal s. please refer to the respective processor documentation to find the appropriate voltage level. vccdsw3_3 3.3 v supply for deep s4/s5 wells. if platform does not support deep s4/s5 then tie to vccsus3_3. vccspi 3.3 v supply for spi controller logic. this rail must be powered when vccasw is powered. note: this rail can be optionally po wered on 3.3 v suspend power (vccsus3_3) based on platform needs. vccssc 1.05 v supply for integrated clock spre ad modulators. this power is supplied by core well. vccclkdmi 1.05 v supply for dmi di fferential clock buffer table 2-26. power and ground signals (sheet 2 of 2) name description
datasheet 89 signal description 2.27 pin straps the following signals are used for static configuration. they are sampled at the rising edge of pwrok to select configurations (excep t as noted), and then revert later to their normal usage. to invoke the associated mode, the signal should be driven at least four pci clocks prior to the time it is sampled. the pch implements soft straps, which are us ed to configure specific functions within the pch and processor very early in the boot process before bios or sw intervention. when descriptor mode is enabled, the pch will read soft strap data out of the spi device prior to the deassertion of reset to both the intel management engine and the host system. please refer to section 5.24.2 for information on descriptor mode table 2-27. functional strap definitions (sheet 1 of 4) signal usage when sampled comment spkr no reboot rising edge of pwrok the signal has a weak internal pu ll-down. note that the internal pull-down is disabled after pltrst# de asserts. if the signal is sampled high, this indicates that the system is strapped to the ?no reboot? mode (pch will disable the tco timer system reboot feature). the status of this strap is readable using the no reboot bit (chipset config regist ers: offset 3410h:bit 5). init3_3v# reserved rising edge of pwrok this signal has a weak internal pull -up. note that the internal pull- up is disabled after pltrst# deasserts. note: this signal should not be pulled low gnt3# / gpio55 to p - b l o c k swap override rising edge of pwrok the signal has a weak internal pull -up. note that the internal pull- up is disabled after pltrst# deasserts. if the signal is sampled low, this indicates that the syst em is strapped to the ?topblock swap? mode (pch inverts a16 for al l cycles targeting bios space). the status of this strap is readab le using the top swap bit (chipset config registers: offset 3414h:bit 0). note that software will not be able to clear the top-swap bi t until the system is rebooted without gnt3# being pulled down. intvrmen integrated 1.05 v vrm enable / disable always integrated 1.05 v vrms is enabled when high external vr power source is us ed for dcpsus when sampled low. notes: 1. external vr powering option is for mobile only. other systems should not pull the strap low. 2. see vcccore signal de scription for behavior when intvrmen is sampled low (external vr mode).
signal description 90 datasheet gnt1#/ gpio51 boot bios strap bit 1 bbs1 rising edge of pwrok this signal has a weak internal pull-up. note that the internal pull-u p is disabled after pltrst# deasserts.this field de termines the destinatio n of accesses to the bios memory range. also controll able using boot bios destination bit (chipset config registers: offset 3410h:bit 11). this strap is used in conjunction with boot bios destination selection 0 strap. notes: 1. if option 00 (lpc) is selected, bios may still be placed on lpc, but all platforms are required to have spi flash connected directly to the pch's spi bus with a valid descriptor in order to boot. 2. booting to pci is intended fo r debut/testing only. boot bios destination select to lpc/pci by functional strap or using boot bios destination bit will not affect spi accesses initiated by intel ? me or integrated gbe lan. 3. pci boot bios destination is not supported on mobile sata1gp/ gpio19 boot bios strap bit 0 bbs0 rising edge of pwrok this signal has a weak internal pull-up. note that the internal pull-up is disabled after pltrst# deasserts. this field determines the destin ation of accesses to the bios memory range. also controllable using boot bios destination bit (chipset config registers: offset 3410h:bit 10). this strap is used in conjunction with boot bios destination selection 1 strap. notes: 1. if option 00 (lpc) is selected, bi os may still be placed on lpc, but all platforms are required to have spi flash connected directly to the pch's spi bus with a valid descriptor in order to boot. 2. booting to pci is intended fo r debut/testing only. boot bios destination select to lpc/pci by functional strap or using boot bios destination bit will not affect spi accesses initiated by management engine or integrated gbe lan. 3. pci boot bios destination is not supported on mobile. gnt2#/ gpio53 esi strap (server/ workstation only) rising edge of pwrok this signal has a weak internal pull-up. tying this strap low configures dmi for esi compatible operation. notes: 1. the internal pull-up is disa bled after pltrst# deasserts. 2. esi compatible mode is for serv er platforms only. this signal should not be pulled lo w for desktop and mobile. table 2-27. functional strap definitions (sheet 2 of 4) signal usage when sampled comment bit11 bit 10 boot bios destination 01 reserved 10 pci 11 spi 00 lpc bit11 bit 10 boot bios destination 01 reserved 10 pci 11 spi 00 lpc
datasheet 91 signal description hda_sdo flash descriptor security override / intel me debug mode rising edge of pwrok signal has a weak internal pull-down. if strap is sampled low, the securi ty measures defined in the flash descriptor will be in effect (default) if sa mpled high, the flash descriptor security will be overridden. this strap should only be asserted high using external pull-up in manufacturing/debug environments only. notes: 1. the weak internal pull-down is disabled after pltrst# deasserts. 2. asserting the hda_sdo high on the rising edge of pwrok will also halt intel ? management engine after chipset bring up and disable runtime intel me featur es. this is a debug mode and must not be asserted af ter manufacturing/debug. df_tvs dmi and fdi tx/rx te rm i n a t i o n voltage rising edge of pwrok this signal has a weak internal pull-down. note: the internal pull-down is disa bled after pltrst# deasserts. gpio28 on-die pll voltage regulator rising edge of rsmrst# pin this signal has a weak internal pull-up. note: the internal pull-up is disa bled after rsmrst# deasserts. the on-die pll voltage regulator is enabled when sampled high. when sampled low the on-die pll voltage regulator is disabled. hda_sync on-die pll voltage regulator voltage select rising edge of rsmrst# pin this signal has a weak internal pull-down. on die pll vr is supplied by 1.5 v from vccvrm when sampled high, 1.8 v from vccvrm when sampled low. gpio15 tls confidentiality rising edge of rsmrst# pin low = intel me crypto transport la yer security (tls) cipher suite with no confidentiality high = intel me crypto tls ciph er suite with confidentiality this signal has a weak internal pull-down. notes: 1. a strong pull-up may be ne eded for gpio functionality 2. this signal must be pulled up to support intel amt with tls. intel me configuration parameters also need to be set correctly to enable tls. l_ddc_dat a lvds detected rising edge of pwrok when ?1?- lvds is detected; wh en ?0?- lvds is not detected. note: this signal has a weak internal pull-down. the internal pull- down is disabled after pltrst# deasserts. sdvo_ctrl data port b detected rising edge of pwrok when ?1?- port b is detected; wh en ?0?- port b is not detected this signal has a weak internal pull-down. note: the internal pull-down is disa bled after pltrst# deasserts. ddpc_ctrl data port c detected rising edge of pwrok when ?1?- port c is detected; when ?0?- po rt c is not detected this signal has a weak internal pull-down. note: the internal pull-down is disa bled after pl trst# deasserts. ddp d_ctrl data port d detected rising edge of pwrok when ?1?- port d is detected; when ?0?- port d is not detected this signal has a weak internal pull-down. note: the internal pull-down is disa bled after pltrst# deasserts. dswvrmen deep s4/s5 well on-die voltage regulator enable always if strap is sampled high, the in tegrated deep s4/s5 well (dsw) on-die vr mode is enabled. table 2-27. functional strap definitions (sheet 3 of 4) signal usage when sampled comment
signal description 92 datasheet note: see section 3.1 for full details on pull-up/pull-down resistors. 2.28 external rtc circuitry the pch implements an internal oscillator circuit that is sensitive to step voltage changes in vccrtc. figure 2-2 shows an example schematic recommended to ensure correct operation of the pch rtc. notes: 1. the exact capacitor values for c1 and c2 must be based on the crystal maker recommendations. 2. reference designators are arbitrarily assigned. 3. for platforms not supporting deep s4/s5, th e vccdsw3_3 pins will be connected to the vccsus3_3 pins. 4. vbatt is voltage provided by th e rtc battery (suc h as coin cell). 5. vccrtc, rtcx1, rtcx2, rtcrst#, and srtcrst# are pch pins. 6. vccrtc powers pch rtc well. 7. rtcx1 is the input to the internal oscillator. 8. rtcx2 is the amplified feedba ck for the external crystal. sata2gp/ gpio36 reserved rising edge of pwrok this signal has a weak internal pull-down. notes: 1. the internal pull-down is di sabled after pltrst# deasserts. 2. this signal should not be pull ed high when strap is sampled. sata3gp/ gpio37 reserved rising edge of pwrok this signal has a weak internal pull-down. notes: 1. the internal pull-down is di sabled after pltrst# deasserts. 2. this signal should not be pu lled high when strap is sampled. gpio8 reserved rising edge of rsmrst# this signal has a we ak internal pull-up. notes: 1. the internal pull-up is disa bled after rsmrst# deasserts. 2. this signal should not be pu lled low when strap is sampled. table 2-27. functional strap definitions (sheet 4 of 4) signal usage when sampled comment figure 2-2. example external rtc circuit 32.768 khz xtal 10m ? vccrtc rtcx2 rtcx1 vbatt 1uf 1 k ? vccdsw3_3 (see note 3) c1 c2 r1 rtcrst# 1.0 uf 20 k? 0.1uf srtcrst# 20 k? 1.0 uf schottky diodes
datasheet 93 pch pin states 3 pch pin states 3.1 integrated pull-ups and pull-downs table 3-1. integrated pull-up and pull-down resistor s (sheet 1 of 2) signal resistor ty pe nominal no tes cl_clk1 pull-up/pull- down 32/100 8 , 13 cl_data1 pull-up/pull- down 32/100 8 , 13 clkoutflex[3:0]/gpio[67:64] pull-down 20k 1 , 10 gpio15 pull-down 20k 3 hda_sdin[3:0] pull-down 20k 2 hda_sync, hda_sdo pull-down 20k 2 , 5 gnt[3:1]#/gpio[55,53,51] pull-up 20k 3 , 6 , 7 gpio8 pull-up 20k 3 , 12 lad[3:0]# / fwh[3:0]# pull-up 20k 3 ldrq0#, ldrq1# / gpio23 pull-up 20k 3 df_tvs pull-down 20k 8 pme# pull-up 20k 3 init3_3v# pull-up 20k 3 pwrbtn# pull-up 20k 3 spi_mosi pull-down 20k 3 , 5 spi_miso pull-up 20k 3 spkr pull-down 20k 3 , 9 tach[7:0]/gpio[71:68,7,6,1,17] pull-up 20k 3 (only on tach[7:0]) usb[13:0] [p,n] pull-down 20k 4 ddp[d:c]_crtldata pull-down 20k 3 , 9 sdvo_ctrldata,l_ddc_data pull-down 20k 3 , 9 sdvo_intp, sdvo_intn pull-down 50 18 sdvo_tvclkinp, sdvo_tvclkinn pull-down 50 18 sdvo_stallp, sdvo_stalln pull-down 50 18 batlow#/gpio72 pull-up 20k 3 clkout_pci[4:0] pull-down 20k 1 , 10 gpio27 pull-up 20k 3 , 14 jtag_tdi, jtag_tms pull-up 20k 1 , 11 jtag_tck pull-down 20k 1 , 11 gpio28 pull-up 20k 3 , 12
pch pin states 94 datasheet notes: 1. simulation data shows that these resistor values can range from 10 k ? to 40 k ? . 2. simulation data shows that these resistor values can range from 9 k ? to 50 k ? . 3. simulation data shows that these resistor values can range from 15 k ? to 40 k ? . 4. simulation data shows that these resistor values can range from 14.25 k ? to 24.8 k ? . 5. the pull-up or pull-down on this signal is on ly enabled at boot/reset for strapping function. 6. the pull-up on this signal is not enabled when pcirst# is high. 7. the pull-up on this signal is not enabled when pwrok is low. 8. simulation data shows that these resistor values can range from 15 k ? to 31 k ? . 9. the pull-up or pull-down is not active when pltrst# is not asserted. 10. the pull-down is enabled when pwrok is low. 11. external termination is also required on these signals for jtag enabling. 12. pull-up is disabled afte r rsmrst# is deasserted. 13. the controller link clock and data buffers use internal pull -up or pull-down resistors to drive a logical 1 or 0. 14. pull-up is enabled only in deep s4/s5 state. 15. pull-down is enabled only in deep s4/s5 state. 16. when the interface is in bus idle , the internal pull-down of 10 k ? is enabled. in normal transmission, a 400 ? pull-down takes effect, the signal will be override to logic 1 with pull-up resistor (37 ? ) to vcc 1.5 v. 17. this is a 350- ? normal pull-down, signal will be ove rridden to logic 1 with pull-up resistor (31 ? ) to vcc 1.05 v. 18. internal pull-down serves as rx terminat ion and is enabled after pltrst# deasserts. sata[3:2]gp/gpio[37:36] pull-down 20k 3 , 9 acpresent/gpio31 pull-down 20k 3 , 15 pcieclkrq5#/gpio44 pull-up 20k 1 , 12 sst (server/workstation only) pull-down 10k 16 pcieclkrq7#/gpio46 pull-up 20k 1 , 12 sata1gp/gpio19 pull-up 20k 3 , 9 susack# pull-up 20k 3 peci pull-down 350 17 table 3-1. integrated pull-up and pull-down resistors (sheet 2 of 2) signal resistor type nominal notes
datasheet 95 pch pin states 3.2 output and i/o signals planes and states ta b l e 3 . 2 and ta b l e 3 - 3 shows the power plane associated with the output and i/o signals, as well as the state at various times. within the table, the following terms are used: ?high-z? tri-state. pch not driving the signal high or low. ?high? pch is driving the signal to a logic 1. ?low? pch is driving the signal to a logic 0. ?defined? driven to a level that is defi ned by the function or external pull- up/pull-down resistor (will be high or low). ?undefined? pch is driving the sign al, but the value is indeterminate. ?running? clock is toggling or signal is transitioning because function not stopping. ?off? the power plane is off; pch is not driving when configured as an output or sampling when configured as an input. ?input? pch is sampling and signal st ate determined by external driver. note: signal levels are the same in s4 and s5, except as noted. pch suspend well signal states are indeterminate and undefined and may glitch prior to rsmrst# deassertion. this does not apply to slp_s3#, slp_s4#, slp_s5#, gpio24, and gpio29. these signals are determinate and defined prior to rsmrst# deassertion. pch core well signal states are indeterminate and undefined and may glitch prior to pwrok assertion. this does not apply to th rmtrip#. this signal is determinate and defined prior to pwrok assertion. dsw indicates pch deep s4/s5 well. this stat e provides a few wake events and critical context to allow system to draw minimal power in s4 or s5 states. asw indicates pch active sleep well. this power well contains functionality associated with active usage models while the host system is in sx. table 3-2. power plane and states for output and i/o signals for desktop configurations (sheet 1 of 6) signal name power plane during reset 1 immediately after reset 1 s0/s1 s3 s4/s5 pci express* petp[8:1], petn[8:1] core low low 4 defined off off dmi dmi[3:0]txp, dmi[3:0]txn core low low defined off off pci bus ad[31:0] core low low low off off c/be[3:0]# core low low low off off devsel# core high-z high-z high-z off off
pch pin states 96 datasheet frame# core high-z high-z high-z off off gnt0#, gnt[3:1]#7/ gpio[55, 53, 51] core high high high off off irdy#, trdy# core high-z high-z high-z off off par core low low low off off pcirst# suspend low high high low low perr# core high-z high-z high-z off off plock# core high-z high-z high-z off off stop# core high-z high-z high-z off off lpc/fwh interface lad[3:0] / fwh[3:0] core high high high off off lframe# / fwh[4] core high high high off off init3_3v# 7 core high high high off off sata interface sata[5:0]txp, sata[5:0]txn core high-z high-z defined off off sataled# core high-z high-z defined off off sataicompo core high high defined off off sclock/gpio22 core high-z (input) high-z (input) defined off off sload/gpio38 core high-z (input) high-z (input) defined off off sdataout[1:0]/ gpio[48,39] core high-z high-z high-z off off sata3rbias core te r m i n a t e d t o vss terminated to vss te r m i n a t e d to vss off off sata3icompo core high-z high-z high-z off off sata3rcompo core high-z high-z high-z off off interrupts pirq[a:d]# core high-z high-z high-z off off pirq[h:e]# / gpio[5:2] core high-z (input) high-z (input) defined off off serirq core high-z high-z high-z off off usb interface usb[13:0][p,n] suspend low low defined defined defined usbrbias suspend high-z high-z high high high table 3-2. power plane and states for output and i/o signals for desktop configurations (sheet 2 of 6) signal name power plane during reset 1 immediately after reset 1 s0/s1 s3 s4/s5
datasheet 97 pch pin states power management lan_phy_pwr_ctrl 10 / gpio12 suspend low low defined defined defined pltrst# suspend low high high low low slp_a# 5 suspend low high high defined defined slp_s3# suspend low high high low low slp_s4# suspend low high high high defined slp_s5#/gpio63 suspend low high high high defined 2 sus_stat#/gpio61 suspend low high high low low susclk/gpio62 suspend low running drampwrok suspend low high-z high-z high-z low pmsynch core low low defined off off stp_pci#/gpio34 core high-z (input) high-z (input) defined off off slp_lan#/gpio29 8 slp_lan# (using soft- strap) gpio29 (using soft- strap) suspend low high-z low 8 high-z high high-z defined high-z defined high-z processor interface procpwrgd processor low high high off off smbus interface smbclk, smbdata suspend high-z high-z defined defined defined system management interface sml0alert# / gpio60 suspend high-z high-z 11 defined defined defined sml0data suspend high-z high-z defined defined defined sml0clk suspend high-z high-z defined defined defined sml1clk/gpio58 suspend high-z high-z defined defined defined sml1alert#/pchhot#/ gpio74 suspend high-z high-z defined defined defined sml1data/gpio75 suspend high-z high-z defined defined defined miscellaneous signals spkr 7 core low low defined off off jtag_tdo suspend high-z high-z high-z high-z high-z gpio24 / proc_missing suspend low low defined defined defined table 3-2. power plane and states for output and i/o signals for desktop configurations (sheet 3 of 6) signal name power plane during reset 1 immediately after reset 1 s0/s1 s3 s4/s5
pch pin states 98 datasheet clocking signals clkout_itpxdp_p clkout_itpxdp_n core running running running off off clkout_dp_p clkout_dp_n core running running running off off clkout_dmi_p, clkout_dmi_n core running running running off off clkout_peg_a_p, clkout_peg_a_n core running running running off off clkout_peg_b_p, clkout_peg_b_n core running running running off off clkout_pcie[7:0]p, clkout_pcie[7:0]n core running running running off off clkout_pci[4:0] core running running running off off clkoutflex[3:0]/ gpio[67:64] core low running running off off xtal25_out core running running running off off xclk_rcomp core high-z high-z high-z off off intel ? high definition audio interface hda_rst# suspend low low 3 defined low low hda_sdo 7 suspend low low defined low low hda_sync 7 suspend low low defined low low hda_bclk 13 suspend low low low low low unmultiplexed gpio signals gpio8 7 suspend high high defined defined defined gpio15 7 suspend low low defined defined defined gpio27 7 (non-deep s4/ s5 mode) dsw high-z high-z high-z high-z high-z gpio27 7 (deep s4/s5 mode) dsw high-z high-z high-z high-z high-z gpio28 12 suspend high low low low low gpio32 core high high defined off off gpio57 suspend low high-z (input) defined defined defined gpio72 9 suspend high high defined defined defined multiplexed gpio signals used as gpio only gpio0 core high-z (input) high-z (input) defined off off gpio13 9 suspend high-z high-z high-z high-z high-z gpio30 9 suspend high-z (input) high-z (input) defined defined defined table 3-2. power plane and states for output and i/o signals for desktop configurations (sheet 4 of 6) signal name power plane during reset 1 immediately after reset 1 s0/s1 s3 s4/s5
datasheet 99 pch pin states gpio31 9 (non deep-s4/ s5 mode) dsw high-z (input) high-z (input) defined defined defined gpio31 9 (deep-s4/s5 mode) dsw high-z (input) high-z (input) defined defined defined gpio33 9 core high high high off off gpio35 / nmi# (nmi# is server/ workstation only) core low low defined off off spi interface spi_cs0# asw high 12 high defined defined defined spi_cs1# asw high 12 high defined defined defined spi_mosi asw low 12 low defined defined defined spi_clk asw low 12 low running defined defined controller link cl_clk1 6 suspend high/low 15 high/low 15 defined defined defined cl_data1 6 suspend high/low 15 high/low 15 defined defined defined cl_rst1# 6 suspend low high high high high thermal signals pwm[3:0] (server/workstation only) core low low defined off off sst (server/workstation only) suspend low low defined off off peci processor low low defined off off analog display / crt dac signals vga_red, vga_green, vga_blue core high-z high-z high-z off off dac_iref core high-z low low off off vga_hsync core low low low off off vga_vsync core low low low off off vga_ddc_clk core high-z high-z high-z off off vga_ddc_data core high-z high-z high-z off off vga_irtn core high-z high-z high-z off off intel ? flexible display interface fdi_fsync[1:0] core high-z high-z high-z off off fdi_lsync[1:0] core high-z high-z high-z off off fdi_int core high-z high-z high-z off off table 3-2. power plane and states for output and i/o signals for desktop configurations (sheet 5 of 6) signal name power plane during reset 1 immediately after reset 1 s0/s1 s3 s4/s5
pch pin states 100 datasheet notes: 1. the states of core and proc essor signals are evaluated at the times during pltrst# and immediately after pltrst#. the states of the controller li nk signals are taken at the times during cl_r st1# and immediately after cl_rst1#. the states of the suspend signals are evaluated at the times during rsmrst# and imme diately after rsmrst#, with an exception to gpio signals; refer to section 2.24 for more details on gpio state after reset. the states of the hda signals are evaluated at the times during hda_rst# and immediately after hda_rst#. 2. slp_s5# signal will be high in th e s4 state and low in the s5 state. 3. low until intel high definition audio controller reset bit set (d27:f0:offset hdbar+08h:bit 0), at which time hda_rst# will be high and hd a_bit_clk will be running. 4. petp/n[8:1] low until port is enabled by software. 5. the slp_a# state will be de termined by intel me policies. 6. the state of signals in s3-5 will be defined by intel me policies. 7. this signal is sampled as a functional strap during reset. refer to functional straps definition table for usage. 8. slp_lan# behavior after rese t is dependent on value of sl p_lan# default value bit. a soft-strap is used to select between slp_la n# and gpio usage. when strap is set to 0 (default), pin is used as slp_lan#; when soft -strap is set to 1, pin is used as gpio29. 9. native functionality multiplexed with these gpios are not used in desktop configurations. 10. native/gpio functionality controlled using soft straps. default to native functionality until soft straps are loaded. 11. state of the pins depend on the source of vccasw power. 12. pin is tri-stated prior to apwrok assertion during reset. 13. when controller reset bit of global control register (d27:f0 offset hdbar 08h bit 0) gets set, this pin wi ll start toggling. 14. not all signals or pin f unctionalities may be availa ble on a given sku. see section 1.3 and chapter 2 for details. 15. controller link clock and data buffers use in ternal pull-up and pull-down resistors to drive a logical 1 or a 0. digital display interface ddp[d:b]_[3:0]p, ddp[d:b]_[3:0]n core low low defined off off ddp[d:b]_auxp, ddp[d:b]_auxn core low low defined off off sdvo_ctrlclk core high-z high-z defined off off sdvo_ctrldata core low high-z defined off off ddpc_ctrlclk, ddpd_ctrlclk core high-z high-z defined off off ddpc_ctrldata ddpd_ctrldata core low high-z defined off off table 3-2. power plane and states for output and i/o signals for desktop configurations (sheet 6 of 6) signal name power plane during reset 1 immediately after reset 1 s0/s1 s3 s4/s5
datasheet 101 pch pin states table 3-3. power plane and states for output and i/o signals for mobile configurations (sheet 1 of 6) signal name power plane during reset 1 immediately after reset 1 c-x states s0/s1 s3 s4/s5 pci express* pet[8:1]p, pet[8:1]n core low low 4 defined defined off off dmi dmi[3:0]txp, dmi[3:0]txn core low low defined defined off off lpc/fwh interface lad[3:0] / fwh[3:0] core high high high high off off lframe# / fwh[4] core high high high high off off init3_3v# 7 core high high high high off off sata interface sata[5:0]txp, sata[5:0]txn core high-z high-z defined defined off off sataled# core high-z high-z defined defined off off sataicompo core high-z high-z defined defined off off sclock/gpio22 core high-z (input) high-z (input) defined defined off off sload/gpio38 core high-z (input) high-z (input) defined defined off off sdataout[1:0]/ gpio[48,39] core high-z (input) high-z (input) defined defined off off sata3rbias core te r m i n a t e d to vss te r m i n a t e d t o vss te r m i n a t e d to vss te r m i n a t e d to vss off off sata3icompo core high-z high-z high-z high-z off off sata3rcompo core high-z high-z high-z high-z off off interrupts pirq[a:d]# core high-z high-z defined defined off off pirq[h:e]# / gpio[5:2] core high-z (input) high-z (input) defined defined off off serirq core high-z high-z running high-z off off usb interface usb[13:0][p,n] suspend low low defined defined defined defined usbrbias suspend high-z high-z defined defined defined defined
pch pin states 102 datasheet power management clkrun# 19 core low low defined defined off off pltrst# suspend low high high high low low slp_a# 5 suspend low high high high defined defined slp_s3# suspend low high high high low low slp_s4# suspend low high high high high defined slp_s5#/gpio63 suspend low high high high high defined 2 sus_stat#/gpio61 suspend low high high high low low susclk/gpio62 suspend low running suswarn#/ suspwrdnack/ gpio30 (note 20) suspend 0 1 defined defined defined defined suswarn#/ suspwrdnack/ gpio30 (note 21) suspend 0 1 1 1 1 1 drampwrok suspend low high-z high-z high-z high-z low lan_phy_pwr_ctrl 9 /gpio12 suspend low low defined defined defined defined pmsynch core low low defined/ low 10 defined off off stp_pci#/gpio34 core high-z (input) high-z (input) defined defined off off slp_lan# 14 /gpio29 slp_lan# (using soft-strap) gpio29 (using soft- strap) suspend low low low 14 high-z high high-z high high-z defined high-z defined high-z processor interface procpwrgd processor low high high high off off smbus interface smbclk, smbdata suspend high-z high -z defined defined defined defined table 3-3. power plane and states for output and i/o signals for mobile configurations (sheet 2 of 6) signal name power plane during reset 1 immediately after reset 1 c-x states s0/s1 s3 s4/s5
datasheet 103 pch pin states system management interface sml0alert#/ gpio60 suspend high-z high-z defined defined defined defined sml0data suspend high-z high-z defined defined defined defined sml0clk suspend high-z high-z defined defined defined defined sml1clk/gpio58 suspend high-z high-z defined defined defined defined sml1alert#/ pchhot#/gpio74 suspend high-z high-z defined defined defined defined sml1data/gpio75 suspend high-z high-z defined defined defined defined miscellaneous signals spkr 7 core low low defined defined off off jtag_tdo suspend high-z high-z high-z high-z high-z high-z clocking signals clkout_itpxdp_p, clkout_itpxdp_n core running running running running off off clkout_dp_p, clkout_dp_n core running running running running off off clkout_dmi_p, clkout_dmi_n core running running running running off off xtal25_out core high-z high-z high-z high-z off off xclk_rcomp core high-z high-z high-z high-z off off clkout_peg_a_p, clkout_peg_a_n core running running running running off off clkout_peg_b_p, clkout_peg_b_n core running running running running off off clkout_pcie[7:0] p, clkout_pcie[7:0] n core running running running running off off clkout_pci[4:0] core running running running running off off clkoutflex[3:0]/ gpio[67:64] core low running running/ low running off off intel ? high definition audio interface hda_rst# suspend low low 3 defined defined low low hda_sdo 7 suspend low low low low low low hda_sync 7 suspend low low low low low low hda_bclk 22 suspend low low low low low low hda_dock_en#/ gpio33 core high high 11 high 11 high 11 off off hda_dock_rst#/ gpio13 suspend high-z high-z high-z high-z high-z high-z table 3-3. power plane and states for output and i/o signals for mobile configurations (sheet 3 of 6) signal name power plane during reset 1 immediately after reset 1 c-x states s0/s1 s3 s4/s5
pch pin states 104 datasheet unmultiplexed gpio signals gpio8 7 suspend high high defined defined defined defined gpio15 7 suspend low low defined defined defined defined gpio24 suspend low low defined defined defined defined gpio27 7 (non-deep s4/s5 mode) dsw high-z high-z high-z high-z high-z high-z gpio27 7 (deep s4/s5 mode) dsw high-z high-z high-z high-z high-z high-z gpio28 suspend high low low low low low gpio57 suspend low high-z (input) defined defined defined defined multiplexed gpio signals used as gpio only gpio0 core high-z (input) high-z (input) defined defined off off gpio[17,7,6,1] 8 core high-z high-z high-z high-z off off gpio35 core low low defined defined off off gpio50 core high-z high-z high-z high-z off off gpio[55,53,51] core high high high high off off gpio52 core high-z high-z high-z high-z off off gpio54 core high-z high-z high-z high-z off off gpio[71:68] core high-z hi gh-z high-z high-z off off spi interface spi_cs0# asw high 18 high defined defined defined defined spi_cs1# asw high 18 high defined defined defined defined spi_mosi asw low 18 low defined defined defined defined spi_clk asw low 18 low running running defined defined controller link cl_clk1 6 suspend high/low 13 high/low 13 defined defined defined defined cl_data1 6 suspend high/low 13 high/low 13 defined defined defined defined cl_rst1# 6 suspend low high defined high high high table 3-3. power plane and states for output and i/o signals for mobile configurations (sheet 4 of 6) signal name power plane during reset 1 immediately after reset 1 c-x states s0/s1 s3 s4/s5
datasheet 105 pch pin states lvds signals lvdsa_data[3:0], lvdsa_data#[3:0] core high-z high-z defined/ high-z 12 defined/ high-z 12 off off lvdsa_clk, lvdsa_clk# core high-z high-z defined/ high-z 12 defined/ high-z 12 off off lvdsb_data[3:0], lvdsb_data#[3:0] core high-z high-z defined/ high-z 12 defined/ high-z 12 off off lvdsb_clk, lvdsb_clk# core high-z high-z defined/ high-z 12 defined/ high-z 12 off off l_ddc_clk core high-z high-z high-z high-z off off l_ddc_data core low high-z high-z high-z off off l_vdd_en core low low low/ high-z 12 low/ high-z 12 off off l_bklten core low low low/ high-z 12 low/ high-z 12 off off l_bkltctl core low low low/ high-z 12 low/ high-z 12 off off l_ctrl_clk core high-z high-z high-z high-z off off l_ctrl_data core high-z high-z high-z high-z off off lvd_vbg, lvd_vrefh, lvd_vrefl core high-z high-z high-z high-z off off analog display / crt dac signals crt_red, crt_green, crt_blue core high-z high-z defined defined off off dac_iref core high-z low low low off off crt_hsync core low low low low off off crt_vsync core low low low low off off crt_ddc_clk core high-z high-z high-z high-z off off crt_ddc_data core high-z high-z high-z high-z off off crt_irtn core high-z high-z high-z high-z off off intel ? flexible display interface fdi_fsync[1:0] core high-z high-z defined defined off off fdi_lsync[1:0] core high-z hi gh-z defined defined off off fdi_int core high-z high-z defined defined off off table 3-3. power plane and states for output and i/o signals for mobile configurations (sheet 5 of 6) signal name power plane during reset 1 immediately after reset 1 c-x states s0/s1 s3 s4/s5
pch pin states 106 datasheet notes: 1. the states of core and proc essor signals are evaluated at the times during pltrst# and immediately after pltrst#. the states of the controller li nk signals are taken at the times during cl_rst1# and immediately after cl_rst1#. the states of the suspend signals are evaluated at the times during rsmrst# and imme diately after rsmrst#, with an exception to gpio signals; refer to section 2.24 for more details on gpio state after reset. the states of the hda signals are evaluated at the times during hda_rst# and immediately after hda_rst#. 2. slp_s5# signal will be high in th e s4 state and low in the s5 state. 3. low until intel ? high definition audio controll er reset bit set (d27:f0:offset hdbar+08h:bit 0), at which time hda_rst# will be high and hd a_bit_clk will be running. 4. petp/n[8:1] low until port is enabled by software. 5. the slp_a# state will be de termined by intel me policies. 6. the state of signals in s3-5 will be defined by intel me policies. 7. this signal is sampled as a functional strap during reset. refer to functional straps definition table for usage. 8. native functionality multiplexed with these gp ios is not utilized in mobile configurations. 9. native/gpio functionality controlled using soft straps. default to native functionality until soft straps are loaded. 10. this pin will be driven to a high when dock attach bit is set (docking control register d27:f0 offset 4ch) 11. this pin will be driven to a low when dock attach bit is set (doc king control register d27:f0 offset 4ch) 12. pch tri-states these signals when lvds port is disabled. 13. controller link clock and data buffers use in ternal pull-up and pull-down resistors to drive a logical 1 or a 0. 14. slp_lan# behavior after rese t is dependent on value of sl p_lan# default value bit. a soft-strap is used to select between slp_la n# and gpio usage. when strap is set to 0 (default), pin is used as slp_lan#, when soft -strap is set to 1, pin is used as gpio29. 15. state of the pins depend on the source of vccasw power. 16. pin state reflected when spi2 enable rtc powe r backed soft strap is enabled, for mobile configurations using a finger-print sensor devi ce. when soft strap is not enabled, signal defaults to gp input. 17. based on intel me wake events and intel me state. suspwrdnack is the default mode of operation. if system support s deep s4/s5, subsequent b oots will defaul t to suswarn# 18. pins are tri-stated prior to apwrok assertion during reset. 19. clkrun# is driven to a logic 1 during reset for mobile configurations (default is native function) to ensure that pc i clocks can toggle before devices come out of reset. digital display interface ddp[d:b]_[3:0]p, ddp[d:b]_[3:0]n, core low low defined defined off off ddp[d:b]_auxp, ddp[d:b]_auxn core low low defined defined off off sdvo_ctrlclk core high-z high-z defined defined off off sdvo_ctrldata core low high-z defined defined off off ddpc_ctrlclk, ddpd_ctrlclk core high-z high-z defined defined off off ddpc_ctrldata, ddpd_ctrldata core low high-z defined defined off off table 3-3. power plane and states for output and i/o signals for mobile configurations (sheet 6 of 6) signal name power plane during reset 1 immediately after reset 1 c-x states s0/s1 s3 s4/s5
datasheet 107 pch pin states 20. pin-state indicates suspwrdnack in non- deep s4/s5, deep s4/s5 after rtc power failure. 21. pin-state indicates suswarn# in deep s4/s5 supported platforms. 22. when controller reset bit of global control register (d27:f0 offset hdbar 08h bit 0) gets set, this pin will start toggling. 23. not all signals or pin functionalitie s may be available on a given sku. see section 1.3 and chapter 2 for details. 3.3 power planes for input signals ta b l e 3 - 4 and ta b l e 3 - 5 shows the power plane associated with each input signal, as well as what device drives the signal at various times. valid states include: high low static: will be high or low, but will not change driven: will be high or low, and is allowed to change running: for input clocks pch suspend well signal states are indeterminate and undefined and may glitch prior to rsmrst# deassertion. this does not apply to slp_s3#, slp_s4#, and slp_s5#. these signals are determinate and defined prior to rsmrst# deassertion. pch core well signal states are indeterminate and undefined and may glitch prior to pwrok assertion. this does not apply to th rmtrip#. this signal is determinate and defined prior to pwrok assertion. dsw indicates pch deep s4/s5 well. this stat e provides a few wake events and critical context to allow system to draw minimal power in s4 or s5 states. asw indicates pch active sleep well. this power well contains functionality associated with active usage models while the host system is in sx. table 3-4. power plane for input signals for desktop configurations (sheet 1 of 3) signal name power well driver during reset s0/s1 s3 s4/s5 dmi dmi[3:0]rxp, dmi[3:0]rxn core processor driven off off pci express* per[8:1]p, pern[8:1]n core pci express device driven off off pci bus req0#, req1# / gpio50 1 req2# / gpio52 1 req3# / gpio54 1 core external pull-up driven off off pme# suspend internal pull-up driven driven driven serr# core pci bus peripherals driven off off lpc interface ldrq0# core lpc devices driven off off ldrq1# / gpio23 1 core lpc devices driven off off
pch pin states 108 datasheet sata interface sata[5:0]rxp, sata[5:0]rxn core sata drive driven off off sataicompi core high-z driven off off sata4gp/gpio16 1 core external device or external pull-up/pull-down driven off off sata5gp/gpio49 1 / temp_alert# core external device or external pull-up/pull-down driven off off sata0gp / gpio[21] 1 core external device or external pull-up/pull-down driven off off sata1gp/gpio19 core internal pull-up driven off off sata[3:2]gp/ gpio[37:36] core internal pull-down driven off off sata3compi core external pull-up driven off off usb interface oc[7:0]#/ gpio[14,10,9,43:40,59] 1 suspend external pull-ups driven driven driven usbrbias# suspend external pull-down driven driven driven power management apwrok suspend external circuit high driven driven pwrbtn# dsw internal pull-up driven driven driven pwrok rtc external circuit driven driven driven dpwrok rtc external circuit driven driven driven ri# suspend serial port buffer driven driven driven rsmrst# rtc external rc circuit high high high sys_reset# core external circuit driven off off sys_pwrok suspend external circuit high driven driven thrmtrip# core (processor) external thermal sensor driven off off wake# suspend external pull-up driven driven driven processor interface a20gate core external micro controller static off off rcin# core external micro controller high off off system management interface smbalert# / gpio11 suspend external pull-up driven driven driven intruder# rtc external switch driven driven driven jtag interface jtag_tdi 3 suspend internal pull-up high high high jtag_tms 3 suspend internal pull-up high high high jtag_tck 3 suspend internal pull-down low low low table 3-4. power plane for input signals fo r desktop configurations (sheet 2 of 3) signal name power well driver during reset s0/s1 s3 s4/s5
datasheet 109 pch pin states note: 1. these signals can be configured as outputs in gpio mode. 2. this signal is sampled as a functional strap during reset. refer to functional straps definition table for usage. 3. external termination is also required for jtag enabling. 4. not all signals or pin fu nctionalities may be availa ble on a given sku. see section 1.3 and chapter 2 for details. miscellaneous signals intvrmen 2 rtc external pull-up high high high rtcrst# rtc external rc circuit high high high srtcrst# rtc external rc circuit high high high digital display interface ddp[b:c:d]_hpd core external pull-down driven off off sdvo_intp, sdvo_intn core sdvo controller device driven off off sdvo_tvclkinp, sdvo_tvclkinn core sdvo controller device driven off off sdvo_stallp, sdvo_stalln core sdvo controller device driven off off intel ? flexible display interface fdi_rxp[7:0], fdi_rxn[7:0] core processor driven off off clock interface clkin_sata_n, clkin_sata_p core external pull-down low off off clkin_dot_96p, clkin_dot_96n core external pull-down low off off clkin_dmi_p, clkin_dmi_n core external pull-down low off off clkin_pciloopback core clock generator running off off pcieclkrq[7:5]#/ gpio[46:44] 1 suspend external pull-up driven driven driven pcieclkrq2#/gpio20 1 / smi# (smi# is server/ workstation only) core external pull-up driven off off refclk14in core external pull-down low off off xtal25_in core clock generator high-z high-z high-z intel ? high definition audio interface spi interface spi_miso asw internal pull-up driven driven driven thermal (server/workstation only) tach[7:0]/ gpio[71:68,7,6,1,17] 1 core internal pull-up driven off off table 3-4. power plane for input signals for desktop configurations (sheet 3 of 3) signal name power well driver during reset s0/s1 s3 s4/s5
pch pin states 110 datasheet table 3-5. power plane for input signals fo r mobile configurations (sheet 1 of 3) signal name power well driver during reset c-x states s0/s1 s3 s4/s5 dmi dmi[3:0]rxp, dmi[3:0]rxn core processor driven driven off off pci express* per[8:1]p, per[8:1]n core pci express* device driven driven off off lpc interface ldrq0# core internal pull-up driven high off off ldrq1# / gpio23 1 core internal pull-up driven high off off sata interface sata[5:0]rxp, sata[5:0]rxn core sata drive driven driven off off sataicompi core high-z high-z defined off off sata4gp/gpio16 1 core external device or external pull-up/pull-down driven driven off off sata5gp/gpio49 1 / temp_alert# core external device or external pull-up/pull-down driven driven off off sata[0]gp / gpio[21] 1 core external device or external pull-up/pull-down driven driven off off sata1gp/gpio19 core internal pull-up driven driven off off sata[3:2]gp/ gpio[37:36] core internal pull-down driven driven off off sata3compi core external pull-up driven driven off off usb interface oc[7:0]#/ gpio[14,10,9,43:40, 59] suspend external pull-ups driven driven driven driven usbrbias# suspend external pull-down driven driven driven driven power management acpresent (mobile only) /gpio31 1 (non- deep s4/s5 mode) dsw external microcontroller driven driven driven driven acpresent (mobile only) /gpio31 1 (deep s4/s5 mode) dsw external microcontroller driven driven driven driven batlow# (mobile only) /gpio72 1 suspend external pull-up high high driven driven apwrok suspend external circuit driven driven driven driven pwrbtn# dsw internal pull-up driven driven driven driven pwrok rtc external circuit driven driven off off
datasheet 111 pch pin states ri# suspend serial port buffer driven driven driven driven rsmrst# rtc external rc circuit high high high high sys_reset# core external circuit driven driven off off thrmtrip# core (processor) thermal sensor driven driven off off wake# suspend external pull-u p driven driven driven driven processor interface a20gate core external microcontroller static static off off rcin# core external microcontroller high high off off system management interface smbalert# / gpio11 suspend external pull-up driven driven driven driven intruder# rtc external switch driven driven high high jtag interface jtag_tdi suspend internal pull-up 4 high high high high jtag_tms suspend internal pull-up 4 high high high high jtag_tck suspend internal pull-down4 low low low low miscellaneous signals intvrmen 2 rtc external pull-up or pull- down high high high high rtcrst# rtc external rc circuit high high high high srtcrst# rtc external rc circuit high high high high intel ? high definition audio interface hda_sdin[3 :0] suspend intel ? high definition audio codec driven low low low spi interface spi_miso asw internal pull-up driven driven driven driven table 3-5. power plane for input signals fo r mobile configuratio ns (sheet 2 of 3) signal name power well driver during reset c-x states s0/s1 s3 s4/s5
pch pin states 112 datasheet notes: 1. these signals can be configured as outputs in gpio mode. 2. this signal is sampled as a functional strap during reset. refer to functional straps definition table for usage. 3. external termination is re quired for jtag enabling. 4. not all signals or pin f unctionalities may be availa ble on a given sku. see section 1.3 and chapter 2 for details. clock interface clkin_dmi_p, clkin_dmi_n core external pull-down low low off off clkin_sata_n/ clkin_sata_p/ core external pull-down low low off off clkin_dot_96p, clkin_dot_96n core external pull-down low low off off clkin_pciloopback core clock generator running running off off pcieclkrq[7:3]#/ gpio[46:44,26:25] 1 , pcieclkrq0#/ gpio73 1 suspend external pull-up driven driven driven driven pcieclkrq[2:1]#/ gpio[20:18] 1 core external pull-up driven driven off off peg_a_clkrq#/ gpio47 1 , peg_b_clkrq#/ gpio56 1 suspend external pull-up driven driven driven driven xtal25_in core clock generator high-z high-z off off refclk14in core external pull-down low low off off clkin_pciloopback core clock generator high-z high-z off off intel ? flexible display interface fdi_rxp[7:0], fdi_rxn[7:0] core processor driven driven off off digital display interface ddp[b:c:d]_hpd core external pull-down driven driven off off sdvo_intp, sdvo_intn core sdvo controller device driven driven off off sdvo_tvclkinp, sdvo_tvclkinn core sdvo controller device driven driven off off sdvo_stallp, sdvo_stalln core sdvo controller device driven driven off off table 3-5. power plane for input signals fo r mobile configurations (sheet 3 of 3) signal name power well driver during reset c-x states s0/s1 s3 s4/s5
datasheet 113 pch and system clocks 4 pch and system clocks pch provides a complete system clocking solution through integrated clocking. pch based platforms require several single-end ed and differential clocks to synchronize signal operation and data propagation system-wide between interfaces, and across clock domains. in integrated clock mode, all the system clocks will be provided by pch from a 25 mhz crystal generated clock input. the output signals from pch are: ? one 100 mhz differential source for bclk and dmi (pci express 2.0 jitter tolerant) ? one 120 mhz differential source for embedded displayport (mobile only) on integrated graphics processors. ? ten 100 mhz differential sources for pci express 2.0 ? one 100 mhz differential clock for xdp/itp ? five 33 mhz single-ended source for pci/ot her devices (one of these is reserved as loopback clock) ? four flexible single-ended outputs that can be used for 14.31818/24/27/33/48 mhz for legacy platform functions, discrete gr aphics devices, external usb controllers, etc. 4.1 platform clocking requirements providing a platform-level clocking solu tion uses multiple system components including: ?the pch ? 25 mhz crystal source ta b l e 4 - 1 shows the system clock input to pch. ta b l e 4 - 2 shows system clock outputs generated by pch. notes: 1. clkin_gnd0_[p:n] (desktop pins only) is no t used and requires ex ternal termination on desktop platforms. 2. clkin_gnd1_[p:n] is not used and requires external termination on mobile and desktop platforms. table 4-1. pch clock inputs clock domain frequency usage description clkin_dmi_p, clkin_dmi_n 100 mhz unused. external termination required. clkin_dot96_p, clkin_dot96_n 96 mhz unused. external termination required. clkin_sata_p/ clkin_sata_n 100 mhz unused. external termination required. clkin_pciloopb ack 33 mhz 33 mhz clock feedback input to reduce skew between pch pci clock and clock observed by connected pci devices. this signal must be connected to one of the pins in the group clkout_pci[4:0] refclk14in 14.31818 mhz unused. external termination required. xtal25_in 25 mhz crystal input source used by pch.
pch and system clocks 114 datasheet figure 4-1 shows the high level block diagram of pch clocking. table 4-2. clock outputs clock domain frequency spread spectrum usage clkout_pci[4:0] 33 mhz yes single ended 33 mhz outputs to pci connectors/ devices. one of these signals must be connected to clkin_pciloopback to function as a pci clock loopback. this allows skew control for variable lengths of clkout_pci[4:0] . note: not all skus may support pci devices. see section 1.3 for details. clkout_dmi_p, clkout_dmi_n 100 mhz yes 100 mhz pcie* gen2.0 differential output to the processor for dmi/bclk. clkout_pcie[7:0]_p, clkout_pcie[7:0]_n 100 mhz yes 100 mhz pcie gen2.0 sp ecification differential output to pci express devices. clkout_peg_a_p, clkout_peg_a_n, clkout_peg_b_p, clkout_peg_b_n, 100 mhz yes 100 mhz pcie gen2 specification differential output to pci express graphics devices. clkout_itpxdp_p, clkout_itpxdp_n 100 mhz yes used as 100 mhz clock to processor xdp/itp on the platform. clkout_dp_p, clkout_dp_n 120 mhz yes 120 mhz differential outp ut to processor for embedded displayport clkoutflex0/ gpio64 33 mhz / 14.31818 mhz / 27 mhz (ssc/ non-ssc) /48 mhz / 24mhz no 33 mhz, 48/24 mhz or 14.31818 mhz outputs for various platform device s such as pci/lpc or sio/ec devices, 27 mhz (ssc/non-ssc) clock for discrete graphics devices. clkoutflex1/ gpio65, clkoutflex3/ gpio67 14.31818 mhz / 27 mhz (ssc/ non-ssc) / 48 mhz / 24 mhz no 48/24 mhz or 14.31818 mhz outputs for various platform devices such as pci/lpc or sio/ec devices, 27 mhz (ssc/non-ssc) clock for discrete graphics devices. clkoutflex2/ gpio64 33 mhz / 25 mhz / 14.31818 mhz / 27mhz (ssc/ non-ssc) / 48 mhz / 24 mhz no 33 mhz, 25mhz, 48/24 mhz or 14.31818 mhz outputs for various platform devices such as pci/ lpc or sio/ec devices, 27 mhz (ssc/non-ssc) clock for discrete graphics devices. spi_clk 17.86 mhz/ 31.25 mhz no drive spi devices connected to the pch. generated by the pch.
datasheet 115 pch and system clocks figure 4-1. pch high-level clock diagram pch processor display 120m usb 2.0/1.0 sata 100 m legacy 14 m pcie graphics pci/lpc/33m endpoint pcie * endpoint sio, tpm, etc. dmi/fdi pcie* pcie* 100 m gen 2 loopback 33 m 5x 8x 4x 2x 25 m xtal dmi 100 m dp 120 m 33 m pcie * 100 m gen2 flex 14.318/33/27/48/24m rtc xtal rtc 32.768 m spi (var) int osc intel me xdp/itp connector 1x 1x 100 m dmi/ intel fdi pcie 2.0 pll & ssc block
pch and system clocks 116 datasheet 4.2 functional blocks the pch has up to 8 plls, 4 spread modulators, and a numbers of dividers to provide great flexibility in clock source selection, configuration, and better power management. ta b l e 4 - 3 describes the plls on the pch and the clock domains that are driven from the plls. notes: 1. indicates the source clock frequencies driven to othe r internal logic for delive ring functionality needed. does not indicate external outputs 2. powered in sub-s0 states by a suspend well ring oscillator. ta b l e 4 - 4 provides a basic description of the spread modulators. the spread modulators each operate on the xck pll?s 2.4 ghz outputs. spread spectrum tuning and adjustment can be made on the fly without a platform reboot using specific programming sequence to the clock registers. table 4-3. pch plls pll outputs 1 description/usage xck_pll eight 2.4 ghz 45 phase shifted. outputs are routed to each of the spread modulator blocks before hitting the various dividers and the other plls to provide appropriate clocks to all of the i/o interface logic. main reference pll. always enabled in in tegrated clocking mode. resides in core power well and is not powered in s3 and below states. dmi_pll 2.5 ghz/625 mhz/250 mhz dmi gen2 clocks source clock is 100 mhz from xck_pll (post-dividers). it is the primary pll resource to gene rate the dmi port clocks. resides in core power well and is not powered in s3 and below states. fdi_pll 2.7 ghz/270 mhz/450 mhz fdi logic and link clocks source clock is 100 mhz fro m xck_pll (pos t-dividers). resides in the core power well and is not powered in s3 and below states. pciepxp_pll 2.5 ghz/625 mhz/ 500 mhz/250 mhz/125 mhz clocks for pci express* 2.0 interface. source clock is from xck_pll. pciepxp_pll drives clocks to pcie ports and intel ? me engine 2 (in s0 state). can be optionally used to supply dmi clocks. resides in the core power well and is not powered in s3 and below states. sata_pll 3.0 ghz/1.5 ghz/300 mhz/ 150 mhz clocks for sata logic (serial clock, tx/rx clocks) source clock is 100 mhz fro m xck_pll (post-divider). this pll generates all the requir ed sata gen2 and sata gen3 clocks. resides in core power well and is not powered in s3 and below states. usb_pll 24-/48-/240-/480 mhz clocks for legacy usb 2.0/usb 1.0 logic source clock is from xck_pll (post-divider). resides in core power well and is not powered in s3 and below states. dpll_a/b runs with a wide variety of frequency and di vider options. source clock is 120 mhz fro m xck_pll (post-divider). provides reference clocks requ ired for integrated graphics display. resides in core power well and is not powered in s3 and below states.
datasheet 117 pch and system clocks 4.3 clock configuration access overview the pch provides increased flexibility of host equivalent configurability of clocks, using intel me fw. in the intel me fw assisted configuration mode, control settings for plls, spread modulators and other clock configuration registers will be handled by the intel me engine. the parameters to be loaded will reside in the inte l me data regi on of the spi flash device. bios would only have access to the register set through a set of intel mei commands to the intel me. 4.4 straps related to clock configuration there are no functional (pin) straps required for clock configuration. the following soft-straps are implemented on pch for clock configuration: integrated clocking profile select: 3 profile select bits allow up to 8 different clock profiles to be specified in the spi flash device. in addition, 3 rtc well backed host register bits are also defined for integrated clocking profile selection through bios. table 4-4. ssc blocks modulator description ssc1 used for 120 mhz fixed frequency spre ad spectrum clock. supports up to 0.5% spread ssc2 used for 100 mhz spread spectrum clock. supports up to 0.5% spread. ssc3 used for 100 mhz fixed frequency ss c clock. supports up to 0.5% spread. ssc4 used for 120 mhz fixed-frequency super- spread clocks. supports 0.5% spread for the 100 mhz and up to 2.5% super-sp read for the 120 mhz display clock for integrated graphics.
pch and system clocks 118 datasheet
datasheet 119 functional description 5 functional description this chapter describes the functi ons and interfaces of the pch. 5.1 dmi-to-pci bridge (d30:f0) the dmi-to-pci bridge resides in pci device 30, function 0 on bus 0. this portion of the pch implements the buffering and cont rol logic between pci and direct media interface (dmi). the arbitration for the pci bus is handled by this pci device. the pci decoder in this device must decode the rang es for the dmi. all register contents are lost when core well power is removed. direct media interface (dmi) is the chip-to-chip connection between the processor and the pch. this high-speed interface integr ates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. base functionality is completely software transpar ent permitting current and legacy software to operate normally. to provide for true isochronous transfers and configurable quality of service (qos) transactions, the pch supports two virtual channels on dmi?vc0 and vc1. these two channels provide a fixed arbitration scheme where vc1 is always the highest priority. vc0 is the default conduit of traffic for dmi and is always enabled. vc1 must be specifically enabled and configured at both ends of the dmi link (that is, the pch and processor). configuration registers for dmi, virtual ch annel support, and dmi active state power management (aspm) are in the rcrb sp ace in the chipset config registers ( chapter 10 ). dmi is also capable of operating in an enterprise southbridge interface (esi) compatible mode. esi is a chip-to-chip conne ction for server/workstation chipsets. in this esi-compatible mode, the dmi signals require ac coupling. a hardware strap is used to configure dmi in esi-compatible mode see section 2.27 for details. 5.1.1 pci bus interface the pch pci interface supports pci local bus specification, revision 2.3 , at 33 mhz. the pch integrates a pci arbiter that supports up to four external pci bus masters in addition to the internal pch requests. note: pci bus interface is not available on any mob ile pch skus. pci bus interface is also not available on certain desktop pch skus. see section 5.1.9 for alternative methods for supporting pci devices.
functional description 120 datasheet 5.1.2 pci bridge as an initiator the bridge initiates cycles on the pci bus wh en granted by the pci arbiter. the bridge generates the following cycle types: 5.1.2.1 memory reads and writes the bridge bursts memory writes on pci that are received as a single packet from dmi. 5.1.2.2 i/o reads and writes the bridge generates single dw i/o read and write cycles. when the cycle completes on the pci bus, the bridge generates a corresponding completion on dmi. if the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle. 5.1.2.3 configuration reads and writes the bridge generates single dw configuration read and write cycles. when the cycle completes on the pci bus, the bridge genera tes a corresponding completion on dmi. if the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle. 5.1.2.4 locked cycles the bridge propagates locks from dmi per the pci local bus specification . the pci bridge implements bus lock, which means the arbiter will not grant to any agent except dmi while locked. if a locked read results in a target or mast er abort, the lock is not established (as per the pci local bus specification ). agents north of the pch must not forward a subsequent locked read to the bridge if th ey see the first one finish with a failed completion. 5.1.2.5 target / master aborts when a cycle initiated by the bridge is ma ster/target aborted, the bridge will not re- attempt the same cycle. for multiple dw cycles, the bridge increments the address and attempts the next dw of the transaction. for all non-postable cycles, a target abort response packet is returned for each dw that was master or target aborted on pci. the bridge drops posted writes that abort. 5.1.2.6 secondary master latency timer the bridge implements a master latency timer using the smlt register which, upon expiration, causes the deassertion of frame# at the next legal clock edge when there is another active request to use the pci bus. table 5-1. pci bridge initiator cycle types command c/be# notes i/o read/write 2h/3h non-posted memory read/write 6h /7h writes are posted configuration read/write ah/bh non-posted special cycles 1h posted
datasheet 121 functional description 5.1.2.7 dual address cycle (dac) the bridge will issue full 64-bit dual ad dress cycles for device memory-mapped registers above 4 gb. 5.1.2.8 memory and i/o decode to pci the pci bridge in the pch is a subtractive decode agent that follows the following rules when forwarding a cycle from dmi to the pci interface: ? the pci bridge will positively decode any memory/io address within its window registers, assuming pcicmd.mse (d30:f0:offset 04h:bit 1) is set for memory windows and pcicmd.iose (d30:f0:offset 04h:bit 0) is set for i/o windows. ? the pci bridge will subtractively decode any 64-bit memo ry address not claimed by another agent, assuming pcicmd.mse (d30:f0:offset 04h:bit 1) is set. ? the pci bridge will subtractively decode any 16-bit i/o address not claimed by another agent assuming pcicmd.iose (d30:f0:offset 04h:bit 0) is set. ? if bctrl.ie (d30:f0:offset 3eh:bit 2) is set, the pci bridge will not positively forward from primary to secondary calle d out ranges in the i/o window per pci local bus specification (i/o transactions addressing the last 768 bytes in each, 1 kb block: offsets 100h to 3ffh). the pc i bridge will still take them subtractively assuming the above rules. ? if bctrl.vgae (d30:f0:offset 3eh:bit 3) is set, the pci bridge will positively forward from primary to secondary i/o and memory ranges as called out in the pci bridge specification , assuming the above rules are met. 5.1.3 parity error detection and generation pci parity errors can be detected and repo rted. the following behavioral rules apply: ? when a parity error is detected on pci, the bridge sets the secsts.dpe (d30:f0:offset 1eh:bit 15). ? if the bridge is a master and bctrl.pere (d30:f0:offset 3eh:bit 0) is set and one of the parity errors defined below is detected on pci, then the bridge will set secsts.dpd (d30:f0:offset 1eh:bit 8) and will also generate an internal serr#. ? during a write cycle, the perr# signal is active, or ? a data parity error is detected while performing a read cycle ? if an address or command parity error is detected on pci and pcicmd.see (d30:f0:offset 04h:bit 8), bctrl.pere, and bctrl.see (d30:f0:offset 3eh:bit 1) are all set, the bridge will set psts.sse (d30:f0:offset 06h:bit 14) and generate an internal serr#. ? if the psts.sse is set because of an ad dress parity error and the pcicmd.see is set, the bridge will generate an internal serr#. ? when bad parity is detected from dmi, bad parity will be driven on all data from the bridge. ? when an address parity error is detected on pci, the pci bridge will never claim the cycle. this is a slight deviation from the pci bridge specification that says that a cycle should be claimed if bctrl.pere is not set. howe ver, dmi does not have a concept of address parity error, so claiming the cycle could result in the rest of the system seeing a bad transaction as a good transaction.
functional description 122 datasheet 5.1.4 pcirst# the pcirst# pin is genera ted under two conditions: ?pltrst# active ? bctrl.sbr (d30:f0:offset 3eh:bit 6) set to 1 the pcirst# pin is in the suspend well. pcir st# should be tied to pci bus agents, but not other agents in the system. 5.1.5 peer cycles the pci bridge may be the initiator of peer cycles. peer cycles include memory, i/o, and configuration cycle types. peer cycles are only allowed through vc0, and are enabled with the following bits: ? bpc.pde (d30:f0:offset 4ch:bit 2) ? memory and i/o cycles ? bpc.cde (d30:f0:offset 4ch:bit 1) ? configuration cycles when enabled for peer for one of the above cycle types, the pci bridge will perform a peer decode to see if a peer agent can receive the cycle. when not enabled, memory cycles (posted and/or non-posted) are sent to dmi, and i/o and/or configuration cycles are not claimed. configuration cycles have special considerations. under the pci local bus specification , these cycles are not allowed to be forwarded upstream through a bridge. however, to enable things such as manage ability, bpc.cde can be set. when set, type 1 cycles are allowed into the part. the address format of the type 1 cycle is slightly different from a standard pci configuration cycle to allow addr essing of extended pci space. the format is shown in ta b l e 5 - 2 . note: the pch usb controllers cannot perform peer-to-peer traffic. 5.1.6 pci-to-pci bridge model from a software perspective, the pch contains a pci-to-pci bridge. this bridge connects dmi to the pci bus. by using the pc i-to-pci bridge software model, the pch can have its decode ranges programmed by existing plug-and-play software such that pci ranges do not conflict with graphics aperture ranges in the host controller. table 5-2. type 1 address format bits definition 31:27 reserved (same as the pci local bus specification ) 26:24 extended configuration address ? allows a ddressing of up to 4 kb. these bits are combined with bits 7:2 to get the full register. 23:16 bus number (same as the pci local bus specification ) 15:11 device number (same as the pci local bus specification ) 10:8 function number (same as the pci local bus specification ) 7:2 register (same as the pci local bus specification ) 10 0 must be 1 to indicate a type 1 cy cle. type 0 cycles are not decoded.
datasheet 123 functional description 5.1.7 idsel to device number mapping when addressing devices on the external pc i bus (with the pci slots), the pch asserts one address signal as an idsel. when a ccessing device 0, the pch asserts ad16. when accessing device 1, the pch asserts ad17. this mapping continues all the way up to device 15 where the pch asserts ad31. note that the pch internal functions (intel ? high definition audio, usb, sata and pci bridge) are enumerated like they are off of a separate pci bus (dmi) from the external pci bus. 5.1.8 standard pci bus configuration mechanism the pci bus defines a slot based ?configuration space? that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. the pci local bus specification, revision 2.3 defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the processor. configuration space is supported by a mapping mechanism implemented within the pch. the pci local bus specification, revision 2.3 defines two mechanisms to access configuration space, mechanism 1 and mechanism 2. the pch only supports mechanism 1. warning: configuration writes to internal devices, when the devices are disabled, are illegal and may cause undefined results. 5.1.9 pci legacy mode for some pch skus, native pci functionalit y is not supported requiring methods such as using pcie*-to-pci bridges to enable external pci i/o devices. to be able to use pcie-to-pci bridges and attached legacy pci devices, the pch provides pci legacy mode. pci legacy mode allows both the pci express* root port and pcie-to-pci bridge look like subtractive pci-to-pci bridges. th is allows the pci express root port to subtractively decode and forward legacy cycles to the bridge, and the pcie-to-pci bridge continues forwarding legacy cycles to downstream pci devices. for designs that would like to utilize pci legacy mode, bios must program registers in the dmi-to-pci bridge (device 30:function 0) and in the desired pci express root port (device 28:functions 0-7) to enable subtractive decode. note: software must ensure that only one pch device is enabled for subtractive decode at a time.
functional description 124 datasheet 5.2 pci express* root port s (d28:f0,f1,f2,f3,f4,f5, f6, f7) there are eight root ports available in the pch. the root ports are compliant to the pci express 2.0 specification running at 5.0 gt/s. the ports all reside in device 28, and take function 0 ? 7. port 1 is function 0, port 2 is function 1, port 3 is function 2, port 4 is function 3, port 5 is function 4, port 6 is function 5, port 7 is function 6, and port 8 is function 7. note: this section assumes the default pci express function number-to-root port mapping is used. function numbers for a given root port are assignable through the root port function number and hide for pci express root ports register (rcba+0404h). pci express root ports 1?4 or ports 5?8 can independently be configured as four x1s, two x2s, one x2 and two x1s, or one x4 port widths. the port configuration is set by soft straps in the flash descriptor. 5.2.1 interrupt generation the root port generates interrupts on behalf of hot-plug and power management events, when enabled. these interrupts can ei ther be pin based, or can be msis, when enabled. when an interrupt is generated using the legacy pin, the pin is internally routed to the pch interrupt controllers. the pin that is driv en is based upon the setting of the chipset configuration registers. specifically, the chipset configuration registers used are the d28ip (base address + 310ch) and d2 8ir (base address + 3146h) registers. ta b l e 5 - 3 summarizes interrupt behavior for msi and wire-modes. in the table ?bits? refers to the hot-plug and pme interrupt bits. table 5-3. msi versus pci irq actions interrupt register wire-mode action msi action all bits 0 wire inactive no action one or more bits set to 1 wire active send message one or more bits set to 1, new bit gets set to 1 wire active send message one or more bits set to 1, so ftware clears some (but not all) bits wire active send message one or more bits set to 1, software clears all bits wire inactive no action software clears one or more bits, and one or more bits are set on the same clock wire active send message
datasheet 125 functional description 5.2.2 power management 5.2.2.1 s3/s4/s5 support software initiates the transition to s3/s4/s5 by performing an i/o write to the power management control register in the pch. after the i/o write completion has been returned to the processor, each root port will send a pme_turn_off tlp (transaction layer packet) message on its downstream lin k. the device attached to the link will eventually respond with a pme_to_ack tlp message followed by sending a pm_enter_l23 dllp (data link layer packet) request to enter the l2/l3 ready state. when all of the pch root ports links are in the l2/l3 ready state, the pch power management control logic will proceed with the entry into s3/s4/s5. prior to entering s3, software is re quired to put each device into d3 hot . when a device is put into d3 hot , it will initiate entry into a l1 link state by sending a pm_enter_l1 dllp. thus, under normal operating conditions when the root ports sends the pme_turn_off message, the link will be in st ate l1. however, when the root port is instructed to send the pme_turn_off message, it will send it whether or not the link was in l1. endpoints attached to pch can make no assumptions about the state of the link prior to receiving a pme_turn_off message. 5.2.2.2 resuming from suspended state the root port contains enough circuitry in the suspend well to detect a wake event through the wake# signal and to wake the system. when wake# is detected asserted, an internal signal is sent to the power management controller of the pch to cause the system to wake up. this internal message is not logged in any register, nor is an interrupt/gpe generated due to it. 5.2.2.3 device initiated pm_pme message when the system has returned to a working state from a previous low power state, a device requesting service will send a pm_pme message continuously, until acknowledged by the root port. the root port will take different actions depending upon whether this is the first pm_pme that ha s been received, or whether a previous message has been received but not yet serviced by the operating system. if this is the first message received (rsts.ps - d28:f0/f1/f2/f3/f4/f5/f6/f7:offset 60h:bit 16 is cleared), the root port will set rsts.ps, and log the pme requester id into rsts.rid (d28:f0/f1/f2/f3/f4/f5/f6/f7:o ffset 60h:bits 15:0). if an interrupt is enabled using rctl.pie (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset 5ch:bit 3), an interrupt will be generated. this interrupt can be eith er a pin or an msi if msi is enabled using mc.msie (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset 82h:bit 0). see section 5.2.2.4 for smi/sci generation. if this is a subsequent message received (rst s.ps is already set), the root port will set rsts.pp (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset 60h:bit 17) and log the pme requester id from the message in a hidden register. no other action will be taken. when the first pme event is cleared by softwa re clearing rsts.ps, the root port will set rsts.ps, clear rsts.pp, and move the requester id from the hidden register into rsts.rid. if rctl.pie is set, an interrupt will be gene rated. if rctl.pie is not set, a message will be sent to the power management controller so that a gpe can be set. if messages have been logged (rsts.ps is set), and rctl.pie is later written from a 0 to a 1, an interrupt will be generated. this last condition handles the case where the message was received prior to the operating system re-enabling interrupts after resuming from a low power state.
functional description 126 datasheet 5.2.2.4 smi/sci generation interrupts for power management events are not supported on legacy operating systems. to support power management on non-pci express aware operating systems, pm events can be routed to generate sci. to generate sci, mpc.pmce must be set. when set, a power management event w ill cause smscs.pmcs (d28:f0/f1/f2/f3/f4/ f5/f6/f7:offset dch:bit 31) to be set. additionally, bios workarounds for power management can be supported by setting mpc.pmme (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset d8h:bit 0). when this bit is set, power management events will set smscs.pmms (d28:f0/f1/f2/f3/f4/f5/f6/ f7:offset dch:bit 0), and smi # will be generated. this bit will be set regardless of whether interrupts or sci is enabled. th e smi# may occur concurrently with an interrupt or sci. 5.2.3 serr# generation serr# may be generated using two paths ? through pci mechanisms involving bits in the pci header, or through pci express * mechanisms involving bits in the pci express capability structure. 5.2.4 hot-plug each root port implements a hot-plug controller that performs the following: ? messages to turn on/off/blink leds ? presence and attention button detection ? interrupt generation the root port only allows hot-plug with modules (such as, expresscard*). edge- connector based hot-plug is not supported. 5.2.4.1 presence detection when a module is plugged in and power is supplied, the physical layer will detect the presence of the device, and the root po rt sets slsts.pds (d28:f0/f1/f2/f3/f4/ f5:offset 5ah:bit 6) and slsts.pdc (d28:f0/f1/f2/f3:offset 6h:bit 3). if slctl.pde (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset 58h:bit 3) and slctl.hpe (d28:f0/f1/f2/f3/ f4/f5/f6/f7:offset 58h:bit 5) are both set, the root port will also generate an interrupt. figure 5-1. generation of serr# to platform psts.sse serr# pcicmd.see secondary parity error primary parity error secondary serr# correctable serr# fatal serr# non-fatal serr# pci pci express
datasheet 127 functional description when a module is removed (using the physic al layer detection), the root port clears slsts.pds and sets slsts.pdc. if slctl.pde and slctl.hpe are both set, the root port will also generate an interrupt. 5.2.4.2 message generation when system software writes to slctl.aic (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset 58h:bits 7:6) or slctl.pic (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset 58h:bits 9:8), the root port will send a message down the link to change the state of leds on the module. writes to these fields are non-postable cycles, and the resulting message is a postable cycle. when receiving one of these writes , the root port performs the following: ? changes the state in the register. ? generates a completion into the upstream queue ? formulates a message for the downstream port if the field is written to regardless of if the field changed. ? generates the message on the downstream port ? when the last message of a command is transmitted, sets slsts.cce (d28:f0/f1/ f2/f3/f4/f5/f6/f7:offset 58h:bit 4) to indicate the command has completed. if slctl.cce and slctl.hpe (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset 58h:bit 5) are set, the root port generates an interrupt. the command completed register (slsts.cc) applies only to commands issued by software to control the attention indicator (slctl.aic), power indicator (slctl.pic), or power controller (slctl.pcc). however, writes to other parts of the slot control register would invariably end up writing to the indicators and power controller fields. hence, any write to the slot control register is considered a command and if enabled, will result in a command complete interrupt. the only exception to this rule is a write to disable the command complete interrupt whic h will not result in a command complete interrupt. a single write to the slot control register is considered to be a single command, and hence receives a single command complete, even if the write affects more than one field in the slot control register. 5.2.4.3 attention button detection when an attached device is ejected, an a ttention button could be pressed by the user. this attention button press will result in a the pci express message ?attention_button_pressed? from the device . upon receiving this message, the root port will set slsts.abp (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset 5ah:bit 0). if slctl.abe (d28:f0/f1/f2/f3/f4/f5:offset 58h:bit 0) and slctl.hpe (d28:f0/f1/ f2/f3/f4/f5/f6/f7:offset 58h:bit 5) are set, the hot-plug controller will also generate an interrupt. the interrupt is generated on an edge-event. for example, if slsts.abp is already set, a new interrupt will not be generated. 5.2.4.4 smi/sci generation interrupts for hot-plug events are not supp orted on legacy operating systems. to support hot-plug on n on-pci express aware operating systems, hot-plug events can be routed to generate sci. to generate sci, mpc.hpce (d28:f0/f1/f2/f3/f4/f5/f6/ f7:offset d8h:bit 30) must be set. when set, enabled hot-plug events will cause smscs.hpcs (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset dch:bit 30) to be set.
functional description 128 datasheet additionally, bios workarounds for hot-plug can be supported by setting mpc.hpme (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset d8h:bit 1). when this bit is set, hot-plug events can cause smi status bits in smscs to be set. supported hot-plug events and their corresponding smscs bit are: ? command completed ? scscs.hpccm (d 28:f0/f1/f2/f3/f4/f5/f6/f7:offset dch:bit 3) ? presence detect changed ? smscs.hppdm (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset dch:bit 1) ? attention button pressed ? smscs.hpabm (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset dch:bit 2) ? link active state changed ? smscs.hpla s (d28:f0/f1/f2/f3/f4/f5/f6/f7:offset dch:bit 4) when any of these bits are set, smi# will be generated. these bits are set regardless of whether interrupts or sci is enabled for hot-plug events. the smi# may occur concurrently with an interrupt or sci. 5.3 gigabit ethernet controller (b0:d25:f0) the pch integrates a gigabit ethernet (gbe) controller. the integrated gbe controller is compatible with the intel ? 82579 platform lan connect device. the integrated gbe controller provides two interfaces for 10/ 100/1000 mb/s and manageability operation: ? based on pci express ? a high-speed serdes interface using pci express electrical signaling at half speed while keeping the custom logical protocol for active state operation mode. ? system management bus (smbus) ? a very low speed connection for low power state mode for manageability communication only. at this low power state mode the ethernet link speed is reduced to 10 mb/s. the 82579 can be connected to any availabl e pci express port in the pch. the 82579 only runs at a speed of 1250 mb/s, which is 1/2 of the 2.5 gb/s pci express frequency. each of the pci express root ports in the pc h have the ability to run at the 1250 mb/s rate. there is no need to implement a mechanism to detect that the 82579 lan device is connected. the port configuration (if any), attached to the 82579 lan device, is pre- loaded from the nvm. the selected port adjusts the transmitter to run at the 1250 mb/s rate and does not need to be pci express compliant. note: pcie validation tools cannot be used for electrical validation of this interface; however, pcie layout rules apply for on-board routing. the integrated gbe controller operates at fu ll-duplex at all supported speeds or half- duplex at 10/100 mb/s. it also adheres to the ieee 802.3x flow control specification. note: gbe operation (1000 mb/s) is only supported in s0 mode. in sx modes, smbus is the only active bus and is used to support manageability/remote wake-up functionality. the integrated gbe controller provides a syst em interface using a pci express function. a full memory-mapped or i/o-mapped interface is provided to the software, along with dma mechanisms for high performance data transfer.
datasheet 129 functional description the integrated gbe controller features are: ?network features ? compliant with the 1 gb/s ethern et 802.3 802.3u 802.3ab specifications ? multi-speed operation: 10/100/1000 mb/s ? full-duplex operation at 10/100/1000 mb/s: half-duplex at 10/100 mb/s ? flow control support compliant with the 802.3x specification ? vlan support compliant with the 802.3q specification ? mac address filters: perfect match unica st filters; multicast hash filtering, broadcast filter and promiscuous mode ? pci express/smbus interface to gbe phys ? host interface features ? 64-bit address master support for system s using more than 4 gb of physical memory ? programmable host memory receive buffers (256 bytes to 16 kb) ? intelligent interrupt generation feat ures to enhance driver performance ? descriptor ring management hard ware for transmit and receive ? software controlled reset (resets everything except the configuration space) ? message signaled interrupts ? performance features ? configurable receive and transmit data fifo, programmable in 1 kb increments ? tcp segmentation capability compatib le with windows nt* 5.x off loading features ? fragmented udp checksum offload for packet reassembly ? ipv4 and ipv6 checksum offload support (receive, transmit, and tcp segmentation offload) ? split header support to eliminate payload copy from user space to host space ? receive side scaling (rss) with two hardware receive queues ? supports 9018 bytes of jumbo packets ?packet buffer size ? linksec offload compliant with 802.3ae specification ? timesync offload compliant with 802.1as specification ? virtualization technology features ? warm function reset ? function level reset (flr) ?vmdq1 ? power management features ? magic packet* wake-up enable with unique mac address ? acpi register set and power down functionality supporting d0 and d3 states ? full wake up support (apm, acpi) ? mac power down at sx, dmoff with and without wol
functional description 130 datasheet 5.3.1 gbe pci express* bus interface the gbe controller has a pci express interface to the host processor and host memory. the following sections detail the bus transactions. 5.3.1.1 transaction layer the upper layer of the host architecture is the transaction layer. the transaction layer connects to the device core using an implementation specific protocol. through this core-to-transaction-layer protocol, the applicat ion-specific parts of the device interact with the subsystem and transmit and receive requests to or from the remote agent, respectively. 5.3.1.2 data alignment 5.3.1.2.1 4-kb boundary pci requests must never specify an address/length combination that causes a memory space access to cross a 4 kb boundary. it is hardware?s responsibility to break requests into 4 kb-aligned requests (if needed). this does not pose any requirement on software. however, if software allocates a buffer across a 4-kb boundary, hardware issues multiple requests for the buffer. soft ware should consider aligning buffers to a 4-kb boundary in cases where it improves performance. the alignment to the 4-kb boundaries is done in the core. the transaction layer does not do any alignment according to these boundaries. 5.3.1.2.2 64 bytes pci requests are multiples of 64 bytes an d aligned to make better use of memory controller resources. writes, however, can be on any boundary and can cross a 64-byte alignment boundary. 5.3.1.3 configuration request retry status the integrated gbe controller might have a delay in initialization due to an nvm read. if the nvm configuration read operation is not completed and the device receives a configuration request, the device respon ds with a configuration request retry completion status to terminate the request, and thus effectively stalls the configuration request until such time that the sub-system has completed local initialization and is ready to communicate with the host.
datasheet 131 functional description 5.3.2 error events and error reporting 5.3.2.1 data parity error the pci host bus does not provide parity prot ection, but it does forward parity errors from bridges. the integrated gbe controlle r recognizes parity errors through the internal bus interface and sets the parity error bit in pci configuration space. if parity errors are enabled in configuration space, a system error is indicated on the pci host bus. the offending cycle with a parity e rror is dropped and not processed by the integrated gbe controller. 5.3.2.2 completion with unsu ccessful completion status a completion with unsuccessful completion status (any status other than 000) is dropped and not processed by the integrated gbe controller. furthermore, the request that corresponds to the unsuccessful completion is not retried. when this unsuccessful completion status is received, the system error bit in the pci configuration space is set. if the system errors are enabled in configur ation space, a system error is indicated on the pci host bus. 5.3.3 ethernet interface the integrated gbe controller provides a co mplete csma/cd function supporting ieee 802.3 (10 mb/s), 802.3u (100 mb/s) implementa tions. it also supports the ieee 802.3z and 802.3ab (1000 mb/s) implementations. th e device performs all of the functions required for transmission, reception, and collision handling called out in the standards. the mode used to communicate between the pch and the 82579 phy supports 10/100/ 1000 mb/s operation, with both half- and full-duplex operation at 10/100 mb/s, and full-duplex operation at 1000 mb/s. 5.3.3.1 82579 lan phy interface the integrated gbe controller and the 82579 phy communicate through the pcie and smbus interfaces. all integrated gbe controlle r configuration is performed using device control registers mapped into system me mory or i/o space. the 82579 device is configured using the pci express or smbus interface. the integrated gbe controller supports various modes as listed in ta b l e 5 - 4 . table 5-4. lan mode support mode system state interface active connections normal 10/100/1000 mb/s s0 pci express or smbus 1 notes: 1. gbe operation is not supported in sx states. 82579 manageability and remote wake-up sx smbus 82579
functional description 132 datasheet 5.3.4 pci power management the integrated gbe controller supports the advanced configuration and power interface (acpi) specification as well as advanced power management (apm). this enables the network-related activity (using an internal host wake signal) to wake up the host. for example, from sx (s3?s5) to s0. the integrated gbe controller contains power management registers for pci and supports d0 and d3 states. pcie transactions are only allowed in the d0 state, except for host accesses to the integrated gbe controller?s pci configuration registers. 5.3.4.1 wake up the integrated gbe controller supports two types of wake-up mechanisms: 1. advanced power management (apm) wake up 2. acpi power management wake up both mechanisms use an internal logic signal to wake the system up. the wake-up steps are as follows: 1. host wake event occurs (note that packet is not delivered to host). 2. the 82579 receives a wol packet/link status change. 3. the 82579 wakes up the integrated gbe controller using an smbus message. 4. the integrated gbe controller sets the pme_status bit. 5. system wakes from sx state to s0 state. 6. the host lan function is transitioned to d0. 7. the host clears the pme_status bit. 5.3.4.1.1 advanced power management wake up advanced power management wake up or apm wake up was previously known as wake on lan (wol). it is a feature that has existed in the 10/100 mb/s nics for several generations. the basic premise is to receive a broadcast or unicast packet with an explicit data pattern and then to assert a signal to wake up the system. in earlier generations, this was accomplished by using a special signal that ran across a cable to a defined connector on the motherboard. the nic would assert the signal for approximately 50 ms to signal a wake up. the integrated gbe controller uses (if configured to) an in-band pm_pme message for this. at power up, the integrated gbe controller reads the apm enable bits from the nvm pci init control word into the apm enable (apme) bits of the wake up control (wuc) register. these bits control enabling of apm wake up. when apm wake up is enabled, the integr ated gbe controller checks all incoming packets for magic packets. once the integrated gbe controller receives a matching magic packet, it: ? sets the magic packet received bit in the wake up status (wus) register. ? sets the pme_status bit in the power management control/status register (pmcsr). apm wake up is supported in all power states and only disabled if a subsequent nvm read results in the apm wake up bit being cleared or the software explicitly writes a 0b to the apm wake up (apm) bit of the wuc register.
datasheet 133 functional description note: apm wake up settings will be restored to nvm default by the pch when lan connected device (phy) power is turned off and subsequently restored. some example host wol flows are: ? when system transitions to g3 after wol is disabled from the bios, apm host wol would get enabled. ? anytime power to the lan connected device (phy) is cycled while in s4/s5 after wol is disabled from the bios, apm host wol would get enabled. anytime power to the lan connected device (phy) is cycled while in s3, apm host wol configuration is lost. 5.3.4.1.2 acpi power management wake up the integrated gbe controller supports acpi power management based wake ups. it can generate system wake-up events from three sources: ? receiving a magic packet. ? receiving a network wake up packet. ? detecting a link change of state. activating acpi power management wakeup requires the following steps: ? the software device driver programs the wake up filter control (wufc) register to indicate the packets it needs to wake up from and supplies the necessary data to the ipv4 address table (ip4at) and the flex ible filter mask table (ffmt), flexible filter length table (fflt), and the flexible filter value table (ffvt). it can also set the link status change wake up enable (lnkc) bit in the wake up filter control (wufc) register to cause wake up when the link changes state. ? the operating system (at configuration time) writes a 1b to the pme_en bit of the power management control/status register (pmcsr.8). normally, after enabling wake up, the operating system writes a 11b to the lower two bits of the pmcsr to put the integrated gbe controller into low-power mode. once wake up is enabled, the integrated gbe controller monitors incoming packets, first filtering them according to its standa rd address filtering method, then filtering them with all of the enabled wake-up filter s. if a packet passes both the standard address filtering and at least one of the en abled wake-up filters, the integrated gbe controller: ? sets the pme_status bit in the pmcsr ? sets one or more of the received bits in the wake up status (wus) register. (more than one bit is set if a packet matches more than one filter.) if enabled, a link state change wake up causes similar results, setting the link status changed (lnkc) bit in the wake up status (wus) register when the link goes up or down. after receiving a wake-up packet, the integr ated gbe controller ignores any subsequent wake-up packets until the software device driver clears all of the received bits in the wake up status (wus) register. it also ignores link change events until the software device driver clears the link status changed (lnkc) bit in the wake up status (wus) register. note: acpi wake up settings are not preserved when the lan connected device (phy) power is turned off and subsequently restor ed. some example host wol flows are: ? anytime power to the lan connected device (phy) is cycled while in s3 or s4, acpi host wol configuration is lost.
functional description 134 datasheet 5.3.5 configurable leds the integrated gbe controller supports three controllable and configurable leds that are driven from the 82579 lan device. ea ch of the three led outputs can be individually configured to select the particular event, state, or activity that is indicated on that output. in addition, each led can be individually configured for output polarity as well as for blinking versus non-blinking (steady-state) indication. the configuration for led outputs is specifie d using the ledctl register. furthermore, the hardware-default configuration for all th e led outputs, can be specified using nvm fields; thereby, supporting led displays configurable to a particular oem preference. each of the three leds might be configured to use one of a variety of sources for output indication. the mode bits control the led source: ? link_100/1000 is asserted when link is established at either 100 or 1000 mb/s. ? link_10/1000 is asserted when link is established at either 10 or 1000 mb/s. ? link_up is asserted when any spee d link is established and maintained. ? activity is asserted when link is established and packets are being transmitted or received. ? link/activity is asserted when link is established and there is no transmit or receive activity ? link_10 is asserted when a 10 mb/ps link is established and maintained. ? link_100 is asserted when a 100 mb/s link is established and maintained. ? link_1000 is asserted when a 1000 mb/s link is established and maintained. ? full_duplex is asserted when the link is configured for full duplex operation. ? collision is asserted when a collision is observed. ? paused is asserted when the device's transmitter is flow controlled. ? led_on is always asserted; led_off is always deasserted. the ivrt bits enable the led source to be invert ed before being output or observed by the blink-control logic. led outputs are a ssumed to normally be connected to the negative side (cathode) of an external led. the blink bits control whether the led should be blinked while the led source is asserted, and the blinking frequency (either 200 ms on and 200 ms off or 83 ms on and 83 ms off). the blink control can be especially useful for ensuring that certain events, such as activity indication, cause led transitions, which are sufficiently visible to a human eye. the same blinking rate is shared by all leds.
datasheet 135 functional description 5.3.6 function level reset support (flr) the integrated gbe controller supports flr capability. flr capability can be used in conjunction with intel ? virtualization technology. flr al lows an operating system in a virtual machine to have complete control ov er a device, including its initialization, without interfering with the rest of the platform. the device provides a software interface that enables the operating system to reset the entire device as if a pci reset was asserted. 5.3.6.1 flr steps 5.3.6.1.1 flr initialization 1. flr is initiated by softwa re by writing a 1b to the initiate flr bit. 2. all subsequent requests targeting the function are not claimed and will be master aborted immediately on the bus. this incl udes any configuration, i/o or memory cycles. however, the function will continue to accept completions targeting the function. 5.3.6.1.2 flr operation function resets all configuration, i/o, an d memory registers of the function except those indicated otherwise and resets all internal states of the function to the default or initial condition. 5.3.6.1.3 flr completion the initiate flr bit is reset (cleared) when the fl r reset completes. this bit can be used to indicate to the software that the flr reset completed. note: from the time the initiate flr bit is written to 1b, software must wait at least 100 ms before accessing the function.
functional description 136 datasheet 5.4 lpc bridge (with system and management functions) (d31:f0) the lpc bridge function of the pch resides in pci device 31:function 0. in addition to the lpc bridge function, d31:f0 contains other functional units including dma, interrupt controllers, timers, power management, system management, gpio, and rtc. in this chapter, registers and functi ons associated with other functional units (power management, gpio, usb, etc.) are described in their respective sections. note: the lpc bridge cannot be configured as a subtractive decode agent. 5.4.1 lpc interface the pch implements an lpc interface as described in the low pin count interface specification, revision 1.1. the lpc interface to the pch is shown in figure 5-2 . note that the pch implements all of the signals that are shown as optional, but peripherals are not required to do so. figure 5-2. lpc interface diagram
datasheet 137 functional description 5.4.1.1 lpc cycle types the pch implements all of the cycle types described in the low pin count interface specification, revision 1.1. ta b l e 5 - 5 shows the cycle types supported by the pch. notes: 1. the pch provides a single generic memory ra nge (lgmr) for decoding memory cycles and forwarding them as lpc memory cycles on the lpc bus. the lgmr memory decode range is 64 kb in size and can be defined as being anyw here in the 4 gb me mory space. this range needs to be configured by bios duri ng post to provide the necessary memory resources. bios should advertise the lpc generic memory range as reserved to the os in order to avoid resource conflict. for larger transfers, the pch performs multiple 8-bit transfers. if the cycle is not claimed by any pe ripheral, it is subsequently aborted, and the pch returns a value of all 1s to the processor. this is done to maintain compatibility with isa memory cycles where pull-up resistors woul d keep the bus high if no device responds. 2. bus master read or write cycles must be naturally aligned. for example, a 1-byte transfer can be to any address. however, the 2-byte tran sfer must be word-aligned (that is, with an address where a0=0). a dword transfer must be dword-aligned (that is, with an address where a1 and a0 are both 0). 5.4.1.2 start field definition note: all other encodings are reserved. table 5-5. lpc cycle types supported cycle type comment memory read 1 byte only. (see note 1 below) memory write 1 byte only. (see note 1 below) i/o read 1 byte only. the pch breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. i/o write 1 byte only. the pch breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. dma read can be 1, or 2 bytes dma write can be 1, or 2 bytes bus master read can be 1, 2, or 4 bytes. (see note 2 below) bus master write can be 1, 2, or 4 bytes. (see note 2 below) table 5-6. start field bit definitions bits[3:0] encoding definition 0000 start of cycle for a generic target 0010 grant for bus master 0 0011 grant for bus master 1 1111 stop/abort: end of a cycle for a target.
functional description 138 datasheet 5.4.1.3 cycle type / di rection (cyctype + dir) the pch always drives bit 0 of this field to 0. peripherals running bus master cycles must also drive bit 0 to 0. ta b l e 5 - 7 shows the valid bit encodings. 5.4.1.4 size bits[3:2] are reserved. the pch always drives them to 00. peripherals running bus master cycles are also supposed to drive 00 for bits 3:2; however, the pch ignores those bits. bits[1:0] are encoded as listed in ta b l e 5 - 8 . 5.4.1.5 sync valid values for the sync field are shown in ta b l e 5 - 9 . table 5-7. cycle type bit definitions bits[3:2] bit1 definition 00 0 i/o read 00 1 i/o write 01 0 memory read 01 1 memory read 10 0 dma read 10 1 dma write 11 x reserved. if a peripheral performing a bus master cycle generates this value, the pch aborts the cycle. table 5-8. transfer size bit definition bits[1:0] size 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) 10 reserved. the pch never drives this comb ination. if a peripheral running a bus master cycle drives this combination, the pch may abort the transfer. 11 32-bit transfer (4 bytes) table 5-9. sync bit definition (sheet 1 of 2) bits[3:0] indication 0000 ready: sync achieved with no error. for dm a transfers, this also indicates dma request deassertion and no more transfers desired for that channel. 0101 short wait: part indicating wait-states. for bu s master cycles, the pch does not use this encoding. instead, the pch uses the long wait encoding (see next encoding below). 0110 long wait: part indicating wait-sta tes, and many wait-state s will be added. this encoding driven by the pch for bus master cycles, rather than the short wait (0101). 1001 ready more (used only by peripheral for dma cycle): sync achieved with no error and more dma transfers desired to cont inue after this transfer. this value is valid only on dma transfers and is no t allowed for any other type of cycle.
datasheet 139 functional description notes: 1. all other combinations are reserved. 2. if the lpc controller receives any sync retu rned from the device other than short (0101), long wait (0110), or ready (0000) when running a fwh cycle, indeterminate results may occur. a fwh device is not allo wed to assert an error sync. 5.4.1.6 sync time-out there are several error cases that can occur on the lpc interface. the pch responds as defined in section 4.2.1.9 of the low pin count interface specification , revision 1.1 to the stimuli described therein. there may be other peripheral failure conditions; however, these are not handled by the pch. 5.4.1.7 sync error indication the pch responds as defined in section 4.2.1.10 of the low pin count interface specification, revision 1.1. upon recognizing the sync field indicating an error, the pch treats this as a serr by reporting this into the device 31 error reporting logic. 5.4.1.8 lframe# usage the pch follows the usage of lframe# as defined in the low pin count interface specification, revision 1.1. the pch performs an abort for the follo wing cases (possible failure cases): ? the pch starts a memory, i/o, or dma cy cle, but no device drives a valid sync after four consecutive clocks. ? the pch starts a memory, i/o, or dma cycle, and the peripheral drives an invalid sync pattern. ? a peripheral drives an illegal address when performing bus master cycles. ? a peripheral drives an invalid value. 5.4.1.9 i/o cycles for i/o cycles targeting registers specif ied in the pch?s decode ranges, the pch performs i/o cycles as defined in the low pin count interface specification, revision 1.1. these are 8-bit transfers. if the processor attempts a 16-bit or 32-bit transfer, the pch breaks the cycle up into multiple 8-bit transfers to consecutive i/o addresses. note: if the cycle is not claimed by any peripheral (and subsequently aborted), the pch returns a value of all 1s (ffh) to the processor. this is to maintain compatibility with isa i/o cycles where pull-up resistors would keep the bus high if no device responds. 1010 error: sync achieved with error. this is ge nerally used to replace the serr# or iochk# signal on the pci/isa bus. it indicates that the data is to be transferred, but there is a serious error in this transfer. for dma transfers, this not only indicates an error, but also indicates dma request deassertion and no mo re transfers desired for that channel. table 5-9. sync bit definition (sheet 2 of 2) bits[3:0] indication
functional description 140 datasheet 5.4.1.10 bus master cycles the pch supports bus master cycles and requests (using ldrq#) as defined in the low pin count interface specification, revision 1.1. the pch has two ldrq# inputs, and thus supports two separate bus master devices. it uses the associated start fields for bus master 0 (0010b) or bus master 1 (0011b). note: the pch does not support lpc bus masters performing i/o cycles. lpc bus masters should only perform memory read or memory write cycles. 5.4.1.11 lpc power management lpcpd# protocol same timings as for sus_stat#. upon driving sus_stat# low, lpc peripherals drive ldrq# low or tri-state it. the pch shuts off the ldrq# input buffers. after driving sus_stat# active, the pch drives lframe# low, and tri-states (or drives low) lad[3:0]. note: the low pin count interface specification, revision 1.1 defines the lpcpd# protocol where there is at least 30 s from lpcpd# assertion to lrst# assertion. this specification explicitly states that this protocol only applies to entry/exit of low power states which does not include asynchrono us reset events. the pch asserts both sus_stat# (connects to lpcpd#) and pltrst# (connects to lrst#) at the same time during a global reset. this is not inconsistent with the lpc lpcpd# protocol. 5.4.1.12 configuration and pch implications lpc i/f decoders to allow the i/o cycles and memory mapped cycles to go to the lpc interface, the pch includes several decoders. during configurat ion, the pch must be programmed with the same decode ranges as the peripheral. the decoders are programmed using the device 31:function 0 configuration space. note: the pch cannot accept pci write cycles from pci-to-pci bridges or devices with similar characteristics (specifically those with a ?ret ry read? feature which is enabled) to an lpc device if there is an outstanding lpc read cycle towards the same pci device or bridge. these cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures. bus master device mapping and start fields bus masters must have a unique start field. in the case of the pch that supports two lpc bus masters, it drives 0010 for the start field for grants to bus master 0 (requested using ldrq0#) and 0011 for grants to bus master 1 (requested using ldrq1#.). thus, no registers are needed to configure the start fields for a particular bus master.
datasheet 141 functional description 5.5 dma operation (d31:f0) the pch supports lpc dma using the pch?s dma controller. the dma controller has registers that are fixed in the lower 64 kb of i/o space. the dma controller is configured using registers in the pci configuration space. these registers allow configuration of the channels for use by lpc dma. the dma circuitry incorporates the functi onality of two 82c37 dma controllers with seven independently programmable channels ( figure 5-3 ). dma controller 1 (dma-1) corresponds to dma channels 0?3 and dma controller 2 (dma-2) corresponds to channels 5?7. dma channel 4 is used to cascade the two controllers and defaults to cascade mode in the dma channel mode (dcm ) register. channel 4 is not available for any other purpose. in addition to accepting requests from dma slaves, the dma controller also responds to requests that so ftware initiates. software may initiate a dma service request by setting any bit in the dma channel request register to a 1. each dma channel is hardwired to the co mpatible settings for dma device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. the pch provides 24-bit addressing in compliance with the isa-compatible specification. each channel includes a 16-bit isa-compatible current register which holds the sixteen least-significant bits of the 24-bit address, an isa-compatible page register which contains the eight next most significant bits of address. the dma controller also features refresh address generation, and auto-initialization following a dma termination. 5.5.1 channel priority for priority resolution, the dma consists of two logical channel groups: channels 0?3 and channels 4?7. each group may be in either fixed or rotate mode, as determined by the dma command register. dma i/o slaves normally assert their dreq line to arbitrate for dma service. however, a software request for dma service can be presented through each channel's dma request register. a software request is subject to the same prioritization as any hardware request. see the detailed register description for request register programming information in section 13.2 . 5.5.1.1 fixed priority the initial fixed priority structure is as follows: the fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. in this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. channels [3:0] of dma-1 assume the priority position of channel 4 in dma-2, thus taking priority over channels 5, 6, and 7. figure 5-3. pch dma controller channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 dma-1 dma-2 high priority low priority 0, 1, 2, 3 5, 6, 7
functional description 142 datasheet 5.5.1.2 rotating priority rotation allows for ?fairness? in priority resolution. the priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0?3, 5?7). channels 0?3 rotate as a group of 4. they are always placed between channel 5 and channel 7 in the priority list. channel 5?7 rotate as part of a group of 4. that is, channels (5?7) form the first three positions in the rotation, while channel group (0?3) comprises the fourth position in the arbitration. 5.5.2 address compatibility mode when the dma is operating, the addresses do not increment or decrement through the high and low page registers. therefore, if a 24-bit address is 01ffffh and increments, the next address is 010000h, not 020000h. similarly, if a 24-bit address is 020000h and decrements, the next address is 02ffffh, not 01ffffh. however, when the dma is operating in 16-bit mode, the addresses st ill do not increment or decrement through the high and low page registers but the page boundary is now 128 k. therefore, if a 24-bit address is 01fffeh and increments, the next address is 000000h, not 0100000h. similarly, if a 24-bit address is 020000h and decrements, the next address is 03fffeh, not 02fffeh. this is compatible with the 82c37 and page register implementation used in the pc-at. this mode is set after cpurst is valid. 5.5.3 summary of dma transfer sizes ta b l e 5 - 1 0 lists each of the dma device transfer sizes. the column labeled ?current byte/word count register? indicates that the register contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. the column labeled ?current address increment/decrem ent? indicates the number added to or taken from the current address register after each dma transfer cycle. the dma channel mode register determines if the cu rrent address register will be incremented or decremented. 5.5.3.1 address shifti ng when programmed for 16-bit i/o count by words the pch maintains compatibility with the implementation of the dma in the pc at that used the 82c37. the dma shifts the addre sses for transfers to/from a 16-bit device count-by-words. note: the least significant bit of the low page re gister is dropped in 16-bit shifted mode. when programming the current address regi ster (when the dma channel is in this mode), the current address must be progra mmed to an even address with the address value shifted right by one bit. table 5-10. dma transfer size dma device date size and word count current byte/word count register current address increment/ decrement 8-bit i/o, count by bytes bytes 1 16-bit i/o, count by words (address shifted) words 1
datasheet 143 functional description the address shifting is shown in ta b l e 5 - 1 1 . note: the least significant bit of the page register is droppe d in 16-bit shifted mode. 5.5.4 autoinitialize by programming a bit in the dma channel mode register, a channel may be set up as an autoinitialize channel. when a channel undergoes auto initialization, the original values of the current page, current address and current byte/word count registers are automatically restored from the base page, address, and byte/word count registers of that channel following tc. the base registers are loaded simultaneously with the current registers by the microprocessor when the dma channel is programmed and remain unchanged throughout the dma service. the mask bit is not set when the channel is in autoinitialize. follo wing autoinitialize, the channel is ready to perform another dma service, without processo r intervention, as soon as a valid dreq is detected. 5.5.5 software commands there are three additional special software commands that the dma controller can execute. the three software commands are: ? clear byte pointer flip-flop ?master clear ? clear mask register they do not depend on any specific bit pattern on the data bus. table 5-11. address shifting in 16-bit i/o dma transfers output address 8-bit i/o programmed address (ch 0C3) 16-bit i/o programmed address (ch 5C7) (shifted) a0 a[16:1] a[23:17] a0 a[16:1] a[23:17] 0 a[15:0] a[23:17]
functional description 144 datasheet 5.6 lpc dma dma on lpc is handled through the use of the ldrq# lines from peripherals and special encodings on lad[3:0] from the ho st. single, demand, verify, and increment modes are supported on the lpc interface. channels 0?3 are 8-bit channels. channels 5?7 are 16-bit channels. channel 4 is reserved as a generic bus master request. 5.6.1 asserting dma requests peripherals that need dma service encode their requested channel number on the ldrq# signal. to simplify the protocol, each peripheral on the lpc i/f has its own dedicated ldrq# signal (they may not be sh ared between two separate peripherals). the pch has two ldrq# inputs, allowing at least two devices to support dma or bus mastering. ldrq# is synchronous with lclk (pci clock). as shown in figure 5-4 , the peripheral uses the following serial encoding sequence: ? peripheral starts the sequence by assert ing ldrq# low (start bit). ldrq# is high during idle conditions. ? the next three bits contain the encoded dma channel number (msb first). ? the next bit (act) indicates whether the request for the indicated dma channel is active or inactive. the act bit is 1 (high) to in dicate if it is active and 0 (low) if it is inactive. the case where act is low is rare, and is only used to indicate that a previous request for that channel is being abandoned. ? after the active/inactive indication, the ldrq# signal must go high for at least one clock. after that one clock, ldrq# signal can be brought low to the next encoding sequence. if another dma channel also needs to reques t a transfer, another sequence can be sent on ldrq#. for example, if an encoded reques t is sent for channel 2, and then channel 3 needs a transfer before the cycle for channe l 2 is run on the interface, the peripheral can send the encoded request for channel 3. this allows multiple dma agents behind an i/o device to request use of the lpc inte rface, and the i/o device does not need to self-arbitrate before sending the message. figure 5-4. dma request assertion through ldrq# start msb lsb act start lclk ldrq#
datasheet 145 functional description 5.6.2 abandoning dma requests dma requests can be deasserted in two fashions: on error conditions by sending an ldrq# message with the ?act? bit set to 0, or normally through a sync field during the dma transfer. this section describes boundary conditions where the dma request needs to be removed prior to a data transfer. there may be some special cases where the peripheral desires to abandon a dma transfer. the most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its fifo, or software stopping a device prematurely. in these cases, the peripheral wishes to stop further dma activity. it may do so by sending an ldrq# message with the act bit as 0. however, since the dma request was seen by the pch, there is no assurance th at the cycle has not been granted and will shortly run on lpc. therefore, peripherals mu st take into account that a dma cycle may still occur. the peripheral can choose not to respond to this cycle, in which case the host will abort it, or it can choose to complete the cycle normally with any random data. this method of dma deassertion should be prevented whenever possible, to limit boundary conditions both on the pch and the peripheral. 5.6.3 general flow of dma transfers arbitration for dma channels is performed th rough the 8237 within the host. once the host has won arbitration on behalf of a dma channel assigned to lpc, it asserts lframe# on the lpc i/f and begins the dma transfer. the general flow for a basic dma transfer is as follows: 1. the pch starts transfer by asserting 00 00b on lad[3:0] with lframe# asserted. 2. the pch asserts ?cycle type? of dma, direction based on dma transfer direction. 3. the pch asserts channel number and, if applicable, terminal count. 4. the pch indicates the size of the transfer: 8 or 16 bits. 5. if a dma read? ? the pch drives the first 8 bits of data and turns the bus around. ? the peripheral acknowledges the data with a valid sync. ? if a 16-bit transfer, the process is repeated for the next 8 bits. 6. if a dma write? ? the pch turns the bus around and waits for data. ? the peripheral indicates data ready th rough sync and transfers the first byte. ? if a 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. the peripheral turns around the bus. 5.6.4 terminal count terminal count is communicated through lad[3] on the same clock that dma channel is communicated on lad[2:0]. this field is th e channel field. terminal count indicates the last byte of transfer, based upon the size of the transfer. for example, on an 8-bit transfer size (size fiel d is 00b), if the tc bit is set, then this is the last byte. on a 16-bit transfer (size fiel d is 01b), if the tc bit is set, then the second byte is the last byte. the peripheral, therefore, must internalize the tc bit when the channel field is communicated, and only signal tc when the last byte of that transfer size has been transferred.
functional description 146 datasheet 5.6.5 verify mode verify mode is supported on the lpc interfac e. a verify transfer to the peripheral is similar to a dma write, where the peripheral is transferring data to main memory. the indication from the host is the same as a dma write, so the peripheral will be driving data onto the lpc interface. however, the ho st will not transfer this data into main memory. 5.6.6 dma request deassertion an end of transfer is communicated to the pch through a special sync field transmitted by the peripheral. an lpc device must not attempt to signal the end of a transfer by deasserting ldreq#. if a dma tran sfer is several bytes (such as, a transfer from a demand mode device) the pch need s to know when to deassert the dma request based on the data currently being transferred. the dma agent uses a sync encoding on each byte of data being transferred, which indicates to the pch whether this is the last byte of transfer or if more bytes are requested. to indicate the last byte of transfer, the peripheral uses a sync value of 0000b (ready with no error), or 1010b (ready with error). these encodings tell the pch that this is the last piece of data transferre d on a dma read (pch to peripheral), or the byte that follows is the last piece of data transferred on a dma write (peripheral to the pch). when the pch sees one of these two encodings, it ends the dma transfer after this byte and deasserts the dma request to the 8237. therefore, if the pch indicated a 16-bit transfer, the peripheral can end the transfer after one byte by indicating a sync value of 0000b or 1010b. the pch does not attempt to transfer the second byte, and deasserts the dma request internally. if the peripheral indicates a 0000b or 1010b sync pattern on the last byte of the indicated size, then the pch only deasserts the dma request to the 8237 since it does not need to end the transfer. if the peripheral wishes to keep the dma request active, then it uses a sync value of 1001b (ready plus more data). this tells the 8237 that more data bytes are requested after the current byte has been transferred, so the pch keeps the dma request active to the 8237. therefore, on an 8-bit transfer size, if the peripheral indicates a sync value of 1001b to the pch, the data will be transferred and the dma request will remain active to the 8237. at a later time, the pch will then come back with another start? cyctype?channel?size etc. combination to initiate another transfer to the peripheral. the peripheral must not assume that the next start indication from the pch is another grant to the peripheral if it had in dicated a sync value of 1001b. on a single mode dma device, the 8237 will re-arbitrate after every transfer. only demand mode dma devices can be assured that they will receive the next start indication from the pch. note: indicating a 0000b or 1010b encoding on th e sync field of an odd byte of a 16-bit channel (first byte of a 16-bit transfer) is an error condition. note: the host stops the transfer on the lpc bus as indicated, fills the upper byte with random data on dma writes (peripheral to memory), and indicates to the 8237 that the dma transfer occurred, incrementing the 8 237?s address and decrementing its byte count.
datasheet 147 functional description 5.6.7 sync field / ldrq# rules since dma transfers on lpc are requested through an ldrq# assertion message, and are ended through a sync field during the dma transfer, the peripheral must obey the following rule when initiating back-t o-back transfers from a dma channel. the peripheral must not assert another message for eight lclks after a deassertion is indicated through the sync field. this is n eeded to allow the 8237, that typically runs off a much slower internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next agent. under default operation, the host only perf orms 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. the method by which this communication between host and peripheral through system bios is performed is beyond the scope of th is specification. sinc e the lpc host and lpc peripheral are motherboard devices, no ?plug-n-play? registry is required. the peripheral must not assume that the host is able to perform transfer sizes that are larger than the size allowed for the dma cha nnel, and be willing to accept a size field that is smaller than what it may currently have buffered. to that end, it is recommended that future devices that may appear on the lpc bus, that require higher bandwidth than 8-bit or 16-bit dma allow, do so with a bus mastering interface and not rely on the 8237. 5.7 8254 timers (d31:f0) the pch contains three counters that have fixed uses. all registers and functions associated with the 8254 timers are in the core well. the 8254 unit is clocked by a 14.31818 mhz clock. counter 0, system timer this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value 1 counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by tw o each counter period. the counter then asserts irq0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating irq0. counter 1, refresh request signal this counter provides the refresh request si gnal and is typically programmed for mode 2 operation and only impacts the period of the ref_toggle bit in port 61. the initial count value is loaded one counter period afte r being written to the counter i/o address. the ref_toggle bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. programming the counter to anything other than mode 2 will result in undefined behavior for the ref_toggle bit. counter 2, speaker tone this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initia l count value. the speaker must be enabled by a write to port 061h (see nmi status and control ports).
functional description 148 datasheet 5.7.1 timer programming the counter/timers are programmed in the following fashion: 1. write a control word to select a counter. 2. write an initial count for that counter. 3. load the least and/or most significant bytes (as required by control word bits 5, 4) of the 16-bit counter. 4. repeat with other counters. only two conventions need to be observed when programming the counters. first, for each counter, the control word must be written before the initial count is written. second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). a new initial count may be written to a counter at any time without affecting the counter's programmed mode. counting is affect ed as described in the mode definitions. the new count must follow the programmed count format. if a counter is programmed to read/write two-byte counts, the following precaution applies: a program must not transfer contro l between writing the first and second byte to another routine which also writes into that same counter. otherwise, the counter will be loaded with an incorrect count. the control word register at port 43h controls the operation of all three counters. several commands are available: ? control word command. specifies which counter to read or write, the operating mode, and the count format (binary or bcd). ? counter latch command. latches the current count so that it can be read by the system. the countdown process continues. ? read back command. reads the count value, programmed mode, the current state of the out pins, and the state of the null count flag of the selected counter. ta b l e 5 - 1 2 lists the six operating modes for the interval counters. table 5-12. counter operating modes mode function description 0 out signal on end of count (=0) output is 0. when count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. 1 hardware retriggerable one-shot output is 0. when count goes to 0, output goes to 1 for one clock time. 2 rate generator (divide by n counter) output is 1. output goes to 0 for one clock time, then back to 1 and counter is reloaded. 3square wave output output is 1. output goes to 0 when counter rolls over, and counter is relo aded. output goes to 1 when counter rolls over, and counter is reloaded, etc. 4 software triggered strobe output is 1. output goes to 0 when count expires for one clock time. 5 hardware triggered strobe output is 1. output goes to 0 when count expires for one clock time.
datasheet 149 functional description 5.7.2 reading from the interval timer it is often desirable to read the value of a counter without disturbing the count in progress. there are three methods for reading the counters: a simple read operation, counter latch command, and the read-back command. each is explained below. with the simple read and counter latch co mmand methods, the count must be read according to the programmed format; specifica lly, if the counter is programmed for two byte counts, two bytes must be read. the tw o bytes do not have to be read one right after the other. read, write, or programmi ng operations for other counters may be inserted between them. 5.7.2.1 simple read the first method is to perform a simple read operation. the counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). note: performing a direct read from the counter does not return a determinate value, because the counting process is asynchronous to read operations. however, in the case of counter 2, the count can be stopped by writing to the gate bit in port 61h. 5.7.2.2 counter latch command the counter latch command, written to port 43h, latches the count of a specific counter at the time the command is received. this command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. the count value is then read from each counter?s count register as was programmed by the control register. the count is held in the latch until it is re ad or the counter is reprogrammed. the count is then unlatched. this allows reading the contents of the counters on the fly without affecting counting in progress. multiple co unter latch commands may be used to latch more than one counter. counter latch comma nds do not affect the programmed mode of the counter in any way. if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read is the count at the time the first counter latch command was issued. 5.7.2.3 read back command the read back command, written to port 43h, latches the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the value of the counter and its status may then be read by i/o access to the counter address. the read back command may be used to latch multiple counter outputs at one time. this single command is functionally equivalent to several counter latch commands, one for each counter latched. each counter's la tched count is held until it is read or reprogrammed. once read, a counter is unlatched. the other counters remain latched until they are read. if multiple count read back commands are issued to the same counter without reading the count, all but the first are ignored. the read back command may additionally be used to latch status information of selected counters. the status of a counter is accessed by a read from that counter's i/o port address. if multiple counter status latch operations are performed without reading the status, all but the first are ignored.
functional description 150 datasheet both count and status of the selected counters may be latched simultaneously. this is functionally the same as issuing two consecutive, separate read back commands. if multiple count and/or status read back commands are issued to the same counters without any intervening reads, all but the first are ignored. if both count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latched first. the next one or two reads, depending on whether the co unter is programmed for one or two type counts, returns the latched count. subsequent reads return unlatched count. 5.8 8259 interrupt controllers (pic) (d31:f0) the pch incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the isa compatible interrupts. these interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, mouse, and dma channels. in addition, this interrupt contro ller can support the pci based interrupts, by mapping the pci interrupt onto the compat ible isa interrupt line. each 8259 core supports eight interrupts, numbered 0?7. ta b l e 5 - 1 3 shows how the cores are connected. the pch cascades the slave controller onto the master controller through master controller interrupt input 2. this means there are only 15 possible interrupts for the pch pic. table 5-13. interrupt controller core connections 8259 8259 input typical interrupt source connected pin / function master 0 internal internal timer / counter 0 output / hpet #0 1 keyboard irq1 using serirq 2 internal slave controller intr output 3 serial port a irq3 using serirq, pirq# 4 serial port b irq4 using serirq, pirq# 5 parallel port / generic i rq5 using serirq, pirq# 6 floppy disk irq6 using serirq, pirq# 7 parallel port / generic i rq7 using serirq, pirq# slave 0 internal real time clock internal rtc / hpet #1 1 generic irq9 using serirq, sci, tco, or pirq# 2 generic irq10 using serirq, sci, tco, or pirq# 3generic irq11 using serirq, sci, tco, or pirq#, or hpet #2 4ps/2 mouse irq12 using serirq, sci, tco, or pirq#, or hpet #3 5internal state machine output based on processor ferr# assertion. may optionally be used for sci or tco interrupt if ferr# not needed. 6sata sata primary (legacy mode), or using serirq or pirq# 7sata sata secondary (legacy mode) or using serirq or pirq#
datasheet 151 functional description interrupts can individually be programmed to be edge or level, except for irq0, irq2, irq8#, and irq13. note: active-low interrupt sources (such as, the pi rq#s) are inverted inside the pch. in the following descriptions of the 8259s, the interru pt levels are in reference to the signals at the internal interface of the 8259s, afte r the required inversions have occurred. therefore, the term ?high? indicates ?act ive,? which means ?low? on an originating pirq#. 5.8.1 interrupt handling 5.8.1.1 generating interrupts the pic interrupt sequence involves three bi ts, from the irr, isr, and imr, for each interrupt level. these bits are used to determine the interrupt vector returned, and status of any other pending interrupts. ta b l e 5 - 1 4 defines the irr, isr, and imr. 5.8.1.2 acknowledging interrupts the processor generates an interrupt acknowledge cycle that is translated by the host bridge into a pci interrupt acknowledge cycle to the pch. the pic translates this command into two internal inta# pulses expe cted by the 8259 cores. the pic uses the first internal inta# pulse to freeze the state of the interrupts for priority resolution. on the second inta# pulse, the master or slave sends the interrupt vector to the processor with the acknowledged interrupt code . this code is based upon bits [7:3] of the corresponding icw2 register, combined wi th three bits representing the interrupt within that controller. table 5-14. interrupt status registers bit description irr interrupt request register. this bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. this bit is set whether or not the interrupt is masked. however, a ma sked interrupt will not generate intr. isr interrupt service register. this bit is set, and the co rresponding irr bit cleared, when an interrupt acknowledge cycle is seen, and the vect or returned is for that interrupt. imr interrupt mask register. this bit determines whethe r an interrupt is masked. masked interrupts will not generate intr. table 5-15. content of interrupt vector byte master, slave interrupt bits [7:3] bits [2:0] irq7,15 icw2[7:3] 111 irq6,14 110 irq5,13 101 irq4,12 100 irq3,11 011 irq2,10 010 irq1,9 001 irq0,8 000
functional description 152 datasheet 5.8.1.3 hardware/software interrupt sequence 1. one or more of the interrupt request lines (irq) are raised high in edge mode, or seen high in level mode, setting the corresponding irr bit. 2. the pic sends intr active to the processor if an asserted interrupt is not masked. 3. the processor acknowledges the intr and responds with an interrupt acknowledge cycle. the cycle is translated into a pc i interrupt acknowledge cycle by the host bridge. this command is broadcast over pci by the pch. 4. upon observing its own interrupt acknowle dge cycle on pci, the pch converts it into the two cycles that the internal 8259 pair can respond to. each cycle appears as an interrupt acknowledge pulse on the internal inta# pin of the cascaded interrupt controllers. 5. upon receiving the first internally generated inta# pulse, the highest priority isr bit is set and the corresponding irr bit is reset. on the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. the slave controller uses these bits to determine if it must respond with an interrupt vector during the second inta# pulse. 6. upon receiving the second internally ge nerated inta# pulse, the pic returns the interrupt vector. if no interrupt request is present because the request was too short in duration, the pic returns vector 7 from the master controller. 7. this completes the interrupt cycle. in aeoi mode the isr bit is reset at the end of the second inta# pulse. otherwise, the isr bit remains set until an appropriate eoi command is issued at the end of the interrupt subroutine. 5.8.2 initialization command words (icwx) before operation can begin, each 8259 must be initialized. in the pch, this is a four byte sequence. the four initialization command words are referred to by their acronyms: icw1, icw2, icw3, and icw4. the base address for each 8259 initialization command word is a fixed location in the i/o memory space: 20h for the master controller, and a0h for the slave controller. 5.8.2.1 icw1 an i/o write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to icw1. upon sensin g this write, the pch?s pic expects three more byte writes to 21h for the master controller, or a1h for the slave controller, to complete the icw sequence. a write to icw1 starts the initialization sequence during which the following automatically occur: 1. following initialization, an interrupt re quest (irq) input must make a low-to-high transition to generate an interrupt. 2. the interrupt mask register is cleared. 3. irq7 input is assigned priority 7. 4. the slave mode address is set to 7. 5. special mask mode is cleared and status read is set to irr.
datasheet 153 functional description 5.8.2.2 icw2 the second write in the sequence (icw2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. a different base is selected for each interrupt controller. 5.8.2.3 icw3 the third write in the sequence (icw3) has a different meaning for each controller. ? for the master controller, icw3 is used to indicate which irq input line is used to cascade the slave controller. within the pch, irq2 is used. therefore, bit 2 of icw3 on the master controller is set to a 1, and the other bits are set to 0s. ? for the slave controller, icw3 is the slave identification code used during an interrupt acknowledge cycle. on interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. the slave controller compares this identification code to the value stored in its icw3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 5.8.2.4 icw4 the final write in the sequence (icw4) must be programmed for both controllers. at the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an intel architecture-based system. 5.8.3 operation command words (ocw) these command words reprogram the interrupt controller to operate in various interrupt modes. ? ocw1 masks and unmasks interrupt lines. ? ocw2 controls the rotation of interrupt pr iorities when in rotating priority mode, and controls the eoi function. ? ocw3 sets up isr/irr reads, enables/disables the special mask mode (smm), and enables/disables polled interrupt mode. 5.8.4 modes of operation 5.8.4.1 fully nested mode in this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest. when an interrupt is acknow ledged, the highest priority request is determined and its vector placed on the bus. additionally, the isr for the interrupt is set. this isr bit remains set until: the processor issues an eoi command immediately before returning from the service routine; or if in aeoi mode, on the trailing edge of the second inta#. while the isr bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels ge nerate another interrupt. interrupt priorities can be changed in the rotating priority mode.
functional description 154 datasheet 5.8.4.2 special fully-nested mode this mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. in this case, the special fully-nested mode is programmed to the master controller. this mode is similar to the fully-nested mode with the following exceptions: ? when an interrupt request from a certain slav e is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave are recognized by the master and initiate interrupts to the processor. in the normal-nested mode, a slave is masked out when its request is in service. ? when exiting the interrupt service routine, software has to check whether the interrupt serviced was the only one from that slave. this is done by sending a non- specific eoi command to the slave and then reading its isr. if it is 0, a non- specific eoi can also be sent to the master. 5.8.4.3 automatic rotation mo de (equal priority devices) in some applications, there are a number of interrupting devices of equal priority. automatic rotation mode provides for a sequential 8-way rotation. in this mode, a device receives the lowest priority after being serviced. in the worst case, a device requesting an interrupt has to wait until each of seven other devices are serviced at most once. there are two ways to accomplish automatic rotation using ocw2; the rotation on non-specific eoi command (r=1, sl=0, eoi=1) and the rotate in automatic eoi mode which is set by (r=1, sl=0, eoi=0). 5.8.4.4 specific rotation mode (specific priority) software can change interrupt priorities by programming the bottom priority. for example, if irq5 is programmed as the bottom priority device, then irq6 is the highest priority device. the set priority command is issued in ocw2 to accomplish this, where: r=1, sl=1, and lo?l2 is the binary priority level code of the bottom priority device. in this mode, internal status is updated by software control during ocw2. however, it is independent of the eoi command. priority changes can be executed during an eoi command by using the rotate on specific eoi command in ocw2 (r=1, sl=1, eoi=1 and lo?l2=irq level to receive bottom priority. 5.8.4.5 poll mode poll mode can be used to conserve space in the interrupt vector table. multiple interrupts that can be serviced by one inte rrupt service routine do not need separate vectors if the service routine uses the poll command. poll mode can also be used to expand the number of interrupts. the polling interrupt service routine can call the appropriate service routine, instead of prov iding the interrupt vectors in the vector table. in this mode, the intr output is not used and the microprocessor internal interrupt enable flip-flop is reset, disabling its interrupt input. service to devices is achieved by software using a poll command. the poll command is issued by setting p=1 in ocw3. the pic treats its next i/o read as an interrupt acknowledge, sets the appropriate isr bit if there is a request, and reads the priority level. interrupts are frozen from the ocw3 write to the i/o read. the byte returned during the i/o read contains a 1 in bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0.
datasheet 155 functional description 5.8.4.6 cascade mode the pic in the pch has one master 8259 and one slave 8259 cascaded onto the master through irq2. this configuration can handle up to 15 separate priority levels. the master controls the slaves through a three bit internal bus. in the pch, when the master drives 010b on this bus, the slave controller takes responsibility for returning the interrupt vector. an eoi command must be issued twice: once for the master and once for the slave. 5.8.4.7 edge and level triggered mode in isa systems this mode is programmed using bit 3 in icw1, which sets level or edge for the entire controller. in the pch, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. this is the edge/level control registers elcr1 and elcr2. if an elcr bit is 0, an interrupt request w ill be recognized by a low-to-high transition on the corresponding irq input. the irq input can remain high without generating another interrupt. if an elcr bit is 1, an in terrupt request will be recognized by a high level on the corresponding irq input and ther e is no need for an edge detection. the interrupt request must be removed before the eoi command is issued to prevent a second interrupt from occurring. in both the edge and level triggered modes, the irq inputs must remain active until after the falling edge of the first internal inta#. if the irq input goes inactive before this time, a default irq7 vector is returned. 5.8.4.8 end of interrupt (eoi) operations an eoi can occur in one of two fashions: by a command word write issued to the pic before returning from a service routine, the eoi command; or automatically when aeoi bit in icw4 is set to 1. 5.8.4.9 normal end of interrupt in normal eoi, software writes an eoi co mmand before leaving the interrupt service routine to mark the interrupt as complete d. there are two forms of eoi commands: specific and non-specific. when a non-specific eoi command is issued, the pic clears the highest isr bit of those that are set to 1. non-specif ic eoi is the normal mode of operation of the pic within the pch, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. when the pic is operated in modes that preserve the fully nested structure, softwa re can determine which isr bit to clear by issuing a specific eoi. an isr bit that is ma sked is not cleared by a non-specific eoi if the pic is in the special mask mode. an eoi command must be issued for both the master and slave controller. 5.8.4.10 automatic end of interrupt mode in this mode, the pic automatically performs a non-specific eoi operation at the trailing edge of the last interrupt acknowle dge pulse. from a system standpoint, this mode should be used only when a nested mu lti-level interrupt structure is not required within a single pic. the aeoi mode can only be used in the master controller and not the slave controller.
functional description 156 datasheet 5.8.5 masking interrupts 5.8.5.1 masking on an indi vidual interrupt request each interrupt request can be masked individually by the interrupt mask register (imr). this register is programmed through ocw1. each bit in the imr masks one interrupt channel. masking irq2 on the master controller masks all requests for service from the slave controller. 5.8.5.2 special mask mode some applications may require an interrupt service routine to dynamically alter the system priority structure during its executio n under software control. for example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. the special mask mode enables all interrupts not masked by a bit set in the mask register. normally, when an interrupt servic e routine acknowledges an interrupt without issuing an eoi to clear the isr bit, the interrupt controller inhibits all lower priority requests. in the special mask mode, any interrupts may be selectively enabled by loading the mask register with the appropri ate pattern. the special mask mode is set by ocw3 where: ssmm=1, smm=1, and cleared where ssmm=1, smm=0. 5.8.6 steering pci interrupts the pch can be programmed to allow pirqa# -pirqh# to be routed internally to interrupts 3?7, 9?12, 14 or 15. the assign ment is programmable through the pirqx route control registers, located at 60?63h and 68?6bh in device 31:function 0. one or more pirqx# lines can be routed to the same irqx input. if interrupt steering is not required, the route registers can be programmed to disable steering. the pirqx# lines are defined as active low, level sensitive to allow multiple interrupts on a pci board to share a single line across the connector. when a pirqx# is routed to specified irq line, software must change the irq's corresponding elcr bit to level sensitive mode. the pch internal ly inverts the pirqx# line to send an active high level to the pic. when a pci interrupt is routed onto the pic, the selected irq can no longer be used by an active high device (through serirq). however, active low interrupts can share their interrupt with pci interrupts. internal sources of the pirqs, including sci and tco interrupts, cause the external pirq to be asserted. the pch receives the pirq input, like all of the other external sources, and routes it accordingly.
datasheet 157 functional description 5.9 advanced programmable interrupt controller (apic) (d31:f0) in addition to the standard isa-compatible pic described in the previous chapter, the pch incorporates the apic. while the standard interrupt controller is intended for use in a uni-processor system, apic can be used in either a uni-processor or multi- processor system. 5.9.1 interrupt handling the i/o apic handles interrupts very diff erently than the 8259. briefly, these differences are: ? method of interrupt transmission. the i/o apic transmits interrupts through memory writes on the normal data path to the processor, and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. ? interrupt priority. the priority of interrupts in th e i/o apic is independent of the interrupt number. for example, interrupt 10 can be given a higher priority than interrupt 3. ? more interrupts. the i/o apic in the pch supports a total of 24 interrupts. ? multiple interrupt controllers. the i/o apic architecture allows for multiple i/o apic devices in the system with their own interrupt vectors. 5.9.2 interrupt mapping the i/o apic within the pch supports 24 ap ic interrupts. each interrupt has its own unique vector assigned by software. the interrupt vectors are mapped as follows, and match ?config 6? of the multi-processor specification . table 5-16. apic interrupt mapping 1 (sheet 1 of 2) irq # using serirq direct from pin using pci message internal modules 0 no no no cascade from 8259 #1 1yes no yes 2 no no no 8254 counter 0, hpet #0 (legacy mode) 3yes no yes 4yes no yes 5yes no yes 6yes no yes 7yes no yes 8no no nortc, hpet #1 (legacy mode) 9 yes no yes option for sci, tco 10 yes no yes option for sci, tco 11 yes no yes hpet #2, option for sci, tco (note2) 12 yes no yes hpet #3 (note 3) 13 no no no ferr# logic 14 yes no yes sata primary (legacy mode) 15 yes no yes sata secondary (legacy mode)
functional description 158 datasheet notes: 1. when programming the polarity of internal interrupt sour ces on the apic, interrupts 0 through 15 receive active-high internal interrupt sources, wh ile interrupts 16 through 23 receive active-low inte rnal interrupt sources. 2. if irq 11 is used for hpet #2, software shou ld ensure irq 11 is not shared with any other devices to ensure the proper operation of hpet #2. the pch hardware does not prevent sharing of irq 11. 3. if irq 12 is used for hpet #3, software shou ld ensure irq 12 is not shared with any other devices to ensure the proper operation of hpet #3. the pch hardware does not prevent sharing of irq 12. 4. pirq[e:h] are multiplexed with gpio pins. interrupts pirq[e:h] will not be exposed if they are configured as gpios. 5.9.3 pci / pci express* message-based interrupts when external devices through pci/pci expre ss wish to generate an interrupt, they will send the message defined in the pci express* base specification, revision 1.0a for generating inta# ? intd#. these will be tran slated internal assertions/deassertions of inta# ? intd#. 5.9.4 ioxapic address remapping to support intel ? virtualization technology, interrupt messages are required to go through similar address remapping as any other memory request. address remapping allows for domain isolation for interrupts, so a device assigned in one domain is not allowed to generate an interrupt to another domain. the address remapping is based on the bus: device: function field associated with the requests. the internal apic is required to initiate the interrupt message using a unique bus: device: function. the pch allows bios to program the uniqu e bus: device: function address for the internal apic. this address field does not ch ange the apic functionality and the apic is not promoted as a stand-alone pci device. see device 31: function 0 offset 6ch for additional information. 5.9.5 external interrupt controller support the pch supports external ap ics off of pci express ports but does not support apics on the pci bus. the eoi special cycle is only forwarded to pci express ports. 16 pirqa# pirqa# yes internal devices are routable; see section 10.1.20 though section 10.1.34 . 17 pirqb# pirqb# 18 pirqc# pirqc# 19 pirqd# pirqd# 20 n/a pirqe# 4 yes option for sci, tco, hpet #0,1,2, 3. other internal devices are routable; see section 10.1.20 though section 10.1.34 . 21 n/a pirqf# 4 22 n/a pirqg# 4 23 n/a pirqh# 4 table 5-16. apic interrupt mapping 1 (sheet 2 of 2) irq # using serirq direct from pin using pci message internal modules
datasheet 159 functional description 5.10 serial interrupt (d31:f0) the pch supports a serial irq scheme. this allows a single signal to be used to report interrupt requests. the signal used to transm it this information is shared between the host, the pch, and all peripherals that support serial interrupts. the signal line, serirq, is synchronous to pci clock, and follows the sustained tri-state protocol that is used by all pci signals. this means that if a device has driven serirq low, it will first drive it high synchronous to pci clock and release it the following pci clock. the serial irq protocol defines this sustained tri-state signaling in the following fashion: ? s C sample phase. signal driven low ? r ? recovery phase. signal driven high ? t ? turn-around phase. signal released the pch supports a message for 21 serial interrupts. these represent the 15 isa interrupts (irq0?1, 2?15), the four pci inte rrupts, and the control signals smi# and iochk#. the serial irq protocol does no t support the additional apic interrupts (20?23). note: when the sata controller is configured for legacy ide mode, irq14 and irq15 are expected to behave as isa legacy interrupts that cannot be shared (that is, through the serial interrupt pin). if irq14 and irq15 ar e shared with serial interrupt pin then abnormal system behavior may occur. for ex ample, irq14/15 may not be detected by the pch's interrupt controller. when the sata controller is not running in native ide mode, irq14 and irq15 are used as special interrupts. if the sata controller is in native mode, these interrupts can be mapped to other devices accordingly. 5.10.1 start frame the serial irq protocol has two modes of operation which affect the start frame. these two modes are: continuous, where the pch is solely responsible for generating the start frame; and quiet, where a serial irq peripheral is responsible for beginning the start frame. the mode that must first be entered when enabling the serial irq protocol is continuous mode. in this mode, the pch assert s the start frame. this start frame is 4, 6, or 8 pci clocks wide based upon the serial irq control register, bits 1:0 at 64h in device 31:function 0 configuration space. this is a polling mode. when the serial irq stream enters quiet mode (signaled in the stop frame), the serirq line remains inactive and pulled up between the stop and start frame until a peripheral drives the serirq signal low. the pch senses the line low and continues to drive it low for the remainder of the start frame. since the first pci clock of the start frame was driven by the peripheral in this mode, the pch drives the serirq line low for 1 pci clock less than in continuous mode. th is mode of operation allows for a quiet, and therefore lower power, operation.
functional description 160 datasheet 5.10.2 data frames once the start frame has been initiated, all of the serirq peripherals must start counting frames based on the rising edge of serirq. each of the irq/data frames has exactly 3 phases of 1 clock each: ? sample phase. during this phase, the serirq device drives serirq low if the corresponding interrupt signal is low. if the corresponding interrupt is high, then the serirq devices tri-state the serirq signal. the serirq line remains high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). a low le vel during the irq0?1 and irq2?15 frames indicates that an active-high isa interrupt is not being requested, but a low level during the pci int[a:d], smi#, and iochk# frame indicates that an active-low interrupt is being requested. ? recovery phase. during this phase, the device drives the serirq line high if in the sample phase it was driven low. if it was not driven in the sample phase, it is tri-stated in this phase. ? turn-around phase. the device tri-states the serirq line 5.10.3 stop frame after all data frames, a stop frame is driven by the pch. the serirq signal is driven low by the pch for 2 or 3 pci clocks. the number of clocks is determined by the serirq configuration register. the number of clocks determines the next mode. 5.10.4 specific interrupts not supported using serirq there are three interrupts seen through the se rial stream that are not supported by the pch. these interrupts are generated internally , and are not sharable with other devices within the system. these interrupts are: ? irq0. heartbeat interrupt generated off of the internal 8254 counter 0. ? irq8#. rtc interrupt can only be generated internally. ? irq13. floating point error interrupt gene rated off of the processor assertion of ferr#. the pch ignores the state of th ese interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream. table 5-17. stop frame explanation stop frame width next mode 2 pci clocks quiet mode. any serirq device may initiate a start frame 3 pci clocks continuous mode. only the host (the pch) may initiate a start frame
datasheet 161 functional description 5.10.5 data frame format ta b l e 5 - 1 8 shows the format of the data frames. for the pci interrupts (a?d), the output from the pch is and?d with the pci input signal. this way, the interrupt can be signaled using both the pci interrupt input signal and using the serirq signal (they are shared). table 5-18. data frame format data frame # interrupt clocks past start frame comment 1irq0 2 ignored. irq0 can only be generated using the internal 8524 2irq1 5 3 smi# 8 causes smi# if low. wi ll set the serirq_smi_sts bit. 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23 9 irq8 26 ignored. irq8# can only be generated internally. 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 ignored. irq13 can on ly be generated from ferr# 15 irq14 44 not attached to sata logic 16 irq15 47 not attached to sata logic 17 iochck# 50 same as isa iochck# going active. 18 pci inta# 53 drive pirqa# 19 pci intb# 56 drive pirqb# 20 pci intc# 59 drive pirqc# 21 pci intd# 62 drive pirqd#
functional description 162 datasheet 5.11 real time clock (d31:f0) the real time clock (rtc) module provides a battery backed-up date and time keeping device with two banks of static ram with 128 bytes each, although the first bank has 114 bytes for general purpose usage. three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 s to 500 ms, and end of update cycle notification. seconds, minutes, hours, days, day of week, month, and year are counted. daylight savings compensation is no longer supported. the hour is represented in twelve or twenty-four hour format, and data can be represented in bcd or binary format. the design is functionally compatible with the motorola ms146818b. the time keeping come s from a 32.768 khz oscillating source, which is divided to achieve an update ev ery second. the lower 14 bytes on the lower ram block has very specific functions. the fi rst ten are for time and date information. the next four (0ah to 0dh) are registers, which configure and report rtc functions. the time and calendar data should match the data mode (bcd or binary) and hour mode (12 or 24 hour) as selected in regist er b. it is up to the programmer to make sure that data stored in these locations is within the reasonable values ranges and represents a possible date and time. the exception to these ranges is to store a value of c0?ffh in the alarm bytes to indicate a don?t care situation. all alarm conditions must match to trigger an alarm flag, which co uld trigger an alarm interrupt if enabled. the set bit must be 1 while programming these locations to avoid clashes with an update cycle. access to time and date inform ation is done through the ram locations. if a ram read from the ten time and date bytes is attempted during an update cycle, the value read do not necessarily represent the true contents of those locations. any ram writes under the same conditions are ignored. note: the leap year determination for adding a 29th day to february does not take into account the end-of-the-century exceptions. the logic simply assumes that all years divisible by 4 are leap years. according to the royal observatory greenwich, years that are divisible by 100 are typically not leap year s. in every fourth century (years divisible by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. note that the year 2100 will be the first time in which the current rtc implementation would incorrectly calculate the leap-year. the pch does not implement month/year alarms. 5.11.1 update cycles an update cycle occurs once a second, if th e set bit of register b is not asserted and the divide chain is properly configured. during this procedure, the stored time and date are incremented, overflow is checked, a ma tching alarm condition is checked, and the time and date are rewritten to the ram locations. the update cycle will start at least 488 s after the uip bit of register a is asserted, and the entire cycle does not take more than 1984 s to complete. the time and date ram locations (0?9) are disconnected from the external bus during this time. to avoid update and data corruption conditions, external ram access to these locations can safely occur at two times. when a updated-ended interrupt is detected, almost 999 ms is available to read and write the va lid time and date data. if the uip bit of register a is detected to be low, there is at least 488 s before the update cycle begins. warning: the overflow conditions for leap years adjustments are based on more than one date or time item. to ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before leap year occurs.
datasheet 163 functional description 5.11.2 interrupts the real-time clock interrupt is internally routed within the pch both to the i/o apic and the 8259. it is mapped to interrupt vector 8. this interrupt does not leave the pch, nor is it shared with any other interrupt. irq8# from the serirq stream is ignored. however, the high performance event timers can also be mapped to irq8#; in this case, the rtc interrupt is blocked. 5.11.3 lockable ram ranges the rtc battery-backed ram supports two 8-byte ranges that can be locked using the configuration space. if the locking bits are set, the corresponding range in the ram will not be readable or writable. a write cycle to those locations will have no effect. a read cycle to those locations will not return the location?s actual value (resultant value is undefined). once a range is locked, the range can be unlocked only by a hard reset, which will invoke the bios and allow it to relock the ram range. 5.11.4 century rollover the pch detects a rollover when the year by te (rtc i/o space, index offset 09h) transitions form 99 to 00. upon detecting the rollover, the pch sets the newcentury_sts bit (tcobase + 04h, bit 7). if the system is in an s0 state, this causes an smi#. the smi# handler can update registers in the rtc ram that are associated with century value. if the system is in a sleep state (s1?s5) when the century rollover occurs, the pch also sets the newcentury_sts bit, but no smi# is generated. when the system resumes from the sleep state, bios should check the newcentury_sts bit and update the century value in the rtc ram. 5.11.5 clearing battery-backed rtc ram clearing cmos ram in a pch-based platform can be done by using a jumper on rtcrst# or gpi. implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. using rtcrst# to clear cmos a jumper on rtcrst# can be used to clear cmos values, as well as reset to default, the state of those configuration bits that reside in the rtc power well. when the rtcrst# is strapped to ground, the rtc_pw r_sts bit (d31:f0:a4h bit 2) will be set and those configuration bits in the rtc power well will be set to their default state. bios can monitor the state of this bit, and manually clear the rtc cmos array once the system is booted. the normal position would cause rtcrst# to be pulled up through a weak pull-up resistor. ta b l e 5 - 1 9 shows which bits are set to their default state when rtcrst# is asserted. this rtcrst# jumper technique allows the jumper to be moved and then replaced?all while the system is powered off. then, once booted, the rtc_pwr_sts can be detected in the set state.
functional description 164 datasheet using a gpi to clear cmos a jumper on a gpi can also be used to clear cmos values. bios would detect the setting of this gpi on system boot-up, and manually clear the cmos array. note: the gpi strap technique to clear cmos requ ires multiple steps to implement. the system is booted with the jumper in ne w position, then powered back down. the jumper is replaced back to the normal position, then the system is rebooted again. warning: do not implement a jumper on vccrtc to clear cmos. table 5-19. configuration bits reset by rtcrst# assertion bit name register location bit(s) default state alarm interrupt enable (aie) register b (general configuration) (rtc_regb) i/o space (rtc index + 0bh) 5x alarm flag (af) register c (flag register) (rtc_regc) i/o space (rtc index + 0ch) 5x swsmi_rate_sel general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 7:6 0 slp_s4# minimum assertion width general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 5:4 0 slp_s4# assertion stretch enable general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 3 0 rtc power status (rtc_pwr_sts) general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 2 0 power failure (pwr_flr) general pm configuration 3 register (gen_pmcon_3) d31:f0:a4h 1 0 afterg3_en general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 0 0 power button override status (prbtnor_sts) power management 1 status register (pm1_sts) pmbase + 00h 11 0 rtc event enable (rtc_en) power management 1 enable register (pm1_en) pmbase + 02h 10 0 sleep type (slp_typ) power management 1 control (pm1_cnt) pmbase + 04h 12:10 0 pme_en general purpose event 0 enables register (gpe0_en) pmbase + 2ch 11 0 batlow_en general purpose event 0 enables register (gpe0_en) pmbase + 2ch 10 0 ri_en general purpose event 0 enables register (gpe0_en) pmbase + 2ch 8 0 newcentury_st s tco1 status register (tco1_sts) tcobase + 04h 7 0 intruder detect (intrd_det) tco2 status register (tco2_sts) tcobase + 06h 0 0 to p swa p ( ts ) backed up control register (buc) chipset config registers:offset 3414h 0x
datasheet 165 functional description 5.12 processor interface (d31:f0) the pch interfaces to the processor with following pin-based signals other than dmi: ? standard outputs to processor: procpwrgd, pmsynch, peci ? standard input from processor: thrmtrip# most pch outputs to the processor use standard buffers. the pch has separate v_proc_io signals that are pulled up at the system level to the processor voltage, and thus determines voh for the outputs to the processor. the following processor interface lega cy pins were removed from the pch: ? ignne#, stpclk#, dpslp#, are dprslpvr are no longer required on pch based systems. ? a20m#, smi#, nmi, init#, intr, ferr#: f unctionality has been replaced by in- band virtual legacy wire (vlw) messages. see section 5.12.3 . 5.12.1 processor interface signals and vlw messages this section describes each of the signals that interface between the pch and the processor(s). note that the behavior of some signals may vary during processor reset, as the signals are used for frequency strapping. 5.12.1.1 a20m# (mask a20) / a20gate the a20m# vlw message is asserted when both of the following conditions are true: ? the alt_a20_gate bit (bit 1 of port92 register) is a 0 ? the a20gate input signal is a 0 the a20gate input signal is expected to be generated by the external microcontroller (kbc).
functional description 166 datasheet 5.12.1.2 init (initialization) the init# vlw message is asserted based on any one of several events described in ta b l e 5 - 2 0 . when any of these events occur, init# is asserted for 16 pci clocks, then driven high. note: init3_3v# is functionally identical to init# vlw but it is a physical signal at 3.3 v on desktop skus only. 5.12.1.3 ferr# (numeric coprocessor error) the pch supports the coprocessor error function with the ferr# message. the function is enabled using the coproc_err_en bit. if ferr# is driven active by the processor, irq13 goes active (internally). when it detects a write to the coproc_err register (i/o register f0h), the pch nega tes the internal irq1 3 and ignne# will be active. ignne# remains active until ferr# is driven inactive. ignne# is never driven active unless ferr# is active. note: ignne# (ignore numeric error is now internally generated by the processor. table 5-20. init# going active cause of init3_3v# going active comment shutdown special cycle from processor observed on pch-processor interconnect. init assertion based on value of shutdown policy select register (sps) port92 write, where init_now (bit 0) transitions from a 0 to a 1. portcf9 write, where sys_rst (bit 1) was a 0 and rst_cpu (bit 2) transitions from 0 to 1. rcin# input signal goes low. rcin# is expected to be driven by the external microcontroller (kbc). 0 to 1 transition on rcin# must occur before the pch will arm init3_3v# to be generated again. note: rcin# signal is expected to be low during s3, s4, and s5 states. transition on the rcin# signal in those states (or the transition to those states) may not necessarily cause the init3_3v# signal to be generated to the processor. processor bist to enter bist, software sets cpu_bist_en bit and then does a full processor reset using the cf9 register.
datasheet 167 functional description 5.12.1.4 nmi (non-maskable interrupt) non-maskable interrupts (nmis) can be genera ted by several sources, as described in ta b l e 5 - 2 1 . 5.12.1.5 processor power good (procpwrgd) this signal is connected to the processo r?s uncorepwrgood input to indicate when the processor power is valid. 5.12.2 dual-proce ssor issues 5.12.2.1 usage differences in dual-processor designs, some of the processor signals are unused or used differently than for uniprocessor designs. ? a20m#/a20gate and ferr# are generally not used, but still supported. ? i/o apic and smi# are assumed to be used. 5.12.3 virtual legacy wire (vlw) messages the pch supports vlw messages as alternative method of conveying the status of the following legacy sideband interface signals to the processor: ? a20m#, intr, smi#, init#, nmi note: ignne# vlw message is not required to be ge nerated by the pch as it is internally emulated by the processor. vlw are inbound messages to the processor. they are communicated using vendor defined message over the dmi link. legacy processor signals can only be deliv ered using vlw in the pch. delivery of legacy processor signals (a20m#, intr, smi# , init# or nmi) using i/o apic controller is not supported. table 5-21. nmi sources cause of nmi comment serr# goes active (either internally, externally using serr# signal, or using message from processor) can instead be routed to generate an sci, through the nmi2sci_en bit (device 31:function 0, tco base + 08h, bit 11). iochk# goes active using serirq# stream (isa system error) can instead be routed to generate an sci, through the nmi2sci_en bit (device 31:function 0, tco base + 08h, bit 11). secsts register device 31: function f0 offset 1eh, bit 8. this is enabled by the parity error response bit (per) at device 30: func tion 0 offset 04, bit 6. dev_sts register device 31:function f0 offset 06h, bit 8 this is enabled by the parity error response bit (per) at device 30: func tion 0 offset 04, bit 6. gpio[15:0] when configured as a general purpose input and routed as nmi (by gpio_rout at device 31: function 0 offset b8) this is enabled by gpi nmi enable (gpi_nmi_en) bits at device 31: function 0 offset: gpiobase + 28h bits 15:0
functional description 168 datasheet 5.13 power management 5.13.1 features ? support for advanced configuration and power interface, version 4.0a (acpi) providing power and thermal management ? acpi 24-bit timer sci and smi# generation ? pci pme# signal for wake up from low-power states ? system sleep state control ? acpi s3 state ? suspend to ram (str) ? acpi s4 state ? suspend-to-disk (std) ? acpi g2/s5 state ? soft off (soff) ? power failure detection and recovery ? deep s4/s5 ?intel ? management engine power management support ? wake events from the intel management engine (enabled from all s-states including catastrophic s5 conditions) 5.13.2 pch and system power states ta b l e 5 - 2 2 shows the power states defined for pch-based platforms. the state names generally match the corresponding acpi states. table 5-22. general power states for systems using the pch (sheet 1 of 2) state/ substates legacy name / description g0/s0/c0 full on: processor operating. individual devi ces may be shut down or be placed into lower power states to save power. g0/s0/cx cx state: cx states are processor power states within the s0 system state that provide for various levels of power saving s. the processor initiates c-state entry and exit while interacting with the pch. the pch will base its behavior on the processor state. g1/s1 s1: the pch provides the s1 messages and the s0 messages on a wake event. it is preferred for systems to use c-states than s1. g1/s3 suspend-to-ram (str): the system context is maintained in system dram, but power is shut off to non-critical ci rcuits. memory is re tained and refreshes continue. all external clocks stop except rtc. g1/s4 suspend-to-disk (std): the context of the system is maintained on the disk. all power is then shut off to the system except for th e logic required to resume. g2/s5 soft off (soff): system context is not maintained. all power is shut off except for the logic required to restart. a full boot is required when waking. deep s4/s5 deep s4/s5: an optional low power state where system context may or may not be maintained depending upon entry co ndition. all power is shut off except for minimal logic that allows exiting deep s4/s5. if deep s4/s5 state was entered from s4 state, then the resume path will plac e system back into s4. if deep s4/s5 state was entered from s5 stat e, then the resume path will place system back into s5.
datasheet 169 functional description ta b l e 5 - 2 3 shows the transitions rules among the various states. note that transitions among the various states may appear to temporarily transition through intermediate states. for example, in going from s0 to s3, it may appear to pass through the g1/s1 states. these intermediate transitions and states are not listed in the table. notes: 1. some wake events can be pr eserved through power failure. 2. transitions from the s1?s5 or g3 states to the s0 state are defe rred until batlow# is inactive in mobile configurations. 3. includes all other applicable types of events that force the host into and stay in g2/s5. 4. if the system was in g1/s4 be fore g3 entry, then the system will go to s0/c0 or g1/s4. g3 mechanical off (moff): system context not maintained. all power is shut off except for the rtc. no ?wak e? events are possible. this state occurs if the user removes the main system batteries in a mobile system, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the ?waking? logic. when system power return s, transition will depend on the state just prior to the entry to g3 and the afterg3_en bit in the gen_pmcon3 register (d31:f0, offset a4). refer to ta b l e 5 - 2 9 for more details. table 5-22. general power states for systems using the pch (sheet 2 of 2) state/ substates legacy name / description table 5-23. state transition rules for the pch present state transition trigger next state g0/s0/c0 ?dmi msg ?slp_en bit set ? power button override 3 ? mechanical off/power failure ?g0/s0/cx ? g1/sx or g2/s5 state ?g2/s5 ?g3 g0/s0/cx ?dmi msg ? power button override 3 ? mechanical off/power failure ?g0/s0/c0 ?s5 ?g3 g1/s1 or g1/s3 ?any enabled wake event ? power button override 3 ? mechanical off/power failure ?g0/s0/c0 2 ?g2/s5 ?g3 g1/s4 ? any enabled wake event ? g0/s0/c0 2 ? power button override 3 ?g2/s5 ? conditions met as described in section 5.13.7.6.1 and section 5.13.7.6.2 ?deep s4/s5 ? mechanical off/power failure ? g3 g2/s5 ? any enabled wake event ? g0/s0/c0 2 ? conditions met as described in section 5.13.7.6.1 and section 5.13.7.6.2 ?deep s4/s5 ? mechanical off/power failure ? g3 g2/deep s4/s5 ?any enabled wake event ? acpresent assertion ? mechanical off/power failure ?g0/s0/c0 2 ? g1/s4 or g2/s5 (see section 5.13.7.6.2 ) ?g3 g3 ? power returns ? s0/c0 (reboot) or g2/s5 4 (stay off until power button pressed or other wake event) 1 , 2
functional description 170 datasheet 5.13.3 system power planes the system has several independent power planes, as described in ta b l e 5 - 2 4 . note that when a particular power plane is shut off, it should go to a 0 v level. table 5-24. system power plane plane controlled by description processor slp_s3# signal the slp_s3# signal can be used to cut the power to the processor completely. main slp_s3# signal when slp_s3# goes active, power can be shut off to any circuit not required to wake the system from the s3 state. since the s3 state requires that the memory context be preserved, power must be retained to the main memory. the processor, devices on the pci bus, lpc i/f, and graphics will typically be shut off when the ma in power plane is off, although there may be small subsections powered. memory slp_s4# signal slp_s5# signal when slp_s4# goes active, power can be shut off to any circuit not required to wake the system from the s4. since the memory context does not need to be preserved in the s4 state, the power to the memory can also be shut down. when slp_s5# goes active, power can be shut off to any circuit not required to wake the system from the s5 state. since the memory context does not need to be preserved in the s5 state, the power to the memory can also be shut. intel ? me slp_a# this signal is asserted when th e manageability platform goes to moff. depending on the platform, this pin may be used to control the intel management engine power planes, lan subsystem power, and the spi flash power. lan slp_lan# this signal is asserted in sx/m off when both host and intel me wol are not supported. this signal can be use to control power to the intel gbe phy. deep s4/ s5 well slp_sus# this signal that the sus rails externally can be shut off for enhanced power saving. device[n] implementation specific individual subsystems may have their own power plane. for example, gpio signals may be used to control the power to disk drives, audio amplifiers, or the display screen.
datasheet 171 functional description 5.13.4 smi#/sci generation upon any enabled smi event taking place whil e the end of smi (eos) bit is set, the pch will clear the eos bit and assert smi to the processor, which will cause it to enter smm space. smi assertion is performed using a virtual legacy wire (vlw) message. prior system generations (those based upon legacy processors) used an actual smi# pin. once the smi vlw has been delivered, the pch takes no action on behalf of active smi events until host software sets the end of smi (eos) bit. at that point, if any smi events are still active, the pch will send another smi vlw message. the sci is a level-mode interrupt that is ty pically handled by an acpi-aware operating system. in non-apic systems (which is the de fault), the sci irq is routed to one of the 8259 interrupts (irq 9, 10, or 11). the 8259 interrupt controller must be programmed to level mode for that interrupt. in systems using the apic, the sci can be rout ed to interrupts 9, 10, 11, 20, 21, 22, or 23. the interrupt polarity changes depending on whether it is on an interrupt shareable with a pirq or not (see section 13.1.13 ). the interrupt remains asserted until all sci sources are removed. ta b l e 5 - 2 5 shows which events can cause an smi and sci. note that some events can be programmed to cause either an smi or sc i. the usage of the event for sci (instead of smi) is typically associated with an ac pi-based system. each smi or sci source has a corresponding enable and status bit. table 5-25. causes of smi and sci (sheet 1 of 2) cause sci smi additional enables where reported pme# yes yes pme_en=1 pme_sts pme_b0 (internal, bus 0, pme- capable agents) yes yes pme_b0_en=1 pme_b0_sts pci express* pme messages yes yes pci_exp_en=1 (not enabled for smi) pci_exp_sts pci express hot plug message yes yes hot_plug_en=1 (not enabled for smi) hot_plug_sts power button press yes yes pwrbtn_en=1 pwrbtn_sts power button override (n ote 7) yes no none prbtnor_sts rtc alarm yes yes rtc_en=1 rtc_sts ring indicate yes yes ri_en=1 ri_sts acpi timer overflow (2.34 sec.) yes yes tmrof_en=1 tmrof_sts any gpi[15:0] yes yes gpi[x]_route=10; gpi[x]_en=1 (sci) gpi[x]_route=01; alt_gpi_smi[x]_en=1 (smi) gpi[x]_sts alt_gpi_smi[x]_sts gpio[27] yes yes gp27_en=1 gp27_sts tco sci logic yes no tcosci_en=1 tcosci_sts tco sci message from processor yes no none cpusci_sts tco smi logic no yes tco_en=1 tco_sts tco smi ? no yes none newcentury_sts tco smi ? tco timerout no yes none timeout tco smi ? os writes to tco_dat_in register no yes none os_tco_smi
functional description 172 datasheet notes: 1. sci_en must be 1 to enable sci, except fo r bios_rls. sci_en must be 0 to enable smi. 2. sci can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in apic mode). 3. gbl_smi_en must be 1 to enable smi. 4. eos must be written to 1 to re-enable smi for the next 1. 5. the pch must have smi fully enabled when the pch is al so enabled to trap cycles. if smi is not enabled in conjunction with the trap enabling, then hardware behavior is undefined. 6. only gpi[15:0] may generate an smi or sci. 7. when a power button override first occurs, the system will transition i mmediately to s5. the sci will only occur after the next wake to s0 if the residual status bit (prbtnor_s ts) is not cleared prior to setting sci_en. 8. gbl_sts being set will cause an sci, even if the sci_ en bit is not set. software must take great care not to set the bios_rls bit (which causes gbl_sts to be set) if the sci handler is not in place. tco smi ? message from processor no yes none cpusmi_sts tco smi ? nmi occurred (and nmis mapped to smi) no yes nmi2smi_en=1 nmi2smi_sts tco smi ? intruder# signal goes active no yes intrd_sel=10 intrd_det tco smi ? change of the bioswe (d31:f0:dch, bit 0) bit from 0 to 1 no yes ble=1 bioswr_sts tco smi ? write attempted to bios no yes bioswe=1 bioswr_sts bios_rls written to yes no gbl_en=1 gbl_sts gbl_rls written to no yes bios_en=1 bios_sts write to b2h register no yes apmc_en = 1 apm_sts periodic timer expires no yes periodic_en=1 periodic_sts 64 ms timer expires no yes swsmi_tmr_en=1 swsmi_tmr_sts enhanced usb legacy support event no yes legacy_usb2_en = 1 legacy_usb2_sts enhanced usb intel specific event n o yes intel_usb2_en = 1 intel_usb2_sts serial irq smi reported no yes none serirq_smi_sts device monitors match address in its range no yes none devtrap_sts smbus host controller no yes smb_smi_en host controller enabled smbus host status reg. smbus slave smi message no yes none smbus_smi_sts smbus smbalert# signal active no yes none smbus_smi_sts smbus host notify message received no yes host_notify_intren smbus_smi_sts host_notify_sts (mobile only) batlow# assertion yes yes batlow_en=1 batlow_sts access microcontroller 62h/66h no yes mcsmi_en mcsmi_sts slp_en bit written to 1 no yes sm i_on_slp_en=1 smi_on_slp_en_sts spi command completed no yes none spi_smi_sts software generated gpe yes yes swgpe=1 swgpe_sts usb per-port registers write enable bit changes to 1 no yes usb2_en=1, write_enable_smi_enable=1 usb2_sts, write enable status gpio lockdown enable bit changes from ?1? to ?0? no yes gpio_unlock_smi_en=1 gpio_unlock_smi_sts table 5-25. causes of smi and sci (sheet 2 of 2) cause sci smi additional enables where reported
datasheet 173 functional description 5.13.4.1 pci express* sci pci express ports and the processor (using dmi) have the ability to cause pme using messages. when a pme message is received, the pch will set the pci_exp_sts bit. if the pci_exp_en bit is also set, the pch ca n cause an sci using the gpe1_sts register. 5.13.4.2 pci express* hot-plug pci express has a hot-plug mechanism and is capable of generating a sci using the gpe1 register. it is also capable of generating an smi. however, it is not capable of generating a wake event. 5.13.5 c-states pch-based systems implement c-states by having the processor control the states. the chipset exchanges messages with the processor as part of the c-state flow, but the chipset does not directly control any of the processor impacts of c-states, such as voltage levels or processor clocking. in addition to the new messages, the pch also provides additional information to the proce ssor using a sideband pin (pmsynch). all of the legacy c-state related pins (stpclk#, stp_cpu#, dprslp#, dprslpvr#, etc.) do not exist on the pch. 5.13.6 dynamic pci clock control (mobile only) the pci clock can be dynamically controlled independent of any other low-power state. this control is accomplished us ing the clkrun# protocol as described in the pci mobile design guide, and is transparent to software. the dynamic pci clock control is handled using the following signals: ? clkrun#: used by pci and lpc peripherals to request the system pci clock to run ? stp_pci#: used to stop the system pci clock note: the 33-mhz clock to the pch is ?free-running? and is not affected by the stp_pci# signal. note: stp_pci# is only used if pci/lpc clocks ar e distributed from clock synthesizer rather than pch. 5.13.6.1 conditions for checking the pci clock when there is a lack of pci activity the pch has the capability to stop the pci clocks to conserve power. ?pci activity? is defined as any activity that would require the pci clock to be running. any of the following conditions will indicate that it is not okay to stop the pci clock: ?cycles on pci or lpc ? cycles of any internal device that would need to go on the pci bus ? serirq activity behavioral description ? when there is a lack of activity (as defined above) for 29 pci clocks, the pch deasserts (drive high) clkrun# for 1 clock and then tri-states the signal.
functional description 174 datasheet 5.13.6.2 conditions for ma intaining the pci clock pci masters or lpc devices that wish to ma intain the pci clock running will observe the clkrun# signal deasserted, and then must re-assert if (drive it low) within 3 clocks. ? when the pch has tri-stated the clkrun# si gnal after deasserting it, the pch then checks to see if the signal has been re-asserted (externally). ? after observing the clkrun# signal asserted for 1 clock, the pch again starts asserting the signal. ? if an internal device needs the pci bu s, the pch asserts the clkrun# signal. 5.13.6.3 conditions for stopping the pci clock ? if no device re-asserts clkrun# once it has been deasserted for at least 6 clocks, the pch stops the pci clock by asserting the stp_pci# signal to the clock synthesizer. ? for case when pch distribute pci clock, pch stop pci clocks without the involvement of stp_pci#. 5.13.6.4 conditions for re -starting the pci clock ? a peripheral asserts clkrun# to indicate that it needs the pci clock re-started. ? when the pch observes the clkrun# signal asserted for 1 (free running) clock, the pch deasserts the stp_pci# signal to the clock synthesizer within 4 (free running) clocks. ? observing the clkrun# signal asserted ex ternally for 1 (free running) clock, the pch again starts driving clkrun# asserted. if an internal source requests the clock to be re-started, the pch re-asserts clkrun#, and simultaneously deasserts the stp_pci# signal. for case when pch distribute pci clock, pch start pci clocks with out the involvement of stp_pci#. 5.13.6.5 lpc devices and clkrun# if an lpc device (of any type) needs the 33 mhz pci clock, such as for lpc dma or lpc serial interrupt, then it can assert clkrun#. note that lpc devices running dma or bus master cycles will not need to assert clkrun #, since the pch asserts it on their behalf. the ldrq# inputs are ignored by the pch when the pci clock is stopped to the lpc devices in order to avoid misinterpreting th e request. the pch assumes that only one more rising pci clock edge occurs at the lpc device after the assertion of stp_pci#. upon deassertion of stp_pci#, the pch assume s that the lpc device receives its first clock rising edge corresponding to the pch?s second pci clock rising edge after the deassertion. 5.13.7 sleep states 5.13.7.1 sleep state overview the pch directly supports different sleep states (s1?s5), which are entered by methods such as setting the slp_en bit or due to a power button press. the entry to the sleep states is based on several assumptions: ? the g3 state cannot be entered using any software mechanism. the g3 state indicates a complete loss of power.
datasheet 175 functional description 5.13.7.2 initiating sleep state sleep states (s1?s5) are initiated by: ? masking interrupts, turning off all bus master enable bits, setting the desired type in the slp_typ field, and then setting the slp_en bit. the hardware then attempts to gracefully put the system into the corresponding sleep state. ? pressing the pwrbtn# signal for more than 4 seconds to cause a power button override event. in this case the transiti on to the s5 state is less graceful, since there are no dependencies on dmi messages from the processor or on clocks other than the rtc clock. ? assertion of the thrmtrip# signal will cause a transition to the s5 state. this can occur when system is in s0 or s1 state. ? shutdown by integrated manageability functions (asf/intel amt) ? internal watchdog timer time-out events 5.13.7.3 exiting sleep states sleep states (s1?s5) are exited based on wake events. the wake events forces the system to a full on state (s0), although some non-critical subsystems might still be shut off and have to be brought back manually . for example, the hard disk may be shut off during a sleep state and have to be enab led using a gpio pin before it can be used. upon exit from the pch-controlled sleep st ates, the wak_sts bit is set. the possible causes of wake events (and their restrictions) are shown in ta b l e 5 - 2 7 . note: (mobile only) if the batlow# signal is asserted, the pch does not attempt to wake from an s1?s5 state, even if the power button is pressed. this prevents the system from waking when the battery power is insu fficient to wake the system. wake events that occur while batlow# is asserted are latched by the pch, and the system wakes after batlow# is deasserted. table 5-26. sleep types sleep type comment s1 system lowers the processor?s power consum ption. no snooping is possible in this state. s3 the pch asserts slp_s3#. the slp_s3# sign al controls the power to non-critical circuits. power is only reta ined to devices needed to wake from this sleeping state, as well as to the memory. s4 the pch asserts slp_s3# and slp_s4#. th e slp_s4# signal shuts off the power to the memory subsystem. only devices needed to wake from this state should be powered. s5 the pch asserts slp_s3#, slp_s4# and slp_s5#.
functional description 176 datasheet table 5-27. causes of wake events (sheet 1 of 2) cause how enabled wake from s1, sx wake from deep s4/s5 wake from s1, sx after power loss (note 1) wake from reset types (note 2) rtc alarm set rtc_en bit in pm1_en register. yy y power button always enabled as wake event. yy yy gpi[15:0] gpe0_en register note: gpis that are in the core well are not capable of waking the system from sleep states when the core well is not powered. y gpio27 set gp27_en in gpe0_en register. yy yy lan will use pme#. wake enable set with lan logic. yy ri# set ri_en bit in gpe0_en register. yy intel ? high definition audio event sets pme_b0_sts bit; pm_b0_en must be enabled. can not wake from s5 state if it was entered due to power failure or power button override. yy primary pme# pme_b0_en bit in gpe0_en register. yy secondary pme# set pme_en bit in gpe0_en register. yy pci_exp_wake# pci_exp_wake bit. (note 3) y y sata set pme_en bit in gpe0_en register. (note 4) s1 s1 pci_exp pme message must use the pci express* wake# pin rather than messages for wake from s3, s4, or s5. s1 s1 smbalert# always enabled as wake event. yyy smbus slave wake message (01h) wake/smi# command always enabled as a wake event. note: smbus slave message can wake the system from s1?s5, as well as from s5 due to power button override. yyy
datasheet 177 functional description notes: 1. this column represents what the pch woul d honor as wake events but there may be enabling dependencies on the device side which are not enabled after a power loss. 2. reset types include: power button override, intel me initiated power button override, intel me initiated host partition reset with powe r down, intel me watchdog timer, smbus unconditional power down, proc essor thermal trip, pch catastrophic temperature event. 3. when the wake# pin is active and the pci ex press device is enabled to wake the system, the pch will wake the platform. 4. sata can only trigger a wake event in s1, bu t if pme is asserted prior to s3/s4/s5 entry and software does not clear the pme_b0 _sts, a wake event would still result. it is important to understand that the various gpis have different levels of functionality when used as wake events. the gpis that reside in the core power well can only generate wake events from sleep states where the core well is powered. also, only certain gpis are ?acpi compliant,? meaning that their status and enable bits reside in acpi i/o space. ta b l e 5 - 2 8 summarizes the use of gpis as wake events. the latency to exit the various sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the pch are insignificant. 5.13.7.4 pci express* wake# signal and pme event message pci express ports can wake the platform from any sleep state (s1, s3, s4, or s5) using the wake# pin. wake# is treated as a wake event, but does not cause any bits to go active in the gpe_sts register. pci express ports and the processor (using dmi) have the ability to cause pme using messages. when a pme message is receiv ed, the pch will set the pci_exp_sts bit. smbus host notify message received host_notify_wken bit smbus slave command register. reported in the smb_wak_sts bit in the gpeo_sts register. yyy intel ? me non- maskable wake always enabled as a wake event. yyy integrated wol enable override wol enable override bit (in configuration space). y y y table 5-27. causes of wake events (sheet 2 of 2) cause how enabled wake from s1, sx wake from deep s4/s5 wake from s1, sx after power loss (note 1) wake from reset types (note 2) table 5-28. gpi wake events gpi power well wake from notes gpi[7:0] core s1 acpi compliant gpi[15:8] suspend s1?s5 acpi compliant
functional description 178 datasheet 5.13.7.5 sx-g3-sx, handling power failures depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure. the afterg3_en bit provides the ability to program whether or not the system should boot once power returns after a power loss event. if the policy is to not boot, the system remains in an s5 state (unless previo usly in s4). there are only three possible events that will wake the system after a power failure. 1. pwrbtn#: pwrbtn# is always enabled as a wake event. when rsmrst# is low (g3 state), the pwrbtn_sts bit is rese t. when the pch exits g3 after power returns (rsmrst# goes high), the pwrbtn# signal is already high (because v cc - standby goes high before rsmrst# goes high) and the pwrbtn_sts bit is 0. 2. ri#: ri# does not have an internal pull-up. th erefore, if this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. if this signal goes low (active), wh en power returns the ri_sts bit is set and the system interprets that as a wake event. 3. rtc alarm: the rtc_en bit is in the rtc well and is preserved after a power loss. like pwrbtn_sts the rtc_sts bit is cleared when rsmrst# goes low. the pch monitors both pch pwrok and rsmrst# to detect for power failures. if pch pwrok goes low, the pwrok_flr bit is set. if rsmrst# goes low, pwr_flr is set. note: although pme_en is in the rtc well, this signal cannot wake the system after a power loss. pme_en is cleared by rtcrst#, and pme_sts is cleared by rsmrst#. note: 1. entry state to deep s4/s5 is preserved thro ugh g3 allowing resume from deep s4/s5 to take appropriate path (that is, return to s4 or s5). table 5-29. transition s due to power failure state at power failure afterg3_en bit transition when power returns s0, s1, s3 1 0 s5 s0 s4 1 0 s4 s0 s5 1 0 s5 s0 deep s4/s5 1 0 deep s4/s5 1 s0
datasheet 179 functional description 5.13.7.6 deep s4/s5 to minimize power consumption while in s4 /s5, the pch supports a lower power, lower featured version of these power states known as deep s4/s5. in the deep s4/s5 state, the suspend wells are powered off, while the deep s4/s5 well (dsw) remains powered. a limited set of wake events are supported by the logic located in the dsw. the deep s4/s5 capability and the suspwrdnack pin functionality are mutually exclusive. 5.13.7.6.1 entry into deep s4/s5 a combination of conditions is requ ired for entry into deep s4/s5. all of the following must be met: ? intel me in moff ? and either a or b as defined below: a. ((dps4_en_ac and s4) or (dps5_ en_ac and s5)) (desktop only) b. ((ac_present = 0) and ((dps4_en_d c and s4) or (dps5_en_dc and s5))) the pch also performs a suswarn#/susack# handshake to ensure the platform is ready to enter deep s4/s5. the pch asserts su swarn# as notification that it is about to enter deep s4/s5. before the pch proc eeds and asserts slp_sus#, the pch waits for susack# to assert. 5.13.7.6.2 exit from deep s4/s5 while in deep s4/s5, the pch monitors and responds to a limited set of wake events (rtc alarm, power button, and gpio27). up on sensing an enabled deep s4/s5 wake event, the pch brings up the suspend well by deasserting slp_sus#. table 5-30. supported deep s4/s5 policy configurations configuration dps4_en_dc dps4_en_ac dps5_en_dc dps5_en_ac 1: enabled in s5 when on battery (acpresent = 0) 0010 2: enabled in s5 (acpresent not considered) (desktop only) 0011 3: enabled in s4 and s5 when on battery (acpresent = 0) 1010 4: enabled in s4 and s5 (acpresent not considered) (desktop only 1111 5: deep s4 / s5 disabled 0000 table 5-31. deep s4/s5 wake events event enable rtc alarm rtc_ds_wake_dis (rcba+3318h:bit 21) power button always enabled gpio27 gpio27_en (pmbase+28h:bit 35)
functional description 180 datasheet note that acpresent has some behaviors that are different from the other deep s4/ s5 wake events. if the intel me has enab led acpresent as a wake event then it behaves just like any other intel me deep s4/s5 wake event. however, even if acpresent wakes are not enabled, if the host policies indicate that deep s4/s5 is only supported when on battery, then acpresen t going high will cause the pch to exit deep s4/s5. in this case, the suspend wells gets powered up and the platform remains in s4/moff or s5/moff. if acpresent subs equently drops (before any host or intel me wake events are detected), the pch will re-enter deep s4/s5. 5.13.8 event input sign als and their usage the pch has various input signals that trigger specific events. this section describes those signals and how they should be used. 5.13.8.1 pwrbtn# (power button) the pch pwrbtn# signal operates as a ?f ixed power button? as described in the advanced configuration and power interface, version 2.0b. pwrbtn# signal has a 16 ms de-bounce on the input. the state transition descriptions are included in ta b l e 5 - 3 2 . note that the transitions start as soon as the pwrbtn# is pressed (but after the debounce logic), and does not depe nd on when the power button is released. note: during the time that the slp_s4# signal is stretched for the minimum assertion width (if enabled), the power button is not a wake event. refer to the following power button override function section for further details. power button override function if pwrbtn# is observed active for at least four consecutive seconds, the state machine should unconditionally transition to the g2 /s5 state, regardless of present state (s0? s4), even if the pch pwrok is not active. in this case, the transition to the g2/s5 state should not depend on any particular response from the processor (such as, a dmi messages), nor any similar dependency from any other subsystem. the pwrbtn# status is readable to check if the button is currently being pressed or has been released. the status is taken afte r the de-bounce, and is readable using the pwrbtn_lvl bit. note: the 4-second pwrbtn# assertion should only be used if a system lock-up has occurred. the 4-second timer starts counting when the pch is in a s0 state. if the pwrbtn# signal is asserted and held active when the system is in a suspend state table 5-32. transitions due to power button present state event transition/action comment s0/cx pwrbtn# goes low smi or sci generated (depending on sci_en, pwrbtn_en and glb_smi_en) software typically initiates a sleep state s1?s5 pwrbtn# goes low wake event. transitions to s0 state standard wakeup g3 pwrbtn# pressed none no effect since no power not latched nor detected s0?s4 pwrbtn# held low for at least 4 consecutive seconds unconditional transition to s5 state no dependence on processor (dmi messages) or any other subsystem
datasheet 181 functional description (s1?s5), the assertion causes a wake event. once the system has resumed to the s0 state, the 4-second timer starts. note: during the time that the slp_s4# signal is stretched for the minimum assertion width (if enabled by d31:f0:a4h bit 3), the power button is not a wake event. as a result, it is conceivable that the user will press and continue to hold the power button waiting for the system to awake. since a 4-second press of the power button is already defined as an unconditional power down, the power butto n timer will be forced to inactive while the power-cycle timer is in progress. once the power-cycle timer has expired, the power button awakes the system. once the minimum slp_s4# power cycle expires, the power button must be pressed for another 4 to 5 seconds to create the override condition to s5. sleep button the advanced configuration and power interface, version 2.0b defines an optional sleep button. it differs from the power button in that it only is a request to go from s0 to s1?s4 (not s5). also, in an s5 state, the power button can wake the system, but the sleep button cannot. although the pch does not include a specific signal designated as a sleep button, one of the gpio signals can be used to create a ?control method? sleep button. see the advanced configuration and power interface, version 2.0b for implementation details. 5.13.8.2 ri# (ring indicator) the ring indicator can cause a wake event (if enabled) from the s1?s5 states. ta b l e 5 - 3 3 shows when the wake event is generated or ignored in different states. if in the g0/s0/cx states, the pch generates an interrupt based on ri# active, and the interrupt will be set up as a break event. note: filtering/debounce on ri# will not be done in pch. can be in modem or external. 5.13.8.3 pme# (pci power management event) the pme# signal comes from a pci device to request that the system be restarted. the pme# signal can generate an smi#, sci, or optionally a wake event. the event occurs when the pme# signal goes from high to low. no event is caused when it goes from low to high. there is also an internal pme_b0 bit. this is separate from the external pme# signal and can cause the same effect. table 5-33. transitions due to ri# signal present state event ri_en event s0 ri# active x ignored s1?s5 ri# active 0 1 ignored wake event
functional description 182 datasheet 5.13.8.4 sys_reset# signal when the sys_reset# pin is detected as ac tive after the 16 ms debounce logic, the pch attempts to perform a ?graceful? reset, by waiting up to 25 ms for the smbus to go idle. if the smbus is id le when the pin is detected active, the reset occurs immediately; otherwise, the counter starts. if at any poin t during the count the smbus goes idle the reset occurs. if, however, the counter expires and the smbus is still active, a reset is forced upon the system even th ough activity is still occurring. once the reset is asserted, it remains assert ed for 5 to 6 ms regardless of whether the sys_reset# input remains asserted or not. it cannot occur again until sys_reset# has been detected inactive after the debounce logic, and the system is back to a full s0 state with pltrst# inactive. note that if bi t 3 of the cf9h i/o register is set then sys_reset# will result in a full power cycle reset. 5.13.8.5 thrmtrip# signal if thrmtrip# goes active, the processor is indicating an overheat condition, and the pch immediately transitions to an s5 state, driving slp_s3#, slp_s4#, slp_s5# low, and setting the cts bit. the transition looks like a power button override. when a thrmtrip# event occurs, the pc h will power down immediately without following the normal s0 -> s5 path. the pch will immediately drive slp_s3#, slp_s4#, and slp_s5# low after sampling thrmtrip# active. if the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the pch, are no longer executing cycles properly. therefore, if thrmtrip# goes active, and the pch is rely ing on state machine logic to perform the power down, the stat e machine may not be working, and the system will not power down. the pch provides filtering for short low glit ches on the thrmtrip# signal in order to prevent erroneous system shut downs from noise. glitches shorter than 25nsec are ignored. during boot, thrmtrip# is ignored until sl p_s3#, pwrok, and pltrst# are all ?1?. during entry into a powered-down state (due to s3, s4, s5 entry, power cycle reset, etc.) thrmtrip# is ignored until either slp_s3# = 0, or pch pwrok = 0, or sys_pwrok = 0. note: a thermal trip event will: ? clear the pwrbtn_sts bit ? clear all the gpe0_en register bits ? clear the smb_wak_sts bit only if smb_sak_sts was set due to smbus slave receiving message and not set due to smbalert
datasheet 183 functional description 5.13.9 alt access mode before entering a low power state, severa l registers from powered down parts may need to be saved. in the majority of cases, this is not an issue, as registers have read and write paths. however, several of the isa compatible registers are either read only or write only. to get data out of write-only registers, and to restore data into read-only registers, the pch implements an alt access mode. if the alt access mode is entered and exit ed after reading the registers of the pch timer (8254), the timer starts counting faster (13.5 ms). the following steps listed below can cause problems: 1. bios enters alt access mode for re ading the pch timer related registers. 2. bios exits alt access mode. 3. bios continues through the execution of other needed steps and passes control to the operating system. after getting control in step #3, if the operating system does not reprogram the system timer again, the timer ticks may be happ ening faster than expected. for example microsoft ms-dos* and its associated soft ware assume that the system timer is running at 54.6 ms and as a result the time-outs in the software may be happening faster than expected. operating systems (such as microsoft wi ndows* 98 and windows* 2000) reprogram the system timer and therefore do not encounter this problem. for other operating systems (such as micros oft ms-dos*) the bios should restore the timer back to 54.6 ms before passing control to the operating system. if the bios is entering alt access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from alt access mode.
functional description 184 datasheet 5.13.9.1 write only registers with read paths in alt access mode the registers described in ta b l e 5 - 3 4 have read paths in alt access mode. the access number field in the table indicates which register will be returned per access to that port. table 5-34. write only registers with read paths in alt access mode (sheet 1 of 2) restore data restore data i/o addr # of rds access data i/o addr # of rds access data 00h 2 1 dma chan 0 base address low byte 40h 7 1 timer counter 0 status, bits [5:0] 2 dma chan 0 base address high byte 2 timer counter 0 base count low byte 01h 2 1 dma chan 0 base count low byte 3 timer counter 0 base count high byte 2 dma chan 0 base count high byte 4 timer counter 1 base count low byte 02h 2 1 dma chan 1 base address low byte 5 timer counter 1 base count high byte 2 dma chan 1 base address high byte 6 timer counter 2 base count low byte 03h 2 1 dma chan 1 base count low byte 7 timer counter 2 base count high byte 2 dma chan 1 base count high byte 41h 1 timer counter 1 status, bits [5:0] 04h 2 1 dma chan 2 base address low byte 42h 1 timer counter 2 status, bits [5:0] 2 dma chan 2 base address high byte 70h 1 bit 7 = nmi enable, bits [6:0] = rtc address 05h 2 1 dma chan 2 base count low byte c4h 2 1 dma chan 5 base address low byte 2 dma chan 2 base count high byte 2 dma chan 5 base address high byte 06h 2 1 dma chan 3 base address low byte c6h 2 1 dma chan 5 base count low byte 2 dm a chan 3 base address high byte 2 dma chan 5 base count high byte 07h 2 1 dma chan 3 base count low byte c8h 2 1 dma chan 6 base address low byte 2 dma chan 3 base count high byte 2 dma chan 6 base address high byte
datasheet 185 functional description notes: 1. the ocw1 register must be read before entering alt access mode. 2. bits 5, 3, 1, and 0 return 0. 08h 6 1 dma chan 0?3 command 2 cah 2 1 dma chan 6 base count low byte 2 dma chan 0?3 request 2 dma chan 6 base count high byte 3 dma chan 0 mode: bits(1:0) = 00 cch 2 1 dma chan 7 base address low byte 4 dma chan 1 mode: bits(1:0) = 01 2 dma chan 7 base address high byte 5 dma chan 2 mode: bits(1:0) = 10 ceh 2 1 dma chan 7 base count low byte 6 dma chan 3 mode: bits(1:0) = 11. 2 dma chan 7 base count high byte 20h 12 1 pic icw2 of master controller d0h 6 1 dma chan 4?7 command 2 2 pic icw3 of master controller 2 dma chan 4?7 request 3 pic icw4 of master controller 3 dma chan 4 mode: bits(1:0) = 00 4 pic ocw1 of master controller 1 4 dma chan 5 mode: bits(1:0) = 01 5 pic ocw2 of master controller 5 dma chan 6 mode: bits(1:0) = 10 6 pic ocw3 of master controller 6 dma chan 7 mode: bits(1:0) = 11. 7 pic icw2 of slave controller 8 pic icw3 of slave controller 9 pic icw4 of slave controller 10 pic ocw1 of slave controller 1 11 pic ocw2 of slave controller 12 pic ocw3 of slave controller table 5-34. write only registers with read paths in alt access mode (sheet 2 of 2) restore data restore data i/o addr # of rds access data i/o addr # of rds access data
functional description 186 datasheet 5.13.9.2 pic reserved bits many bits within the pic are reserved, and must have certain values written in order for the pic to operate properly. therefore, there is no need to return these values in alt access mode. when reading pic registers from 20h and a0h, the reserved bits shall return the values listed in ta b l e 5 - 3 5 . 5.13.9.3 read only registers with write paths in alt access mode the registers described in ta b l e 5 - 3 6 have write paths to them in alt access mode. software restores these values after retu rning from a powered down state. these registers must be handled special by softwa re. when in normal mode, writing to the base address/count register also writes to the current address/count register. therefore, the base address/count must be wr itten first, then the part is put into alt access mode and the current address/count register is written. table 5-35. pic reserved bits return values pic reserved bits value returned icw2(2:0) 000 icw4(7:5) 000 icw4(3:2) 00 icw4(0) 0 ocw2(4:3) 00 ocw3(7) 0 ocw3(5) reflects bit 6 ocw3(4:3) 01 table 5-36. register write accesses in alt access mode i/o address register write value 08h dma status register for channels 0?3 d0h dma status register for channels 4?7
datasheet 187 functional description 5.13.10 system power supplies, planes, and signals 5.13.10.1 power plane control with slp_s3#, slp_s4#, slp_s5#, slp_a# and slp_lan# the slp_s3# output signal can be used to cut power to the system core supply, since it only goes active for the suspend-to-ram st ate (typically mapped to acpi s3). power must be maintained to the pch suspend well, and to any other circuits that need to generate wake signals from the suspend-to-ram state. during s3 (suspend-to-ram) all signals attached to powered down plans w ill be tri-stated or driven low, unless they are pulled using a pull-up resistor. cutting power to the core may be done using the power supply, or by external fets on the motherboard. the slp_s4# or slp_s5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. cutting power to the me mory may be done using the power supply, or by external fets on the motherboard. the slp_s4# output signal is used to remove power to additional subsystems that are powered during slp_s3#. slp_s5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the cont ext of the system is saved on the disk. cutting power to the memory may be done us ing the power supply, or by external fets on the motherboard. slp_a# output signal can be used to cut power to the intel management engine and spi flash on a platform that supports the m3 state (for example, certain power policies in intel amt). slp_lan# output signal can be used to cu t power to the external intel 82579 gbe phy device. 5.13.10.2 slp_s4# and suspend-to-ram sequencing the system memory suspend voltage regulator is controlled by the glue logic. the slp_s4# signal should be used to remove power to system memory rather than the slp_s5# signal. the slp_s4# logic in the pc h provides a mechanism to fully cycle the power to the dram and/or detect if the power is not cycled for a minimum time. note: to use the minimum dram power-down feature that is enabled by the slp_s4# assertion stretch enable bit (d31:f0:a4h bi t 3), the dram power must be controlled by the slp_s4# signal. 5.13.10.3 pwrok signal when asserted, pwrok is an indication to the pch that its core well power rails are powered and stable. pwrok can be driven asynchronously. when pch pwrok is low, the pch asynchronously asserts pltrst#. pwrok must not glitch, even if rsmrst# is low. it is required that the power associated with pci/pcie have been valid for 99 ms prior to pwrok assertion in order to comply with the 100 ms pci 2.3 / pcie 2.0 specification on pltrst# deassertion. note: sys_reset# is recommended for implementing the system reset button. this saves external logic that is needed if the pwrok input is used. additionally, it allows for
functional description 188 datasheet better handling of the smbus and processor resets and avoids improperly reporting power failures. 5.13.10.4 batlow# (batte ry low) (mobile only) the batlow# input can inhibit waking from s3, s4, and s5 states if there is not sufficient power. it also causes an smi if the system is already in an s0 state. 5.13.10.5 slp_lan# pin behavior ta b l e 5 - 3 7 summarizes slp_lan# pin behavior. 5.13.10.6 rtcrst# and srtcrst# the basic behavior of the srtcrst# and rt crst# signals can be summarized by the following: 1. rtc coin cell removal: both srtcrst# and rtcrst# assert and reset logic 2. clear cmos board capability: only rtcrst# asserts it is imperative that srtcrst# is only asserted when rtcrst# is also asserted. a jumper on the srtcrst# signal should not be implemented. 5.13.11 clock generators the clock generator is expected to provide the frequencies shown in ta b l e 4 - 1 . table 5-37. slp_lan# pin behavior pin functionality (determined by soft strap) slp_lan default value bit gpio29 input / output (determined by gp_io_sel bit) pin value in s0 or m3 value in s3-s5/ moff slp_lan# 0 (default) in (default) 1 0 out 1 depends on gpio29 output data value 1 in (default) 1 1 out 1 depends on gpio29 output data value gpio29 0 (default) in z (tri-state) 0 1 in z (tri-state) 1 n/a out depends on gpio29 output data value depends on gpio29 output data value
datasheet 189 functional description 5.13.12 legacy power management theory of operation instead of relying on acpi software, legacy power management uses bios and various hardware mechanisms. the scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. however, the operating system is assumed to be at least apm enabled. without apm calls, there is no quick way to know when the system is idle between keystrokes. the pch does not support burst modes. 5.13.12.1 apm power mana gement (desktop only) the pch has a timer that, when enabled by the 1min_en bit in the smi control and enable register, generates an smi once per minute. the smi handler can check for system activity by reading th e devtrap_sts register. if none of the system bits are set, the smi handler can increment a software counter. when the counter reaches a sufficient number of consecutive minutes with no activity, the smi handler can then put the system into a lower power state. if there is activity, various bits in the devtra p_sts register will be set. software clears the bits by writing a 1 to the bit position. the devtrap_sts register allows for monitori ng various internal devices, or super i/o devices (sp, pp, fdc) on lpc or pci, keyb oard controller accesses, or audio functions on lpc or pci. other pci activity can be monitored by checking the pci interrupts. 5.13.12.2 mobile apm power management (mobile only) in mobile systems, there are additional re quirements associated with device power management. to handle this, the pch has sp ecific smi traps available. the following algorithm is used: 1. the periodic smi timer checks if a device is idle for the require time. if so, it puts the device into a low-power state and sets the associated smi trap. 2. when software (not the smi handler) attempts to access the device, a trap occurs (the cycle doesn?t really go to the device and an smi is generated). 3. the smi handler turns on the device and turns off the trap. 4. the smi handler exits with an i/o restart. this allows the original software to continue. 5.13.13 reset behavior when a reset is triggered, the pch will se nd a warning message to the processor to allow the processor to attempt to complete any outstanding memory cycles and put memory into a safe state before the platform is reset. when the processor is ready, it will send an acknowledge message to the pc h. once the message is received the pch asserts pltrst#. the pch does not require an acknowledge message from the processor to trigger pltrst#. a global reset will occur after 4 seconds if an acknowledge from the processor is not received. when the pch causes a reset by asserting pl trst# its output signals will go to their reset states as defined in chapter 3 .
functional description 190 datasheet a reset in which the host platform is reset and pltrst# is asserted is called a host reset or host partition reset. depending on the trigger a host reset may also result in power cycling see ta b l e 5 - 3 8 for details. if a host reset is triggered and the pch times out before receiving an acknowledge message from the processor a global reset with power cycle will occur. a reset in which the host and intel me partit ions of the platform are reset is called a global reset. during a global reset, all pch functionality is reset except rtc power well backed information and suspend well status, configuration, and functional logic for controlling and reporting the reset. intel me and host power back up after the power cycle period. straight to s5 is another reset type where all power wells that are controlled by the slp_s3#, slp_s4#, and slp_a# pins, as well as slp_s5# and slp_lan# (if pins are not configured as gpios), are turned off. all pch functionality is reset except rtc power well backed information and suspend well status, configuration, and functional logic for controlling and reporting the reset. the host stays there until a valid wake event occurs. ta b l e 5 - 3 8 shows the various reset triggers. table 5-38. causes of host and global resets (sheet 1 of 2) trigger host reset without power cycle 1 host reset with power cycle 2 global reset with power cycle 3 straight to s5 (host stays there) write of 0eh to cf9h (rst_cnt register) no yes no (note 4) write of 06h to cf9h (rst_cnt register) yes no no (note 4) sys_reset# asserted and cf9h (rst_cnt register) bit 3 = 0 yes no no (note 4) sys_reset# asserted and cf9h (rst_cnt register) bit 3 = 1 no yes no (note 4) smbus slave message received for reset with power cycle no yes no (note 4) smbus slave message received for reset without power cycle yes no no (note 4) smbus slave message received for unconditional power down no no no yes tco watchdog timer reaches zero two times yes no no (note 4) power failure: pwrok signal goes inactive in s0/s1 or dpwrok drops no no yes sys_pwrok failure: sys_pwrok signal goes inactive in s0/s1 no no yes processor thermal trip (thrmtrip#) causes transition to s5 and reset asserts no no no yes pch internal thermal sensors signals a catastrophic temperature condition no no no yes power button 4 second override causes transition to s5 and reset asserts no no no yes special shutdown cycle from processor causes cf9h-like pltrst# and cf9h (rst_cnt register) bit 3 = 1 no yes no (note 4) special shutdown cycle from processor causes cf9h-like pltrst# and cf9h (rst_cnt register) bit 3 = 0 yes no no (note 4) intel? management engine triggered host reset without power cycle yes no no (note 4) intel management engine triggered host reset with power cycle no yes no (note 4)
datasheet 191 functional description notes: 1. the pch drops this type of reset request if received while the sy stem is in s3/s4/s5. 2. pch does not drop this type of reset request if received while system is in a software- entered s3/s4/s5 state. however, the pch wi ll perform the reset without executing the reset_warn protocol in these states. 3. the pch does not send warning message to processor; reset oc curs without delay. 4. trigger will result in global reset with power cycle if the ackn owledge message is not received by the pch. 5. the pch waits for enabled wake event to complete reset. intel management engine triggered power button override no no no yes intel management engine watchdog timer time- out no no no yes intel management engine triggered global reset no no yes intel management engine triggered host reset with power down (host stays there) no yes (note 5) no (note 4) pltrst# entry time-out no no yes s3/4/5 entry time-out no no no yes procpwrgd stuck low no no yes power management watchdog timer no no no yes intel management engine hardware uncorrectable error no no no yes table 5-38. causes of host and global resets (sheet 2 of 2) trigger host reset without power cycle 1 host reset with power cycle 2 global reset with power cycle 3 straight to s5 (host stays there)
functional description 192 datasheet 5.14 system management (d31:f0) the pch provides various functions to make a system easier to manage and to lower the total cost of ownership (tco) of the system. features and functions can be augmented using external a/d converters and gpio, as well as an external microcontroller. the following features and func tions are supported by the pch: ? processor present detection ? detects if processor fails to fetch the first instruction after reset ? various error detection (such as ecc errors) indicated by host controller ? can generate smi#, sci, serr, nmi, or tco interrupt ? intruder detect input ? can generate tco interrupt or smi# when the system cover is removed ? intruder# allowed to go active in any power state, including g3 ? detection of bad bios flash (fwh or flash on spi) programming ? detects if data on first read is ffh (indicates that bios flash is not programmed) ? ability to hide a pci device ? allows software to hide a pci device in terms of configuration space through the use of a device hide register (see section 10.1.45 ) note: voltage id from the processor can be read using gpi signals. 5.14.1 theory of operation the system management functions are designed to allow the system to diagnose failing subsystems. the intent of this logic is that some of the system management functionality can be provided without the aid of an external microcontroller. 5.14.1.1 detecting a system lockup when the processor is reset, it is expected to fetch its first instruction. if the processor fails to fetch the first instruction after rese t, the tco timer times out twice and the pch asserts pltrst#.
datasheet 193 functional description 5.14.1.2 handling an intruder the pch has an input signal, intruder#, that can be attached to a switch that is activated by the system?s case being open. this input has a two rtc clock debounce. if intruder# goes active (after the debouncer), this will set the intrd_det bit in the tco2_sts register. the intrd_sel bits in th e tco_cnt register can enable the pch to cause an smi# or interrupt. the bios or in terrupt handler can then cause a transition to the s5 state by writing to the slp_en bit. the software can also directly read the status of the intruder# signal (high or low) by clearing and then reading the intrd_det bit. th is allows the signal to be used as a gpi if the intruder function is not required. if the intruder# signal goes inactive some point after the intrd_det bit is written as a 1, then the intrd_det bit will go to a 0 when intruder# input signal goes inactive. note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. note: the intrd_det bit resides in the pch?s rtc well, and is set and cleared synchronously with the rtc clock. thus, when software a ttempts to clear intrd_det (by writing a 1 to the bit location) there may be as much as two rtc clocks (about 65 s) delay before the bit is actually cleared. also, the intruder# signal should be asserted for a minimum of 1 ms to ensure that the intrd_det bit will be set. note: if the intruder# signal is still active when software attempts to clear the intrd_det bit, the bit remains set and the smi is ge nerated again immediately. the smi handler can clear the intrd_sel bits to avoid furthe r smis. however, if the intruder# signal goes inactive and then active again, there will not be further smis, since the intrd_sel bits would select that no smi# be generated. 5.14.1.3 detecting improper flash programming the pch can detect the case where the bios flash is not programmed. this results in the first instruction fetched to have a valu e of ffh. if this occurs, the pch sets the bad_bios bit. the bios flash may reside in fwh or flash on the spi bus. 5.14.1.4 heartbeat and event reporting using smlink/smbus heartbeat and event reporting using smlink/smbus is no longer supported. the intel amt logic in pch can be programmed to genera te an interrupt to the intel management engine when an event occurs. the intel ma nagement engine will poll the tco registers to gather appropriate bits to send the event message to the gigabit ethernet controller, if intel management engine is programmed to do so.
functional description 194 datasheet 5.14.2 tco modes 5.14.2.1 tco legacy/compatible mode in tco legacy/compatible mode, only the host smbus is utilized. the tco slave is connected to the host smbus internally by de fault. in this mode, the intel management engine smbus controllers are not used an d should be disabled by soft strap. in tco legacy/compatible mode the pch can function directly with an external lan controller or equivalent external lan co ntroller to report messages to a network management console without the aid of the system processor. this is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state. ta b l e 5 - 3 9 includes a list of events that will report messages to the network management console. note: the gpio11/smbalert# pin will trigger an event message (when enabled by the gpio11_alert_disable bit) re gardless of whether it is configured as a gpi or not. figure 5-5. tco legacy/compati ble mode smbus configuration host smbus tco slave spd (slave) uctrl legacy sensors (master or slave with alert) tco legacy/compatible mode smbus x intel me smbus controller 3 x x pci/pcie* device 3 rd party nic pch intel me smbus controller 1 intel me smbus controller 2 table 5-39. event transitions that cause messages event assertion? deassertion? comments intruder# pin yes no must be in ?s1 or hung s0? state thrm# pin yes yes must be in ?s1 or hung s0? state. note that the thrm# pin is isolated when the core power is off, thus preventing this event in s3?s5. watchdog timer expired yes no (na) ?s1 or hung s0? state entered gpio[11]/ smbalert# pin yes yes must be in ?s1 or hung s0? state batlow# yes yes must be in ?s1 or hung s0? state cpu_pwr_flr yes no ?s1 or hung s0? state entered
datasheet 195 functional description 5.14.2.2 advanced tco mode the pch supports the advanced tco mode in which smlink0 and smlink1 are used in addition to the host smbus. see figure 5-6 for more details. in this mode, the intel me smbus controllers must be enabled by soft strap in the flash descriptor. smlink0 is dedicated to integrated lan use and when an intel phy 82579 is connected to smlink0, a soft strap must be set to indi cate that the phy is connected to smlink0. the interface will be running at the freq uency of 300 khz - 400 khz depending on different factors such as board routing or bus loading when the fast mode is enabled using a soft strap. smlink1 is dedicated to embedded controller (ec) or baseboard management controller (bmc) use. in the case where a bmc is connected to smlink1, the bmc communicates with the intel management engine through the intel me smbus connected to smlink1. the host and tco slave communicate with bmc through smbus. figure 5-6. advanced tco mode host smbus tco slave spd (slave) legacy sensors (master or slave with alert) advanced tco mode smbus smlink0 intel me smbus controller 3 ec or bmc intel 82579 smlink1 pch intel me smbus controller 2 intel me smbus controller 1 pci/pcie* device
functional description 196 datasheet 5.15 general purpose i/o (d31:f0) the pch contains up to 70 general purpos e input/output (gpio) signals for desktop pch and 75 general purpose input/output (gpio) for mobile pch. each gpio can be configured as an input or output signal. the number of inputs and outputs varies depending on the configuration. following is a brief summary of new gpio features. ? capability to mask suspend well gpios from cf9h events (configured using gp_rst_sel registers) ? added capability to program gpio prior to switching to output 5.15.1 power wells some gpios exist in the suspend power plane. care must be taken to make sure gpio signals are not driven high into powered-down planes. some pch gpios may be connected to pins on devices that exist in the core well. if these gpios are outputs, there is a danger that a loss of core power (pwrok low) or a power button override event results in the pch driving a pin to a logic 1 to another device that is powered down. 5.15.2 smi# sci and nmi routing the routing bits for gpio[15:0] allow an input to be routed to smi#, sci, nmi or neither. note that a bit can be routed to either an smi# or an sci, but not both. 5.15.3 triggering gpio[15:0] have ?sticky? bits on the input. refer to the gpe0_sts register and the alt_gpi_smi_sts register. as long as the signal goes active for at least 2 clock cycles, the pch keeps the sticky status bit active. the active level can be selected in the gp_inv register. this does not apply to gpi_nmi_sts residing in gpio i/o space. if the system is in an s0 or an s1 state, the gpi inputs are sampled at 33 mhz, so the signal only needs to be active for about 60 ns to be latched. in the s3?s5 states, the gpi inputs are sampled at 32.768 khz, and thus must be active for at least 61 microseconds to be latched. note: gpis that are in the core well are not capabl e of waking the system from sleep states where the core well is not powered. if the input signal is still active when the la tch is cleared, it will again be set. another edge trigger is not requir ed. this makes these signals ?level? triggered inputs. 5.15.4 gpio registers lockdown the following gpio registers are locked do wn when the gpio lockdown enable (gle) bit is set. the gle bit resides in d31:f0:gpio control (gc) register. ? offset 00h: gpio_use_sel[31:0] ? offset 04h: gp_io_sel[31:0] ? offset 0ch: gp_lvl[31:0] ? offset 28h: gpi_nmi_en[15:0] ? offset 2ch: gpi_inv[31:0] ? offset 30h: gpio_use_sel2[63:32] ? offset 34h: gpi_io_sel2[63:32] ? offset 38h: gp_lvl2[63:32] ? offset 40h: gpio_use_sel3[95:64] ? offset 44h: gpi_io_sel3[95:64] ? offset 48h: gp_lvl3[95:64] ? offset 60h: gp_rst_sel[31:0] ? offset 64h: gp_rst_sel2[63:32] ? offset 68h: gp_rst_sel3[95:64]
datasheet 197 functional description once these registers are locked down, they become read-only registers and any software writes to these registers will have no effect. to unlock the registers, the gpio lockdown enable (gle) bit is required to be cleared to ?0?. when the gle bit changes from a ?1? to a ?0? a system management interrupt (smi#) is generated if enabled. once the gpio_unlock_smi bit is set, it can not be changed until a pltrst# occurs. this ensures that only bios can change th e gpio configuration. if the gle bit is cleared by unauthorized software, bios will set the gle bit again when the smi# is triggered and these registers will continue to be locked down. 5.15.5 serial post codes over gpio the pch adds the extended capability allowing system software to serialize post or other messages on gpio. this capability negates the requirement for dedicated diagnostic leds on the platform. additionally, based on the newer btx form factors, the pci bus as a target for post codes is increasingly difficult to support as the total number of pci devices supported are decreasing. 5.15.5.1 theory of operation for the pch generation post code serializat ion logic will be shared with gpio. these gpios will likely be shared with led control offered by the super i/o (sio) component. figure 5-7 shows a likely configuration. the anticipated usage model is that either the pch or the sio can drive a pin low to turn off an led. in the case of the power led, the sio would normally leave its corresponding pin in a high-z state to allow the led to turn on. in this state, the pch can blink the led by driving its corresponding pin low and subsequently tri-stating the buffer. the i/o buffer should not drive a ?1? when configured for this functionality and should be capable of sinking 24 ma of current. an external optical sensing device can detect the on/off state of the led. by externally post-processing the information from the optical device, the serial bit stream can be recovered. the hardware will supply a ?sync? byte before the actual data transmission to allow external detection of the transmit frequency. the frequency of transmission should be limited to 1 transition every 1 ? s to ensure the detector can reliably sample figure 5-7. serial post over gpio reference circuit sio v_3p3_stby led r note: the pull-up value is based on the brightness required. pch
functional description 198 datasheet the on/off state of the led. to allow flex ibility in pull-up resistor values for power optimization, the frequency of the transmissi on is programmable using the drs field in the gp_gb_cmdsts register. the serial bit stream is manchester encoded. this choice of transmission ensures that a transition will be seen on every clock. the 1 or 0 data is based on the transmission happening during the high or low phase of the clock. as the clock will be encoded within the data stream, hardware must ensure that the z- 0 and 0-z transitions are glitch-free. drivin g the pin directly from a flop or through glitch-free logic are possible methods to meet the glitch-free requirement. a simplified hardware/software register interface provides control and status information to track the activity of this block. software enabling the serial blink capability should implement an algorithm re ferenced below to send the serialized message on the enabled gpio. 1. read the go/busy status bit in the gp_gb_cm dsts register and verify it is cleared. this will ensure that the gpio is idled and a previously requested message is still not in progress. 2. write the data to serialize into the gp_gb_data register. 3. write the dls and drs values into the gp _gb_cmdsts register and set the go bit. this may be accomplished using a single write. the reference diagram shows the leds bein g powered from the suspend supply. by providing a generic capability that can be us ed both in the main and the suspend power planes maximum flexibility can be achieved. a key point to make is that the pch will not unintentionally drive the led control pin low unless a serialization is in progress. system board connections utilizing this serialization capability are required to use the same power plane controlling the led as the pch gpio pin. otherwise, the pch gpio may float low during the message and preven t the led from being controlled from the sio. the hardware will only be serializing messages when the core power well is powered and the processor is operational. care should be taken to prevent the pch from driving an active ?1? on a pin sharing the serial led capability. since the sio could be driving the line to 0, having the pch drive a 1 would create a high current path. a recommendation to avoid this condition involves choosing a gpio defaulting to an input. the gp_ser_blink register should be set first before changing the direction of the pin to an output. this sequence ensures the open-drain capability of the buffer is prop erly configured before enabling the pin as an output. 5.15.5.2 serial message format to serialize the data onto the gpio, an initial state of high-z is assumed. the sio is required to have its led control pin in a high-z state as well to allow the pch to blink the led (refer to the reference diagram). the three components of the serial message include the sync, data, and idle fields. the sync field is 7 bits of ?1? data followed by 1 bit of ?0? data. starting from the high-z state (led on) provides external hardware a know n initial condition and a known pattern. in case one or more of the leading 1 sync bits are lost, the 1s followed by 0 provide a clear indication of ?end of sync?. this pattern will be used to ?lock? external sampling logic to the encoded clock. the data field is shifted out with the highest byte first (msb). within each byte, the most significant bit is shifted first (msb).
datasheet 199 functional description the idle field is enforced by the hardware an d is at least 2 bit times long. the hardware will not clear the busy and go bits until this idle time is met. supporting the idle time in hardware prevents time-based counting in bi os as the hardware is immediately ready for the next serial code when the go bit is cleared. note that the idle state is represented as a high-z condition on the pin. if the last transmitted bit is a 1, returning to the idle state will result in a final 0-1 transition on the output manchester data. two full bit times of idle correspond to a count of 4 time intervals (the width of the time interval is controlled by the drs field). the following waveform shows a 1-byte serial write with a data byte of 5ah. the internal clock and bit position are for reference purposes only. the manchester d is the resultant data generated and serialized onto the gpio. since the buffer is operating in open-drain mode the transitions are from high-z to 0 and back. 5.16 sata host controller (d31:f2, f5) the sata function in the pch has three modes of operation to support different operating system conditions. in the case of native ide enabled operating systems, the pch uses two controllers to enable all six ports of the bus. the first controller (device 31: function 2) supports ports 0 ? 3 and the second controller (device 31: function 5) supports ports 4 and 5. when using a legacy operating system, only one controller (device 31: function 2) is available that supports ports 0 ? 3. in ahci or raid mode, only one controller (device 31: function 2) is utilized enabling all six ports and the second controller (device 31: function 5) shall be disabled. the map register, section 15.1.25 , provides the ability to share pci functions. when sharing is enabled, all decode of i/o is do ne through the sata registers. device 31, function 1 (ide controller) is hidden by software writing to the function disable register (d31, f0, offset f2h, bit 1), and its configuration registers are not used. the pch sata controllers feature six sets of interface signals (ports) that can be independently enabled or disabled (they cannot be tri-stated or driven low). each interface is supported by an independent dma controller. the pch sata controllers interact with an attached mass storage device through a register interface that is equivalent to that presented by a traditional ide host adapter. the host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions. note: sata interface transfer rates are independen t of udma mode settings. sata interface transfer rates will operate at the bus?s ma ximum speed, regardless of the udma mode reported by the sata device or the system bios. internal clock manchester d 8-bit sync field (1111_1110) bit 7 0 123456 5a data byte 2 clk idle
functional description 200 datasheet 5.16.1 sata 6 gb/s support the pch supports sata 6 gb/s transfers with all capable sata devices. sata 6 gb/s support is available on pch ports 0 and 1 only. note: pch ports 0 and 1 also support sata 1.5 gb/s and 3.0 gb/s device transfers. 5.16.2 sata feature support feature pch (ahci/raid disabled) pch (ahci/raid enabled) native command queuing (ncq) n/a supported auto activate for dma n/a supported hot plug support n/a supported asynchronous signal recovery n/a supported 3 gb/s transfer rate supported supported atapi asynchronous notification n/a supported host & link initiated powe r management n/a supported staggered spin-up supported supported command completion coalescing n/a n/a external sata n/a supported feature description native command queuing (ncq) allows the device to reorder co mmands for more efficient data transfers auto activate for dma collapses a dma setup then dma activate sequence into a dma setup only hot plug support allows for device detection wi thout power being applied and ability to connect and disconnect devices without prior notification to the system asynchronous signal recovery provides a recovery from a loss of signal or establishing communication after hot plug 6 gb/s transfer rate capable of data transfers up to 6 gb/s atapi asynchronous notification a mechanism for a device to send a notification to the host that the device requires attention host & link initiated power management capability for the host controller or device to re quest partial and slumber interface power states staggered spin-up enables the host the ability to spin up hard drives sequentially to prevent power load problems on boot command completion coalescing reduces interrupt and completi on overhead by allowing a specified number of commands to complete and then generating an interrupt to process the commands external sata technology that allows for an ou tside the box connection of up to 2 meters (when using the cable defined in sata-io)
datasheet 201 functional description 5.16.3 theory of operation 5.16.3.1 standard ata emulation the pch contains a set of registers that shadow the contents of the legacy ide registers. the behavior of the command and control block registers, pio, and dma data transfers, resets, and interrupts are all emulated. note: the pch will assert intr when the mast er device completes the edd command regardless of the command completion status of the slave device. if the master completes edd first, an intr is generated and bsy will remain '1' until the slave completes the command. if the slave comple tes edd first, bsy will be '0' when the master completes the edd command and asserts intr. software must wait for busy to clear (0) before completing an edd command, as required by the ata5 through ata7 (t13) industry standards. 5.16.3.2 48-bit lba operation the sata host controller supports 48-bit lba through the host-to-device register fis when accesses are performed using writes to the task file. the sata host controller will ensure that the correct data is put into the correct byte of the host-to-device fis. there are special considerations when readin g from the task file to support 48-bit lba operation. software may need to read all 16-bits. since the registers are only 8-bits wide and act as a fifo, a bit must be set in the device/control register, which is at offset 3f6h for primary and 376h for secondary (or their native counterparts). if software clears bit 7 of the control regist er before performing a read, the last item written will be returned from the fifo. if so ftware sets bit 7 of the control register before performing a read, the first item written will be returned from the fifo. 5.16.4 sata swap bay support the pch provides for basic sata swap bay support using the psc register configuration bits and power management flows. a device can be powered down by software and the port can then be disabled, allowing removal and insertion of a new device. note: this sata swap bay operation requires bo ard hardware (implementation specific), bios, and operating system support. 5.16.5 hot plug operation the pch supports hot plug surprise removal an d insertion notification in the partial, slumber and listen mode states when used with low power device presence detection. software can take advantage of power savings in the low power states while enabling hot plug operation. refer to chapter 7 of the ahci specification for details. 5.16.5.1 low power device presence detection low power device presence detection enables sata link power management to co- exist with hot plug (insertion and removal) without interlock switch or cold presence detect. the detection mechanism allows hot pl ug events to be detectable by hardware across all link power states (active, partial, slumber) as well as ahci listen mode. if the low power device presence detection circuit is disabled the pch reverts to hot plug surprise removal notification (without an interlock switch) mode that is mutually exclusive of the partial and slumber power management states.
functional description 202 datasheet 5.16.6 function level reset support (flr) the sata host controller supports the function level reset (flr) capability. the flr capability can be used in conjunction with intel virtualization technology. flr allows an operating system in a virtual machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. the device provides a software interface that enables the operating system to reset the whole device as if a pci reset was asserted. 5.16.6.1 flr steps 5.16.6.1.1 flr initialization 1. a flr is initiated by software writing a ?1? to the initiate flr bit. 2. all subsequent requests targeting the function will not be claimed and will be master abort immediate on the bus. this includes any configuration, i/o or memory cycles, however, the function shall continue to accept completions targeting the function. 5.16.6.1.2 flr operation the function will reset all configuration, i/o and memory registers of the function except those indicated otherwise and reset a ll internal states of the function to the default or initial condition. 5.16.6.1.3 flr completion the initiate flr bit is reset (cleared) when the flr reset is comple ted. this bit can be used to indicate to the software that the flr reset is completed. note: from the time initiate flr bit is written to 1 software must wait at least 100 ms before accessing the function. 5.16.7 intel ? rapid storage technology configuration the intel rapid storage technology offers se veral diverse options for raid (redundant array of independent disks) to meet the ne eds of the end user. ahci support provides higher performance and alleviates disk bottlenecks by taking advantage of the independent dma engines that each sata port offers in the pch. ? raid level 0 performance scaling up to 4 drives, enabling higher throughput for data intensive applications such as video editing. ? data security is offered through raid level 1, which performs mirroring. ? raid level 10 provides high levels of storage performance with data protection, combining the fault-tolerance of raid level 1 with the performance of raid level 0. by striping raid level 1 segments, high i/o rates can be achieved on systems that require both performance and fault-tolerance. raid level 10 requires 4 hard drives, and provides the capacity of two drives. ? raid level 5 provides highly efficient storage while maintaining fault-tolerance on 3 or more drives. by striping parity, and rotating it across all disks, fault tolerance of any single drive is achieved while only consuming 1 drive worth of capacity. that is, a 3 drive raid 5 has the capacity of 2 drives, or a 4 drive raid 5 has the capacity of 3 drives. raid 5 has high read transaction rates, with a medium write rate. raid 5 is well suited for applications that require high amounts of storage while maintaining fault tolerance.
datasheet 203 functional description by using the pch?s built-in intel rapid stor age technology, there is no loss of pci resources (request/grant pair) or add-in card slot. intel ? rapid storage technology functionality requires the following items: 1. the pch sku enabled for intel ? rapid storage technology 2. intel rapid storage manager raid option rom must be on the platform 3. intel rapid storage manager drivers, most recent revision. 4. at least two sata hard disk drives (minimum depends on raid configuration). intel rapid storage technology is not available in the following configurations: 1. the sata controller is in compatible mode. 5.16.7.1 intel ? rapid storage manager raid option rom the intel rapid storage manager raid option rom is a standard pnp option rom that is easily integrated into any system bios. when in place, it provides the following three primary functions: ? provides a text mode user interface that allows the user to manage the raid configuration on the system in a pre-oper ating system environment. its feature set is kept simple to keep size to a minimum, but allows the user to create & delete raid volumes and select recovery options when problems occur. ? provides boot support when using a raid vo lume as a boot disk. it does this by providing int13 services when a raid vo lume needs to be accessed by ms-dos applications (such as ntldr) and by ex porting the raid volumes to the system bios for selection in the boot order. ? at each boot up, provides the user with a status of the raid volumes and the option to enter the user interface by pressing ctrl-i. 5.16.8 intel ? smart response technology intel ? smart response technology is a disk ca ching solution that can provide improved computer system performance with improved power savings. it allows configuration of a computer systems with the advantage of having hdds for maximum storage capacity with system performance at or near ssd performance levels. 5.16.9 power management operation power management of the pch sata controller and ports will cover operations of the host controller and the sata wire. 5.16.9.1 power state mappings the d0 pci power management state for device is supported by the pch sata controller. sata devices may also have multiple power states. from parallel ata, three device states are supported through acpi. they are: ? d0 ? device is working and instantly available. ? d1 ? device enters when it receives a standby immediate command. exit latency from this state is in seconds ? d3 ? from the sata device?s perspective, no different than a d1 state, in that it is entered using the standby immediate command. however, an acpi method is also called which will reset the device and then cut its power. each of these device states are subsets of the host controller?s d0 state.
functional description 204 datasheet finally, sata defines three phy layer power states, which have no equivalent mappings to parallel ata. they are: ? phy ready ? phy logic and pll are both on and active ? partial ? phy logic is powered, but in a reduced state. exit latency is no longer than 10 ns ? slumber ? phy logic is powered, but in a reduced state. exit latency can be up to 10 ms. since these states have much lower exit latency than the acpi d1 and d3 states, the sata controller defines these states as sub-states of the device d0 state. 5.16.9.2 power state transitions 5.16.9.2.1 partial and slumber state entry/exit the partial and slumber states save interface power when the interface is idle. it would be most analogous to pci clkrun# (in power savings, not in mechanism), where the interface can have power saved while no commands are pending. the sata controller defines phy layer power management (as performed using primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. the sata controller accepts device transition types, but does not issue any transitions as a host. all received requests from a sata device will be acked. when an operation is performed to the sata controller such that it needs to use the sata cable, the controller must check whet her the link is in the partial or slumber states, and if so, must issue a com_wake to bring the link back online. similarly, the sata device must perform the same action. 5.16.9.2.2 device d1, d3 states these states are entered after some period of time when software has determined that no commands will be sent to this device for some time. the mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to th e device. the command most likely to be used in ata/atapi is the ?standby immediate? command. 5.16.9.2.3 host controller d3 hot state after the interface and device have been pu t into a low power state, the sata host controller may be put into a low power state. this is performed using the pci power management registers in configuration space. there are two very important aspects to note when using pci power management. 1. when the power state is d3, only accesses to configuration space are allowed. any attempt to access the memory or i/o spaces will result in master abort. 2. when the power state is d3, no interrupt s may be generated, even if they are enabled. if an interrupt status bit is pending when the controller transitions to d0, an interrupt may be generated. when the controller is put into d3, it is a ssumed that software has properly shut down the device and disabled the ports. therefore, there is no need to sustain any values on the port wires. the interface will be treated as if no device is present on the cable, and power will be minimized. when returning from a d3 state, an internal reset will not be performed.
datasheet 205 functional description 5.16.9.2.4 non-ahci mode pme# generation when in non-ahci mode (legacy mode) of operation, the sata controller does not generate pme#. this includes attach events (since the port must be disabled), or interlock switch events (using the satagp pins). 5.16.9.3 smi trapping (apm) device 31:function2:offset c0h (see section 14.1.39 ) contain control for generating smi# on accesses to the ide i/o spaces. these bits map to the legacy ranges (1f0? 1f7h, 3f6h, 170?177h, and 376h) and native ide ranges defined by pcmdba, pctlba, scmdba an sctlba. if the sata controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the sata controlle r, and for an smi# to be generated. if an access to the bus-master ide registers occurs while trapping is enabled for the device being accessed, then the register is updated, an smi# is generated, and the device activity status bits ( section 14.1.40 ) are updated indicating that a trap occurred. 5.16.10 sata device presence in legacy mode, the sata controller does not generate interrupts based on hot plug/ unplug events. however, the sata phy does kn ow when a device is connected (if not in a partial or slumber state), and it s beneficial to communicate this information to host software as this will greatly reduce boot times and resume times. the flow used to indicate sata device presence is shown in figure 5-8 . the ?pxe? bit refers to pcs.p[3:0]e bits, depending on the port being checked and the ?pxp? bits refer to the pcs.p[3:0]p bits, depending on the port being checked. if the pcs/pxp bit is set a device is present, if the bit is cleared a device is not present. if a port is disabled, software can check to see if a new device is connected by periodically re-enabling the port and observing if a device is present, if a device is not present it can disable the port and check again later. if a port remains enabled, software can periodically poll pcs.pxp to see if a new device is connected. figure 5-8. flow for port enable / device present bits
functional description 206 datasheet 5.16.11 sata led the sataled# output is driven whenever the bsy bit is set in any sata port. the sataled# is an active-low open-drain outp ut. when sataled# is low, the led should be active. when sataled# is high, the led should be inactive. 5.16.12 ahci operation the pch provides hardware support for adva nced host controller interface (ahci), a programming interface for sata host controllers developed through a joint industry effort. ahci defines transactions between the sata controller and software and enables advanced performance and usability with sa ta. platforms supporting ahci may take advantage of performance features such as no master/slave designation for sata devices?each device is treated as a master?and hardware assisted native command queuing. ahci also provides usability enhancements such as hot-plug. ahci requires appropriate software support (such as, an ahci driver) and for some features, hardware support in the sata device or additional platform hardware. the pch supports all of the mandatory features of the serial ata advanced host controller interface specification , revision 1.2 and many optional features, such as hardware assisted native command queuing, aggressive power management, led indicator support, and hot-plug through the use of interlock switch support (additional platform hardware and software may be re quired depending upon the implementation). note: for reliable device removal notification wh ile in ahci operation without the use of interlock switches (surprise removal), interf ace power management should be disabled for the associated port. see section 7.3.1 of the ahci specification for more information. 5.16.13 sgpio signals the sgpio signals, in accordance to the sff-8485 specification, support per-port led signaling. these signals are not related to sataled#, which allows for simplified indication of sata command activity. the sgpio group interfaces with an external controller chip that fetches and serializes the data for driving across the sgpio bus. the output signals then control the leds. this feature is only valid in ahci/raid mode. 5.16.13.1 mechanism the enclosure management for sata controller 1 (device 31: function 2) involves sending messages that control leds in the enclosure. the messages for this function are stored after the normal registers in the ahci bar, at offset 580h bytes for the pch from the beginning of the ahci bar as sp ecified by the em_loc global register ( section 14.4.1.6 ). software creates messages for transmission in the enclosure management message buffer. the data in the message buffer should not be changed if ctl.tm bit is set by software to transmit an update message. software should only update the message buffer when ctl.tm bit is cleared by hard ware otherwise the message transmitted will be indeterminate. software then writes a register to cause hardware to transmit the message or take appropriate action based on the message content. the software should only create message types supported by the controller, which is led messages for the pch. if the software creates other non led message types (such as, saf-te, ses-2), the sgpio interface may hang and the result is indeterminate. during reset all sgpio pins will be in tri-stat e. the interface will continue to be in tri- state after reset until the first transmission occurs when software programs the message buffer and sets the transmit bit ctl.tm. the sata host controller will initiate the transmission by driving sclock and at the same time drive the sload to ?0? prior
datasheet 207 functional description to the actual bit stream transmission. the host will drive sload low for at least 5 sclock then only start the bit stream by driving the sload to high. sload will be driven high for 1 sclock follow by vendor specific pattern that is default to ?0000? if software has yet to program the value. a total of 21-bit stream from 7 ports (port0, port1, port2, port3, port4 port5 and port6) of 3-bit per port led message will be transmitted on sdataout0 pin after the sload is driven high for 1 sclock. only 3 ports (port4, port5 and port6) of 9 bit total led message follow by 12 bits of tri-state value will be transmitted out on sdataout1 pin. all the default led message values will be high prior to software setting them, except the activity led message that is configured to be hardware driven that will be generated based on the activity from the respective port. all the led message values will be driven to ?1? for the port that is unimplemented as indicated in the port implemented register regardless of the software programmed value through the message buffer. there are 2 different ways of resetting the pch?s sgpio interface, asynchronous reset and synchronous reset. asynchronous reset is caused by platform reset to cause the sgpio interface to be tri-state asynchronously. synchronous reset is caused by setting the ctl.reset bit, clearing the ghc.ae bit or hba reset, where host controller will complete the existing full bit stream transmis sion then only tri-state all the sgpio pins. after the reset, both synchronous and as ynchronous, the sgpio pins will stay tri- stated. note: the pch host controller does not ensure that it will cause the target sgpio device or controller to be reset. softwa re is responsible to keep the pch sgpio interface in tri- state for 2 second to cause a reset on the target of the sgpio interface. 5.16.13.2 message format messages shall be constructed with a one dw ord header that describes the message to be sent followed by the actual message contents. the first dword shall be constructed as follows : bit description 31:28 reserved 27:24 message type (mtype): specifies the type of the message. the message types are: 0h = led 1h = saf-te 2h = ses-2 3h = sgpio (register based interface) all other values reserved 23:16 data size (dsize): specifies the data size in bytes. if the message (enclosure services command) has a data bu ffer that is associated with it that is transferred, the size of that data buffer is spec ified in this field. if there is no separate data buffer, this field shall have a value of ?0?. the data directly follows the message in the message buffer. for the pch , this value should always be ?0?. 15:8 message size (msize): specifies the size of the message in bytes. the message size does not include the one dword header. a value of ?0? is invalid. for the pch , the message size is always 4 bytes. 7:0 reserved
functional description 208 datasheet the saf-te, ses-2, and sgpio message formats are defined in the corresponding specifications, respectively. the led message type is defined in section 5.16.13.3 . it is the responsibility of software to ensure the content of the message format is correct. if the message type is not programmed as 'led' for this controller, the controller shall not take any action to update its leds. note that for led message type, the message size is always consisted of 4 bytes. 5.16.13.3 led message type the led message type specifies the status of up to three leds. typically, the usage for these leds is activity, fault, and locate. no t all implementations necessarily contain all leds (for example, some implementations may not have a locate led). the message identifies the hba port number and the port multiplier port number that the slot status applies to. if a port multiplier is not in use with a particular device, the port multiplier port number shall be ?0?. the format of the led message type is defined in ta b l e 5 - 4 0 . the leds shall retain their values until there is a following update for that particular slot. table 5-40. multi-activity led message type byte description 3-2 value (val): this field describes the state of each led for a particular location. there are three leds that may be supported by th e hba. each led has 3 bits of control. led values are: 000b ? led shall be off 001b ? led shall be solid on as perceived by human eye all other values reserved the led bit locations are: bits 2:0 ? activity led (may be driven by hardware) bits 5:3 ? vendor specific led (such as locate) bits 8:6 - vendor specific led (such as fault) bits 15:9 ? reserved vendor specific message is: bit 3:0 ? vendor specific pattern bit 15:4 ? reserved note: if activity led hardware driven (attr.al hd) bit is set, host will output the hardware led value sampled internally and will ignore software written activity value on bit [2:0]. since the pch enclos ure management does not support port multiplier based led message, th e led message will be generated independently based on respec tive port?s operation activity. vendor specific led values locate (bits 5:3) and fault (bit s 8:6) always are driven by software. 1 port multiplier information: specifies slot specific in formation related to port multiplier. bits 3:0 specify the port multiplier port num ber for the slot that requires the status update. if a port multiplier is not attached to the device in the affected slot, the port multiplier port number shall be '0'. bits 7:4 are reserved. the pc h does not support led messages for devices behi nd a port multiplier. th is byte should be 0. 0 hba information: specifies slot specific information related to the hba. bits 4:0 ? hba port number for the sl ot that requires the status update. bit 5 ? if set to '1', value is a vendor sp ecific message that a pplies to the entire enclosure. if cleared to '0', value appl ies to the port specified in bits 4:0. bits 7:6 ? reserved
datasheet 209 functional description 5.16.13.4 sgpio waveform figure 5-9. serial data transm itted over the sgpio interface
functional description 210 datasheet 5.16.14 external sata the pch supports external sata. external sata utilizes the sata interface outside of the system box. the usage model for this feature must comply with the serial ata ii cables and connectors volume 2 gold specif ication at www.sata-io.org. intel validates two configurations: 1. the cable-up solution involves an internal sata cable that connects to the sata motherboard connector and spans to a back panel pci bracket with an esata connector. a separate esata cable is required to connect an esata device. 2. the back-panel solution involves running a trace to the i/o back panel and connecting a device using an external sata connector on the board. 5.17 high precision event timers this function provides a set of timers that can be used by the operating system. the timers are defined such that in the future, the operating system may be able to assign specific timers to used directly by specific applications. each timer can be configured to cause a separate interrupt. the pch provides eight timers. the timers ar e implemented as a single counter, each with its own comparator and value register. this counter increases monotonically. each individual timer can generate an interrupt when the value in its value register matches the value in the main counter. the registers associated with these timers are mapped to a memory space (much like the i/o apic). however, it is not implemented as a standard pci function. the bios reports to the operating system the location of the register space. the hardware can support an assignable decode space; however, the bios sets this space prior to handing it over to the operating system. it is not expected that the operating system will move the location of these timers once it is set by the bios. 5.17.1 timer accuracy 1. the timers are accurate over any 1 ms peri od to within 0.05% of the time specified in the timer resolution fields. 2. within any 100 microsecond period, the time r reports a time that is up to two ticks too early or too late. each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. the timer is monotonic. it does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). the main counter is clocked by the 14. 31818 mhz clock, synchronized into the 66.666 mhz domain. this results in a non- uniform duty cycle on the synchronized clock, but does have the correct average period. the accuracy of the main counter is as accurate as the 14.31818 mhz clock.
datasheet 211 functional description 5.17.2 interrupt mapping mapping option #1 (legacy replacement option) in this case, the legacy replacement rout bit (leg_rt_cnf) is set. this forces the mapping found in ta b l e 5 - 4 1 . note: the legacy option does not pr eclude delivery of irq0/irq 8 using direct fsb interrupt messages. mapping option #2 (standard option) in this case, the legacy replacement rout bit (leg_rt_cnf) is 0. each timer has its own routing control. the interrupts can be ro uted to various interrupts in the 8259 or i/o apic. a capabilities field indicates which interrupts are valid options for routing. if a timer is set for edge-triggered mode, the ti mers should not be shared with any pci interrupts. for the pch, the only supported interrupt values are as follows: timer 0 and 1: irq20, 21, 22 & 23 (i/o apic only). timer 2: irq11 (8259 or i/o apic) and irq20, 21, 22 & 23 (i/o apic only). timer 3: irq12 (8259 or i/o apic) and irq 20, 21, 22 & 23 (i/o apic only). interrupts from timer 4, 5, 6, 7 can only be delivered using direct fsb interrupt messages. table 5-41. legacy replacement routing timer 8259 mapping apic mapping comment 0i r q 0 i r q 2 in this case, the 8254 timer will not cause any interrupts 1i r q 8 i r q 8 in this case, the rtc will not cause any interrupts. 2 & 3 per irq routing field. per irq routing field 4, 5, 6, 7 not available not available
functional description 212 datasheet 5.17.3 periodic versus non-periodic modes non-periodic mode timer 0 is configurable to 32 (default) or 64-bit mode, whereas timers 1, 2 and 3 only support 32-bit mode (see section 20.1.5 ). all of the timers support non-periodic mode. refer to section 2.3.9.2.1 of the ia-pc hpet specification for a description of this mode. periodic mode timer 0 is the only timer that supports peri odic mode. refer to section 2.3.9.2.2 of the ia-pc hpet specification for a description of this mode. the following usage model is expected: 1. software clears the enable_cnf bit to prevent any interrupts. 2. software clears the main counter by writing a value of 00h to it. 3. software sets the timer0_val_set_cnf bit. 4. software writes the new value in the timer0_comparator_val register. 5. software sets the enable_c nf bit to enable interrupts. the timer 0 comparator value register cannot be programmed reliably by a single 64-bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. if the actual timer 0 compar ator value needs to be reinitialized, then the following software solution will alwa ys work regardless of the environment: 1. set timer0_val_set_cnf bit. 2. set the lower 32 bits of the timer0 comparator value register. 3. set timer0_val_set_cnf bit. 4. set the upper 32 bits of the timer0 comparator value register. 5.17.4 enabling the timers the bios or operating system pnp code shou ld route the interrupts. this includes the legacy rout bit, interrupt rout bit (for each timer), interrupt type (to select the edge or level type for each timer) the device driver code should do the following for an available timer: 1. set the overall enable bit (offset 10h, bit 0). 2. set the timer type field (selects one-shot or periodic). 3. set the interrupt enable. 4. set the comparator value.
datasheet 213 functional description 5.17.5 interrupt levels interrupts directed to the internal 8259s are active high. see section 5.9 for information regarding the polarity programmin g of the i/o apic for detecting internal interrupts. if the interrupts are mapped to the 8259 or i/o apic and set for level-triggered mode, they can be shared with pci interrupts. they may be shared although it is unlikely for the operating system to attempt to do this. if more than one timer is configured to share the same irq (using the timern_int_rout_cnf fields), then the software must configure the timers to level- triggered mode. edge-triggered interrupts cannot be shared. 5.17.6 handling interrupts if each timer has a unique interrupt and the timer has been configured for edge- triggered mode, then there are no specific steps required. no read is required to process the interrupt. if a timer has been configured to level-tr iggered mode, then its interrupt must be cleared by the software. this is done by reading the interrupt status register and writing a 1 back to the bit position for the interrupt to be cleared. independent of the mode, software can read the value in the main counter to see how time has passed between when the interrupt was generated and when it was first serviced. if timer 0 is set up to generate a periodic interrupt, the software can check to see how much time remains until the next interrupt by checking the timer value register. 5.17.7 issues related to 64-bit timers with 32-bit processors a 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit instructions. however, a 32-bit processor may not be able to directly read 64-bit timer. a race condition comes up if a 32-bit processor reads the 64-bit register using two separate 32-bit reads. the danger is that just after reading one half, the other half rolls over and changes the first half. if a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer. if a 32-bit processor does not want to halt the timer, it can use the 64-b it timer as a 32-bit timer by setting the timern_32mode_cnf bit. this causes the timer to behave as a 32-bit timer. the upper 32-bits are always 0. alternatively, software may do a multiple read of the counter while it is running. software can read the high 32 bits, then the low 32 bits, the high 32 bits again. if the high 32 bits have not changed between the two reads, then a rollover has not happened and the low 32 bits are valid. if the high 32 bits have changed between reads, then the multiple reads are repe ated until a valid read is performed. note: on a 64-bit platform, if software attempts a 64 bit read of the 64-bit counter, software must be aware that some platforms may split the 64 bit read into two 32 bit reads. the read maybe inaccurate if the low 32 bits roll over between the high and low reads.
functional description 214 datasheet 5.18 usb ehci host controllers (d29:f0 and d26:f0) the pch contains two enhanced host controller interface (ehci) host controllers which support up to fourteen usb 2.0 high-speed root ports. usb 2.0 allows data transfers up to 480 mb/s. usb 2.0 based debug port is also implemented in the pch. 5.18.1 ehc initialization the following descriptions step through th e expected pch enhanced host controller (ehc) initialization sequence in chronologica l order, beginning with a complete power cycle in which the suspend well and core well have been off. 5.18.1.1 bios initialization bios performs a number of platform cu stomization steps after the core well has powered up. contact your intel field representative for additional pch bios information. 5.18.1.2 driver initialization see chapter 4 of the enhanced host controller interf ace specification for universal serial bus, revision 1.0. 5.18.1.3 ehc resets in addition to the standard pch hardware re sets, portions of the ehc are reset by the hcreset bit and the transition from the d3 hot device power management state to the d0 state. the effects of each of these resets are: if the detailed register descriptions give exceptions to these rules, those exceptions override these rules. this summary is provid ed to help explain the reasons for the reset policies. 5.18.2 data structures in main memory see section 3 and appendix b of the enhanced host controller interface specification for universal serial bus, revision 1.0 for details. reset doe s reset does not reset comments hcreset bit set. memory space registers except structural parameters (which is written by bios). configuration registers. the hcreset must only affect registers that the ehci driver controls. pci configuration space and bios-programmed parameters cannot be reset. software writes the device power state from d3 hot (11b) to d0 (00b). core well registers (except bios- programmed registers). suspend well registers; bios- programmed core well registers. the d3-to-d0 transition must not cause wake information (suspend well) to be lost. it also must not clear bios-programmed registers because bios may not be invoked following the d3-to-d0 transition.
datasheet 215 functional description 5.18.3 usb 2.0 enhanced host controller dma the pch usb 2.0 ehc implements three sources of usb packets. they are, in order of priority on usb during each microframe: 1. the usb 2.0 debug port (see section usb 2.0 based debug port), 2. the periodic dma engine, and 3. the asynchronous dma engine. the pch always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. if there is time left in the mi croframe, then the ehc performs any pending asynchronous traffic until the end of the microframe (eof1). note that the debug port traffic is only presented on port 1 and port 9, while the other ports are idle during this time. 5.18.4 data encoding and bit stuffing see chapter 8 of the universal serial bus specification, revision 2.0. 5.18.5 packet formats see chapter 8 of the universal serial bus specification, revision 2.0 . the pch ehci allows entran ce to usb test modes, as defined in the usb 2.0 specification, including test j, test packet, etc. however note that the pch test packet test mode interpacket gap timing may not meet the usb 2.0 specification. 5.18.6 usb 2.0 interrupts and error conditions section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 goes into detail on the ehc interrupts and the error conditions that cause them. all error conditions that the ehc detects can be reported through the ehci interrupt status bits. only pch-specific interrupt and error-reporting behavior is documented in this section. the ehci interrupts section must be read first, followed by this section of the datasheet to fully comp rehend the ehc interrupt and error-reporting functionality. ? based on the ehc buffer sizes and buffe r management policies, the data buffer error can never occur on the pch. ? master abort and target abort responses from hub interface on ehc-initiated read packets will be treated as fatal host erro rs. the ehc halts when these conditions are encountered. ? the pch may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal writ e buffers. the requirement in the enhanced host controller interface specificatio n for universal serial bus, revision 1.0 (that the status is written to memory) is met internally, even though the write may not be seen on dmi before the interrupt is asserted. ? since the pch supports the 1024-element frame list size, the frame list rollover interrupt occurs every 1024 milliseconds. ? the pch delivers interrupts using pirqh#. ? the pch does not modify the cerr count on an interrupt in when the ?do complete-split? execution criteria are not met. ? for complete-split transactions in the peri odic list, the ?missed microframe? bit does not get set on a control-structure-fetch that fails the late-start test. if subsequent accesses to that control structure do not fail the late-start test, then the ?missed microframe? bit will get set and written back.
functional description 216 datasheet 5.18.6.1 aborts on usb 2.0-initiated memory reads if a read initiated by the ehc is aborted, the ehc treats it as a fatal host error. the following actions are taken when this occurs: ? the host system error status bit is set. ? the dma engines are halted after completi ng up to one more transaction on the usb interface. ? if enabled (by the host system error enable), then an interrupt is generated. ? if the status is master abort, then the received master abort bit in configuration space is set. ? if the status is target abort, then the received target abort bit in configuration space is set. ? if enabled (by the serr enable bit in the function?s configuration space), then the signaled system error bit in configuration bit is set. 5.18.7 usb 2.0 power management 5.18.7.1 pause feature this feature allows platforms to dynamically enter low-power states during brief periods when the system is idle (that is, between keystrokes). this is useful for enabling power management features in the pc h. the policies for entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. normally, when the ehc is enabled, it regularly accesses main memory while traversing the dma schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. suspending all of the enabled ports can prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the usb ports that makes this unacceptable for the purpose of dynamic power management. as a result, the ehci software drivers are allowed to pause the ehc dma engines when it knows that the traffic patterns of the attached devices can afford the delay. the pause only prevents the ehc from generating memory accesses; the sof packets continue to be generated on the usb ports (unlike the suspended state). 5.18.7.2 suspend feature the enhanced host controller interface (ehci) for universal serial bus specification , section 4.3 describes the details of port suspend and resume. 5.18.7.3 acpi device states the usb 2.0 function only supports the d0 and d3 pci power management states. notes regarding the pch implementation of the device states: 1. the ehc hardware does not inherently consume any more power when it is in the d0 state than it does in the d3 state. however, software is required to suspend or disable all ports prior to entering the d3 state such that the maximum power consumption is reduced. 2. in the d0 state, all implemented ehc features are enabled. 3. in the d3 state, accesses to the ehc me mory-mapped i/o range will master abort. note that, since the debug port uses the same memory range, the debug port is only operational when the ehc is in the d0 state. 4. in the d3 state, the ehc interrupt must never assert for any reason. the internal pme# signal is used to signal wake events, etc. 5. when the device power state field is wri tten to d0 from d3, an internal reset is generated. see section ehc resets for general rules on the effects of this reset. 6. attempts to write any other value into the device power state field other than 00b (d0 state) and 11b (d3 state) will complete normally without changing the current value in this field.
datasheet 217 functional description 5.18.7.4 acpi system states the ehc behavior as it relates to other power management states in the system is summarized in the following list: ? the system is always in the s0 state when the ehc is in the d0 state. however, when the ehc is in the d3 state, the system may be in any power management state (including s0). ? when in d0, the pause feature (see section 5.18.7.1 ) enables dynamic processor low-power states to be entered. ? the pll in the ehc is disabled when entering the s3/s4/s5 states (core power turns off). ? all core well logic is reset in the s3/s4/s5 states. 5.18.8 usb 2.0 legacy keyboard operation the pch must support the possibility of a keyboard downstream from either a full- speed/low-speed or a high-speed port. the description of the lega cy keyboard support is unchanged from usb 1.1. the ehc provides the basic ability to generate smis on an interrupt event, along with more sophisticated control of the generation of smis. 5.18.9 usb 2.0 based debug port the pch supports the elimination of the lega cy com ports by providing the ability for new debugger software to interact with devices on a usb 2.0 port. high-level restrictions and features are: ? operational before usb 2.0 drivers are loaded. ? functions even when the port is disabled. ? allows normal system usb 2.0 traffic in a system that may only have one usb port. ? debug port device (dpd) must be high-speed capable and connect directly to port 1 and port 9 on pch-based systems (such as, the dpd cannot be connected to port 1/port 9 through a hub. when a dpd is detected the pch ehci will bypass the integrated rate matching hub and connect directly to the port and the dpd.). ? debug port fifo always makes forward progress (a bad status on usb is simply presented back to software). ? the debug port fifo is only given one usb access per microframe. the debug port facilitates operating system and device driver debug. it allows the software to communicate with an external console using a usb 2.0 connection. because the interface to this link does not go through the normal usb 2.0 stack, it allows communication with the external console during cases where the operating system is not loaded, the usb 2.0 software is broken, or where the usb 2.0 software is being debugged. specific features of th is implementation of a debug port are: ? only works with an external usb 2.0 debug device (console) ? implemented for a specific port on the host controller ? operational anytime the port is not suspended and the host controller is in d0 power state. ? capability is interrupted when port is driving usb reset
functional description 218 datasheet 5.18.9.1 theory of operation there are two operational modes for the usb debug port: 1. mode 1 is when the usb port is in a disabled state from the viewpoint of a standard host controller driver. in mode 1, the debu g port controller is required to generate a ?keepalive? packets less than 2 ms apart to keep the attached debug device from suspending. the keepalive packet should be a standalone 32-bit sync field. 2. mode 2 is when the host controller is running (that is, host controller?s run/stop# bit is 1). in mode 2, the normal transmission of sof packets will keep the debug device from suspending. behavioral rules 1. in both modes 1 and 2, the debug port controller must check for software requested debug transactions at least every 125 microseconds. 2. if the debug port is enabled by the debu g driver, and the standard host controller driver resets the usb port, usb debug transa ctions are held off for the duration of the reset and until after the first sof is sent. 3. if the standard host controller driver suspends the usb port, then usb debug transactions are held off for the duration of the suspend/resume sequence and until after the first sof is sent. 4. the enabled_cnt bit in the debug register space is independent of the similar port control bit in the associated port status and control register. ta b l e 5 - 4 2 shows the debug port behavior relate d to the state of bits in the debug registers as well as bits in the associated port status and control register. table 5-42. debug port behavior owner_cnt enabled_ct port enable run / stop suspend de bug port behavior 0xxxx debug port is not being used. normal operation. 10xxx debug port is not being used. normal operation. 1100x debug port in mode 1. sync keepalives sent plus debug traffic 1101x debug port in mode 2. sof (and only sof) is sent as keepalive. debug traffic is also sent. note that no other norm al traffic is sent out this port, because the port is not enabled. 11100 invalid. host controller driver should never put controller into this state (enabled, not running and not suspended). 1 1 1 0 1 port is suspended. no debug traffic sent. 11110 debug port in mode 2. debug traffic is interspersed with normal traffic. 1 1 1 1 1 port is suspended. no debug traffic sent.
datasheet 219 functional description 5.18.9.1.1 out transactions an out transaction sends data to the debug device. it can occur only when the following are true: ? the debug port is enabled ? the debug software sets the go_cnt bit ? the write_read#_cnt bit is set the sequence of the transaction is: 1. software sets the appropriate values in the following bits: ?usb_address_cnf ?usb_endpoint_cnf ? data_buffer[63:0] ? token_pid_cnt[7:0] ? send_pid_cnt[15:8] ?data_len_cnt ? write_read#_cnt: (note: this will always be 1 for out transactions.) ? go_cnt: (note: this will always be 1 to initiate the transaction.) 2. the debug port controller sends a token packet consisting of: ?sync ? token_pid_cnt field ? usb_address_cnt field ?usb_endpoint_cnt field ? 5-bit crc field 3. after sending the token packet, the debug port controller sends a data packet consisting of: ?sync ? send_pid_cnt field ? the number of data bytes indicated in data_len_cnt from the data_buffer ? 16-bit crc note: a data_len_cnt value of 0 is valid in which case no data bytes would be included in the packet. 4. after sending the data packet, the controller waits for a handshake response from the debug device. ? if a handshake is received, the debug port controller: a. places the received pid in the received_pid_sts field b. resets the error_good#_sts bit c. sets the done_sts bit ? if no handshake pid is received, the debug port controller: a. sets the exception_sts field to 001b b. sets the error_good#_sts bit c. sets the done_sts bit
functional description 220 datasheet 5.18.9.1.2 in transactions an in transaction receives data from the debug device. it can occur only when the following are true: ? the debug port is enabled ? the debug software sets the go_cnt bit ? the write_read#_cnt bit is reset the sequence of the transaction is: 1. software sets the appropriate values in the following bits: ? usb_address_cnf ?usb_endpoint_cnf ? token_pid_cnt[7:0] ?data_len_cnt ? write_read#_cnt: (note: this will always be 0 for in transactions.) ? go_cnt: (note: this will always be 1 to initiate the transaction.) 2. the debug port controller sends a token packet consisting of: ?sync ? token_pid_cnt field ? usb_address_cnt field ? usb_endpoint_cnt field ? 5-bit crc field. 3. after sending the token packet, the debug port controller waits for a response from the debug device. if a response is received: ? the received pid is placed into the received_pid_sts field ? any subsequent bytes are placed into the data_buffer ? the data_len_cnt field is updated to show the number of bytes that were received after the pid. 4. if a valid packet was received from th e device that was one byte in length (indicating it was a handshake packet), then the debug port controller: ? resets the error_good#_sts bit ? sets the done_sts bit 5. if a valid packet was received from the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: ? transmits an ack handshake packet ? resets the error_good#_sts bit ? sets the done_sts bit 6. if no valid packet is received, then the debug port controller: ? sets the exception_sts field to 001b ? sets the error_good#_sts bit ? sets the done_sts bit.
datasheet 221 functional description 5.18.9.1.3 debug software enabling the debug port there are two mutually exclusive conditions that debug software must address as part of its startup processing: ? the ehci has been initialized by system software ? the ehci has not been initialized by system software debug software can determine the current ?ini tialized? state of the ehci by examining the configure flag in the ehci usb 2.0 command register. if this flag is set, then system software has initialized the ehci. othe rwise, the ehci should not be considered initialized. debug software will initialize th e debug port registers depending on the state of the ehci. however, before this can be accomplished, debug software must determine which root usb port is designated as the debug port. determining the debug port debug software can easily determine which us b root port has been designated as the debug port by examining bits 20:23 of the ehci host controller structural parameters register. this 4-bit field represents the numeric value assigned to the debug port (that is, 0001=port 1). debug software startup with non-initialized ehci debug software can attempt to use the debug port if after setting the owner_cnt bit, the current connect status bit in the appropriate (see determining the debug port presence ) portsc register is set. if the current connect status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. if a device is connected to the port, then debug software must reset/enable the port. debug software does this by setting and then clearing the port reset bit the portsc register. to ensure a successful reset, debug software should wait at least 50 ms before clearing the port reset bit. due to possible delays, this bit may not change to 0 immediately; reset is complete when this bi t reads as 0. software must not continue until this bit reads 0. if a high-speed device is attached, the eh ci will automatically set the port enabled/ disabled bit in the portsc register and the debug software can proceed. debug software should set the enabled_cnt bit in the debug port control/status register, and then reset (clear) the port enabled/disabl ed bit in the portsc register (so that the system host controller driver does not see an enabled port when it is first loaded). debug software startup with initialized ehci debug software can attempt to use the debug port if the current connect status bit in the appropriate (see determining the debug port) portsc register is set. if the current connect status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. if a device is connected, then debug software must set the owner_cnt bit and then the enabled_cnt bit in the debug port control/status register.
functional description 222 datasheet determining debug peripheral presence after enabling the debug port functionality, debug software can determine if a debug peripheral is attached by attempting to send data to the debug peripheral. if all attempts result in an error (exception bits in the debug port control/status register indicates a transaction error), then the attached device is not a debug peripheral. if the debug port peripheral is not present, then debug software may choose to terminate or it may choose to wait until a debug peripheral is connected. 5.18.10 ehci caching ehci caching is a power management feature in the usb (ehci) host controllers which enables the controller to execute the schedul es entirely in cache and eliminates the need for the dma engine to access memory when the schedule is idle. ehci caching allows the processor to maintain longer c-state residency times and provides substantial system power savings. 5.18.11 intel ? usb pre-fetch based pause the intel usb pre-fetch based pause is a power management feature in usb (ehci) host controllers to ensure maximum c3/c4 processor power state time with c2 popup. this feature applies to the period schedule, and works by allowing the dma engine to identify periods of idleness and preventing the dma engine from accessing memory when the periodic schedule is idle. typically in the presence of periodic devices with multiple millisecond poll periods, the periodic schedule will be idle for several frames between polls. the intel usb pre-fetch based pause feature is disabled by setting bit 4 of ehci configuration register section 16.2.1 . 5.18.12 function level reset support (flr) the usb ehci controllers support the functi on level reset (flr) capability. the flr capability can be used in conjunction with intel ? virtualization technology. flr allows an operating system in a virtual machine to have complete control over a device, including its initialization, without interferin g with the rest of the platform. the device provides a software interface that enables the operating system to reset the whole device as if a pci reset was asserted. 5.18.12.1 flr steps 5.18.12.1.1 flr initialization 1. a flr is initiated by software writing a ?1? to the initiate flr bit. 2. all subsequent requests targeting the function will not be claimed and will be master abort immediate on the bus. this includes any configuration, i/o or memory cycles, however, the function shall continue to accept completions targeting the function.
datasheet 223 functional description 5.18.12.1.2 flr operation the function will reset all configuration, i/o and memory registers of the function except those indicated otherwise and reset all internal states of the function to the default or initial condition. 5.18.12.1.3 flr completion the initiate flr bit is reset (cleared) when the flr reset is completed. this bit can be used to indicate to the software that the flr reset is completed. note: from the time initiate flr bit is written to 1, software must wait at least 100 ms before accessing the function. 5.18.13 usb overcurrent protection the pch has implemented programmable usb overcurrent signals. the pch provides a total of 8 overcurrent pins to be shared across the 14 ports. four overcurrent signals have been allocated to the ports in each usb device: ? oc[3:0]# for device 29 (ports 0-7) ? oc[7:4]# for device 26 (ports 8-13) each pin is mapped to one or more ports by setting bits in the usbocm1 and usbocm2 registers. see section 10.1.51 and section 10.1.52 . it is system bios? responsibility to ensure that each port is mapped to only one over current pin. operation with more than one overcurrent pin mapped to a port is undefined. it is expected that multiple ports are mapped to a single overcurrent pin, however they should be connected at the port and not at the pch pin. shorting thes e pins together may lead to reduced test capabilities. by default, two ports are routed to each of the oc[6:0]# pins. oc7# is not used by default. notes: 1. all usb ports routed out of the package must have overcurrent protection. it is system bios responsibility to ensure all used ports have oc protection 2. usb ports that are unused on the system (not routed out from the package) should not have oc pins assigned to them
functional description 224 datasheet 5.19 integrated usb 2.0 rate matching hub 5.19.1 overview the pch has integrated two usb 2.0 rate ma tching hubs (rmh). one hub is connected to each of the ehci controllers as shown in figure 5-10 . the hubs convert low and full- speed traffic into high-speed traffic. when the rmhs are enabled, they will appear to software like an external hub is connected to port 0 of each ehci controller. in addition, port 1 of each of the rmhs is multiplexed with port 1 of the ehci controllers and is able to bypass the rmh for use as the debug port. the hub operates like any usb 2.0 discret e hub and will consume one tier of hubs allowed by the usb 2.0 specification. section 4.1.1. a maximum of four additional non- root hubs can be supported on any of th e pch usb ports. the rmh will report the following vendor id = 8087h and product id = 0024h. 5.19.2 architecture a hub consists of three components: the hub repeater, the hub controller, and the transaction translator. 1. the hub repeater is responsible for connectivity setup and tear-down. it also supports exception handling, such as bus fault detection and recovery and connect/ disconnect detect. 2. the hub controller provides the mechanism for host-to-hub communication. hub- specific status and control commands perm it the host to configure a hub and to monitor and control its individual downstream facing ports. 3. the transaction translator (tt) responds to high-speed split transactions and translates them to full-/low-speed tran sactions with full-/low-speed devices attached on downstream facing ports. there is 1 tt per rmh in the pch. see chapter 11 of the usb 2.0 specification fo r more details on the architecture of the hubs. figure 5-10. ehci with usb 2.0 with rate matching hub
datasheet 225 functional description 5.20 smbus controller (d31:f3) the pch provides an system management bu s (smbus) 2.0 host controller as well as an smbus slave interface. the host controller provides a mechanism for the processor to initiate communications with smbus peripherals (slaves). the pch is also capable of operating in a mode in which it can communicate with i 2 c compatible devices. the pch can perform smbus messages with either packet error checking (pec) enabled or disabled. the actual pec calculation and checking is performed in hardware by the pch. the slave interface allows an external master to read from or write to the pch. write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. the pch?s internal host controller cannot access the pch?s internal slave interface. the pch smbus logic exists in device 31:func tion 3 configuration space, and consists of a transmit data path, and host controller. the transmit data path provides the data flow logic needed to implement the seven different smbus command protocols and is controlled by the host controller. the pch?s smbus controller logic is clocked by rtc clock. the smbus address resolution protocol (arp) is supported by using the existing host controller commands through software, except for the new host notify command (which is actually a received message). the programming model of the host controlle r is combined into two portions: a pci configuration portion, and a system i/o mapped portion. all static configuration, such as the i/o base address, is done usin g the pci configuration space. real-time programming of the host interface is done in system i/o space. the pch smbus host controller checks for parity errors as a target. if an error is detected, the detected parity error bit in the pci status register (device 31:function 3:offset 06h:bit 15) is set. if bit 6 and bit 8 of the pci command register (device 31:function 3:offset 04h) are set, an serr# is generated and the signaled serr# bit in the pci status register (bit 14) is set. 5.20.1 host controller the smbus host controller is used to send commands to other smbus slave devices. software sets up the host controller with an address, command, and, for writes, data and optional pec; and then tells the controlle r to start. when the controller has finished transmitting data on writes, or receiving data on reads, it generates an smi# or interrupt, if enabled. the host controller supports 8 command protocols of the smbus interface (see system management bus (smbus) specification, version 2.0 ): quick command, send byte, receive byte, write byte/word, read byte/word, process call, block read/write, block write?block read process call, and host notify. the smbus host controller requires that the various data and command fields be setup for the type of command to be sent. when so ftware sets the start bit, the smbus host controller performs the requested transa ction, and interrupts the processor (or generates an smi#) when the transaction is completed. once a start command has been issued, the values of the ?active re gisters? (host control, host command, transmit slave address, data 0, data 1) should not be changed or read until the interrupt status message (intr) has been set (indicating the completion of the command). any register values needed for co mputation purposes should be saved prior to issuing of a new command, as the smbus host controller updates all registers while completing the new command.
functional description 226 datasheet the pch supports the system management bus (smbus) specification, version 2.0 . slave functionality, including the host notify protocol, is available on the smbus pins. the smlink and smbus signals can be tied to gether externally depending on tco mode used. refer to section 5.14.2 for more details. using the smb host controller to send commands to the pch smb slave port is not supported. 5.20.1.1 command protocols in all of the following commands, the host status register (offset 00h) is used to determine the progress of the command. while the command is in operation, the host_busy bit is set. if the command completes successfully, the intr bit will be set in the host status register. if the device does not respond with an acknowledge, and the transaction times out, the dev_err bit is set. if software sets the kill bit in the host control register while the command is running, the transaction will stop and the failed bit will be set. quick command when programmed for a quick command, the transmit slave address register is sent. the pec byte is never append ed to the quick protocol. software should force the pec_en bit to 0 when performing the quick command. software must force the i2c_en bit to 0 when running this command. see section 5.5.1 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. send byte / receive byte for the send byte command, the transmit slave address and device command registers are sent. for the receive byte command, the transmit slave address register is sent. the data received is stored in the data0 register. software must force the i2c_en bit to 0 when running this command. the receive byte is similar to a send byte, the only difference is the direction of data transfer. see sections 5.5.2 and 5.5.3 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. write byte/word the first byte of a write byte/word access is the command code. the next 1 or 2 bytes are the data to be written. when programmed for a write byte/word command, the transmit slave address, device command, and data0 registers are sent. in addition, the data1 register is sent on a write word command. software must force the i2c_en bit to 0 when running this comm and. see section 5.5.4 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. read byte/word reading data is slightly more complicated th an writing data. first the pch must write a command to the slave device. then it must follow that command with a repeated start condition to denote a read from that device 's address. the slave then returns 1 or 2 bytes of data. software must force the i2c_en bit to 0 when running this command. when programmed for the read byte/word command, the transmit slave address and device command registers are sent. data is received into the data0 on the read byte, and the dat0 and data1 registers on the read word. see section 5.5.5 of the system management bus (smbus) specification, version 2.0 for the format of the protocol.
datasheet 227 functional description process call the process call is so named because a command sends data and waits for the slave to return a value dependent on that data. the pr otocol is simply a write word followed by a read word, but without a second command or stop condition. when programmed for the process call command, the pch transmits the transmit slave address, host command, data0 and data1 registers. data received from the device is stored in the data0 and data1 registers. the process call command with i2c_en set and the pec_en bit set produces undefined results. software must force either i2c_en or pec_en to 0 when runnin g this command. see section 5.5.6 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. note: for process call command, the value written into bit 0 of the transmit slave address register (smb i/o register, offset 04h) needs to be 0. note: if the i2c_en bit is set, the protocol sequence changes slightly: the command code (bits 18:11 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 19 in the sequence). block read/write the pch contains a 32-byte buffer for read and write data which can be enabled by setting bit 1 of the auxiliary control register at offset 0dh in i/o space, as opposed to a single byte of buffering. this 32-byte buffer is filled with write data before transmission, and filled with read data on reception. in the pch, the interrupt is generated only after a transmission or recept ion of 32 bytes, or when the entire byte count has been transmitted/received. note: when operating in i 2 c mode (i2c_en bit is set), the pch will never use the 32-byte buffer for any block commands. the byte count field is transmitted but ignored by the pch as software will end the transfer after all bytes it cares about have been sent or received. for a block write, software must either force the i2c_en bit or both the pec_en and aac bits to 0 when running this command. the block write begins with a slave addre ss and a write condition. after the command code the pch issues a byte count describin g how many more bytes will follow in the message. if a slave had 20 bytes to send, th e first byte would be the number 20 (14h), followed by 20 bytes of data. the byte count may not be 0. a block read or write is allowed to transfer a maximum of 32 data bytes. when programmed for a block write command, the transmit slave address, device command, and data0 (count) registers are sent. data is then sent from the block data byte register; the total data sent being the value stored in the data0 register. on block read commands, the first byte received is stored in the data0 register, and the remaining bytes are stored in the block data byte register. see section 5.5.7 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. note: for block write, if the i2c_en bit is set, the format of the command changes slightly. the pch will still send the number of bytes (o n writes) or receive the number of bytes (on reads) indicated in the data0 register. however, it will not send the contents of the data0 register as part of the message. also, the block write protocol sequence changes slightly: the byte count (bits 27:20 in the bit sequence) are not sent ? as a result, the slave will not acknowledge (bit 28 in the sequence).
functional description 228 datasheet i 2 c read this command allows the pch to perform block reads to certain i 2 c devices, such as serial e 2 proms. the smbus block read supports the 7-bit addressing mode only. however, this does not allow access to devices using the i 2 c ?combined format? that has data bytes after the address. typically these data bytes correspond to an offset (address) within the serial memory chips. note: this command is supported independent of the setting of the i2c_en bit. the i 2 c read command with the pec_en bit set produces undefined results. software must force both the pec_en and aac bit to 0 when running this command. for i 2 c read command, the value written into bit 0 of the transmit slave address register (smb i/o register, offset 04h) needs to be 0. the format that is used for the command is shown in ta b l e 5 - 4 3 . the pch will continue reading data from the peripheral until the nak is received. table 5-43. i 2 c block read bit description 1start 8:2 slave address ? 7 bits 9write 10 acknowledge from slave 18:11 send data1 register 19 acknowledge from slave 20 repeated start 27:21 slave address ? 7 bits 28 read 29 acknowledge from slave 37:30 data byte 1 from slave ? 8 bits 38 acknowledge 46:39 data byte 2 from slave ? 8 bits 47 acknowledge ? data bytes from slave / acknowledge ? data byte n from slave ? 8 bits ? not acknowledge ?stop
datasheet 229 functional description block writeCblock read process call the block write-block read process call is a two-part message. the call begins with a slave address and a write condition. after the command code the host issues a write byte count (m) that describes how many more bytes will be written in the first part of the message. if a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. the write byte count (m) cannot be 0. the second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a re ad bit. the next byte is the read byte count (n), which may differ from the write byte count (m). the read byte count (n) cannot be 0. the combined data payload must not exceed 32 bytes. the byte leng th restrictions of this process call are summarized as follows: ?m ? 1 byte ?n ? 1 byte ?m + n ? 32 bytes the read byte count does not include the pe c byte. the pec is computed on the total message beginning with the first slav e address and using the normal pec computational rules. it is highly recommende d that a pec byte be used with the block write-block read process call. software mu st do a read to the command register (offset 2h) to reset the 32 byte buffer pointe r prior to reading the block data register. note that there is no stop condition before the repeated start condition, and that a nack signifies the end of the read transfer. note: e32b bit in the auxiliary control register must be set when using this protocol. see section 5.5.8 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. 5.20.2 bus arbitration several masters may attempt to get on the bus at the same time by driving the smbdata line low to signal a start condit ion. the pch continuously monitors the smbdata line. when the pch is attempting to drive the bus to a 1 by letting go of the smbdata line, and it samples smbdata low, th en some other master is driving the bus and the pch will stop transferring data. if the pch sees that it has lost arbitration, the condition is called a collision. the pch will set the bus_err bit in the host status register, and if enabled, generate an interrupt or smi#. the processor is responsible for restarting the transaction. when the pch is a smbus master, it drives the clock. when the pch is sending address or command as an smbus master, or data bytes as a master on writes, it drives data relative to the clock it is also driving. it will not start toggling the clock until the start or stop condition meets proper setup and hold time. the pch will also ensure minimum time between smbus transactions as a master. note: the pch supports the same arbitration prot ocol for both the smbus and the system management (smlink) interfaces.
functional description 230 datasheet 5.20.3 bus timing 5.20.3.1 clock stretching some devices may not be able to handle thei r clock toggling at the rate that the pch as an smbus master would like. they have the ca pability of stretching the low time of the clock. when the pch attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time. the pch monitors the smbus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. while the bus is still low, the high time counter must not be enabled. simila rly, the low period of the clock can be stretched by an smbus master if it is not ready to send or receive data. 5.20.3.2 bus time out (the pch as smbus master) if there is an error in the transaction, such that an smbus device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. the pch will discard the cycl e and set the dev_err bit. the time out minimum is 25 ms (800 rtc clocks). the time-out counter inside the pch will start after the last bit of data is transferred by the pch and it is waiting for a response. the 25-ms time-out counter will not count under the following conditions: 1. byte_done_status bit (smbus i/o offset 00h, bit 7) is set 2. the second_to_sts bit (tco i/o offset 06h, bit 1) is not set (this indicates that the system has not locked up). 5.20.4 interrupts / smi# the pch smbus controller uses pirqb# as its interrupt pin. however, the system can alternatively be set up to generate smi# instead of an interrupt, by setting the smbus_smi_en bit (device 31:function 0:offset 40h:bit 1). ta b l e 5 - 4 5 and ta b l e 5 - 4 6 specify how the various enable bits in the smbus function control the generation of the interrupt, host and slave smi, and wake internal signals. the rows in the tables are additive, which means that if more than one row is true for a particular scenario then the results for all of the activated rows will occur. table 5-44. enable for smbalert# event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31:f3:offset 40h, bit 1) smbalert_dis (slave command i/ o register, offset 11h, bit 2) result smbalert# asserted low (always reported in host status register, bit 5) xx xw a k e g e n e r a t e d x1 0 slave smi# generated (smbus_smi_sts) 1 0 0 interrupt generated
datasheet 231 functional description 5.20.5 smbalert# smbalert# is multiplexed with gpio[11]. when enable and the signal is asserted, the pch can generate an interrupt, an smi#, or a wake event from s1?s5. 5.20.6 smbus crc generation and checking if the aac bit is set in the auxiliary contro l register, the pch automatically calculates and drives crc at the end of the transmitted packet for write cycles, and will check the crc for read cycles. it will not transmit the contents of the pec register for crc. the pec bit must not be set in the host control register if this bit is set, or unspecified behavior will result. if the read cycle results in a crc error, the dev_err bit and the crce bit in the auxiliary status register at offset 0ch will be set. table 5-45. enables for smbus slave write and smbus host events event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31:f3:offset 40h, bit 1) event slave write to wake/ smi# command xx wake generated when asleep. slave smi# generated when awake (smbus_smi_sts). slave write to smlink_slave_smi command xx slave smi# generated when in the s0 state (smbus_smi_sts) any combination of host status register [4:1] asserted 0xnone 1 0 interrupt generated 11host smi# generated table 5-46. enables for the host notify command host_notify_intre n (slave control i/o register, offset 11h, bit 0) smb_smi_en (host config register, d31:f3:off40h, bit 1) host_notify_wken (slave control i/o register, offset 11h, bit 1) result 0x 0none xx 1wake generated 1 0 x interrupt generated 11x slave smi# generated (smbus_smi_sts)
functional description 232 datasheet 5.20.7 smbus slave interface the pch smbus slave interface is accessed using the smbus. the smbus slave logic will not generate or handle receiving the pec by te and will only act as a legacy alerting protocol device. the slave interface allows the pch to decode cycles, and allows an external microcontroller to perform specif ic actions. key features and capabilities include: ? supports decode of three types of messages: byte write, byte read, and host notify. ? receive slave address register: this is th e address that the pch decodes. a default value is provided so that the slave interface can be used without the processor having to program this register. ? receive slave data register in the smbus i/o space that includes the data written by the external microcontroller. ? registers that the external microcontroller can read to get the state of the pch. ? status bits to indicate that the smbus sl ave logic caused an interrupt or smi# due to the reception of a message that matched the slave address. ? bit 0 of the slave status register for the host notify command ? bit 16 of the smi status register ( section 13.8.3.8 ) for all others note: the external microcontroller should not a ttempt to access the pch smbus slave logic until either: ? 800 milliseconds after both: rtcrst# is high and rsmrst# is high, or ? the pltrst# deasserts if a master leaves the clock and data bits of the smbus interface at 1 for 50 s or more in the middle of a cycle, the pch slave logic' s behavior is undefined. this is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. note: when an external microcontroller accesses the smbus slave interface over the smbus a translation in the address is needed to accommodate the least significant bit used for read/write control. for example, if the pc h slave address (rcv_slva) is left at 44h (default), the external micro controller would use an address of 88h/89h (write/read).
datasheet 233 functional description 5.20.7.1 format of slave write cycle the external master performs byte write commands to the pch smbus slave i/f. the ?command? field (bits 11:18) indicate which register is being accessed. the data field (bits 20:27) indicate the value that should be written to that register. ta b l e 5 - 4 7 has the values associated with the registers. note: the external microcontroller is responsible to make sure th at it does not update the contents of the data byte registers until they have been read by the system processor. the pch overwrites the old value with any new value received. a race condition is possible where the new value is being writ ten to the register just at th e time it is being read. the pch will not attempt to cover this race condition (that is, unpredictable results in this case). table 5-47. slave write registers register function 0command register. see ta b l e 5 - 4 8 for legal values written to this register. 1?3 reserved 4 data message byte 0 5 data message byte 1 6?7 reserved 8 reserved 9?ffh reserved table 5-48. command types (sheet 1 of 2) command type description 0 reserved 1 wake/smi#. this command wakes the system if it is not already awake. if system is already awake, an smi# is generated. note: the smb_wak_sts bit will be set by this command, even if the system is already awake. the smi handle r should then clear this bit. 2 unconditional powerdown. this command sets the pwrbtnor_sts bit, and has the same effect as the powerbutton override occurring. 3 hard reset without cycling: this command causes a hard reset of the system (does not include cycling of the power supply). this is equivalent to a write to the cf9h register with bits 2:1 set to 1, but bit 3 set to 0. 4 hard reset system. this command causes a ha rd reset of the system (including cycling of the power supply). this is equivalent to a write to the cf9h register with bits 3:1 set to 1. 5 disable the tco messages. this command will disable the pch from sending heartbeat and event mess ages (as described in section 5.14 ). once this command has been executed, heartbea t and event messag e reporting can only be re-enabled by assertion an d deassertion of the rsmrst# signal. 6 wd reload: reload watchdog timer. 7 reserved
functional description 234 datasheet 5.20.7.2 format of read command the external master performs byte read co mmands to the pch smbus slave interface. the ?command? field (bits 18:11) indicate which register is being accessed. the data field (bits 30:37) contain the value that should be read from that register. 8 smlink_slv_smi. when the pch detects this co mmand type while in the s0 state, it sets the smli nk_slv_smi_sts bit (see section 13.9.5 ). this command should only be used if the system is in an s0 state. if the message is received during s1?s5 states, the pch acknowledges it, but the smlink_slv_smi_sts bit does not get set. note: it is possible that the system transitions out of the s0 state at the same time that the smlink_slv_smi command is received. in this case, the smlink_slv_smi_sts bit may get set but not serviced before the system goes to sleep. once the system returns to s0, the smi associated with this bit would then be generated. software must be able to handle this scenario. 9?ffh reserved. table 5-48. command types (sheet 2 of 2) command type description table 5-49. slave read cycle format bit description driven by comment 1 start external microcontroller 2-8 slave address - 7 bits external microcontroller must match value in receive slave address register 9 write external microcontroller always 0 10 ack pch 11-18 command code ? 8 bits external microcontroller indicates which register is being accessed. see ta b l e 5 - 5 0 for a list of implemented registers. 19 ack pch 20 repeated start external microcontroller 21-27 slave address - 7 bits external microcontroller must match value in receive slave address register 28 read external microcontroller always 1 29 ack pch 30-37 data byte pch value depends on register being accessed. see ta b l e 5 - 5 0 for a list of implemented registers. 38 not ack external microcontroller 39 stop external microcontroller
datasheet 235 functional description table 5-50. data values for slave read registers (sheet 1 of 2) register bits description 07:0 reserved for capabilities indication. should always return 00h. future chips may return another value to indicate different capabilities. 1 2:0 system power state 000 = s0 001 = s1 010 = reserved 011 = s3 100 = s4 101 = s5 110 = reserved 111 = reserved 7:3 reserved 2 3:0 reserved 7:4 reserved 3 5:0 watchdog timer current value note that watchdog timer has 10 bits, but this field is only 6 bits. if the current value is grea ter than 3fh, the pch will always report 3fh in this field. 7:6 reserved 4 0 1 = the intruder detect (intrd_det) bit is set. this indicates that the system cover has probably been opened. 1 1 = bti temperature event occurred. this bit will be set if the pch?s thrm# input signal is active. else this bit will read ?0.? 2 doa processor status . this bit will be 1 to indicate that the processor is dead 3 1 = second_to_sts bit set. this bit will be set after the second time- out (second_to_sts bit) of the watchdog timer occurs. 6:4 reserved. will always be 0, but software should ignore. 7 reflects the value of the gpio[11]/smbalert# pin (and is dependent upon the value of the gpi_inv[11] bit. if the gpi_inv[11] bit is 1, then the value in this bit equals the level of the gpi[11]/smbalert# pin (high = 1, low = 0). if the gpi_inv[11] bit is 0, then the value of this bit will equal the inverse of the level of the gpio[11]/smbalert# pin (high = 0, low = 1). 5 0 fwh bad bit. this bit will be 1 to indica te that the fwh read returned ffh, which indicates that it is probably blank. 1 reserved 2 sys_pwrok failure status: this bit will be 1 if the syspwr_flr bit in the gen_pmcon_2 register is set. 3 init3_3v# due to receiving shutdown message: this event is visible from the reception of the shutdown message until a platform reset is done if the shutdown policy sele ct bit (sps) is configured to drive init3_3v#. when the sps bit is configured to generate pltrst# based on shutdown, this register bit will always return 0. events on signal will not create a event message 4 reserved 5 power_ok_bad: indicates the failure core power well ramp during boot/resume. this bit will be active if the slp_s3# pin is deasserted and pwrok pin is not asserted. 6 thermal trip: this bit will shadow the state of processor thermal trip status bit (cts) (16.2.1.2, gen_pmcon_2, bit 3). events on signal will not create a event message 7 reserved: default value is ?x? note: software should not expect a consistent value when this bit is read through smbus/smlink
functional description 236 datasheet 5.20.7.2.1 behavioral notes according to smbus protocol, read and write messages always begin with a start bit ? address? write bit sequence. when the pch detects that the address matches the value in the receive slave address register, it will assume that the protocol is always followed and ignore the write bit (bit 9) and signal an acknowledge during bit 10. in other words, if a start ?address?read occurs (which is illegal for smbus read or write protocol), and the address matches the pch?s slave address, the pch will still grab the cycle. also according to smbus protocol, a read cycle contains a repeated start?address? read sequence beginning at bit 20. once again, if the address matches the pch?s receive slave address, it will assume that th e protocol is followed, ignore bit 28, and proceed with the slave read cycle. note: an external microcontroller must not attempt to access the pch?s smbus slave logic until at least 1 second after both rtcr st# and rsmrst# are deasserted (high). 5.20.7.3 slave read of rtc time bytes the pch smbus slave interface allows external smbus master to read the internal rtc?s time byte registers. the rtc time bytes are internally latched by the pch?s hardware whenever rtc time is not changing and smbus is idle. this ensures that the time byte delivered to the slave read is always valid and it does not change when the read is still in progress on the bus. the rtc time will change whenever hardware update is in progress, or there is a software write to the rtc time bytes. the pch smbus slave interface only supports byte read operation. the external smbus master will read the rtc time bytes one after another. it is software?s responsibility to check and manage the possible time rollover when subsequent time bytes are read. 67:0 contents of the messag e 1 register. refer to section 13.9.8 for the description of this register. 77:0 contents of the messag e 2 register. refer to section 13.9.8 for the description of this register. 87:0 contents of the tco_wdcnt register. refer to section 13.9.9 for the description of this register. 9 7:0 seconds of the rtc a 7:0 minutes of the rtc b7:0hours of the rtc c 7:0 ?day of week? of the rtc d 7:0 ?day of month? of the rtc e 7:0 month of the rtc f7:0year of the rtc 10h?ffh 7:0 reserved table 5-50. data values for slave read registers (sheet 2 of 2) register bits description
datasheet 237 functional description for example, assuming the rtc time is 11 hours: 59 minutes: 59 seconds. when the external smbus master reads the hour as 11, then proceeds to read the minute, it is possible that the rollover happens between the reads and the minute is read as 0. this results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. unless it is certain that rollover will not occur, software is required to detect the possible time rollover by reading multiple times such th at the read time by tes can be adjusted accordingly if needed. 5.20.7.4 format of host notify command the pch tracks and responds to the standard host notify command as specified in the system management bus (smbus) specification, version 2.0. the host address for this command is fixed to 0001000b. if the pch al ready has data for a previously-received host notify command which has not been serviced yet by the host software (as indicated by the host_notify_sts bit), then it will nack following the host address byte of the protocol. this allows the host to communicate non-acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt. note: host software must always clear the host_notify_sts bit after completing any necessary reads of the address and data registers. ta b l e 5 - 5 1 shows the host notify format. table 5-51. host notify format bit description driven by comment 1 start external master 8:2 smb host address ? 7 bits external master always 0001_000 9 write external master always 0 10 ack (or nack) pch pch nacks if host_notify_sts is 1 17:11 device address ? 7 bits external master indicates the address of the master; loaded into the notify device address register 18 unused ? always 0 external master 7-bit-only address; th is bit is inserted to complete the byte 19 ack pch 27:20 data byte low ? 8 bits external master loaded into the notify data low byte register 28 ack pch 36:29 data byte high ? 8 bits external master loaded into the notify data high byte register 37 ack pch 38 stop external master
functional description 238 datasheet 5.21 thermal management 5.21.1 thermal sensor the pch incorporates one on-die digital thermal sensor (dts) for thermal management. the thermal sensor can provide pch temperature information to an ec or sio device that can be used to determine how to control the fans. this thermal sensor is located near the dm i interface. the on-die thermal sensor is placed as close as possible to the hottest on-die location to reduce thermal gradients and to reduce the error on the sensor trip thresholds. the thermal sensor trip points may be programmed to generate various inte rrupts including sci, smi, pci and other general purpose events. 5.21.1.1 internal ther mal sensor operation the internal thermal sensor reports four trip points: aux2, aux, hot and catastrophic trip points in the order of increasing temperature. aux, aux2 temperature trip points these trip points may be set dynamically if desired and provides an interrupt to acpi (or other software) when it is crossed in ei ther direction. these auxiliary temperature trip points do not automatically cause any hardware throttling but may be used by software to trigger interrupts. this trip poin t is set below the hot temperature trip point and responses are separately programmable from the hot temperature settings, in order to provide incrementally more aggressi ve actions. aux and aux2 trip points are fully software programmable during system ru n-time. aux2 trip point is set below the aux temperature trip point. hot temperature trip point this trip point may be set dynamically if de sired and provides an interrupt to acpi (or other software) when it is crossed in either direction. software could optionally set this as an interrupt when the temperature exceeds this level setting. hot trip does not provide any default hardware based thermal throttling, and is available only as a customer configurable interrupt when t j,max has been reached. catastrophic trip point this trip point is set at the temperature at which the pch must be shut down immediately without any software support. the catastrophic trip point must correspond to a temperature ensured to be functional in order for the interrupt generation and hardware response. hardware response usin g thermtrip# would be an unconditional transition to s5. the catastrophic transition to the s5 state does not enforce a minimum time in the s5 state. it is assu med that the s5 residence and the reboot sequence cools down the system. if the catastrophic condition remains when the catastrophic power down enable bit is set by bios, then the system will re-enter s5. thermometer mode the thermometer is implemented using a counter that starts at 0 and increments during each sample point until the comparator indicates the temperature is above the current value. the value of the counter is loaded into a read-only register (thermal sensor thermometer read) when the comparator first trips.
datasheet 239 functional description 5.21.1.1.1 recommended programm ing for available trip points there may be a 2 c offset due to ther mal gradient between the hot-spot and the location of the thermal sensor. trip points should be programmed to account for this temperature offset between the hot-spot t j,max and the thermal sensor. aux trip points should be programmed for software and firmware control using interrupts. hot trip point should be set to throttle at 108 c (t j,max ) due to dts trim accuracy adjustments. hot trip points should also be programmed for a software response. catastrophic trip point should be set to halt operation to avoid maximum t j of about 120 ? c. note: crossing a trip point in either direction may generate several types of interrupts. each trip point has a register that can be programm ed to select the type of interrupt to be generated. crossing a trip point is implemented as edge detection on each trip point to generate the interrupts. 5.21.1.1.2 thermal sensor accuracy (t accuracy ) t accuracy for the pch is 5 c in the temperature range 90 c to 120 c. t accuracy is 10 c for temperatures from 45 c ? 90 c. the pch may not operate above +108 c. this value is based on product characterization and is not ensured by manufacturing test. software has the ability to program the tcat, thot, and taux trip points, but these trip points should be selected with considerat ion for the thermal sensor accuracy and the quality of the platform thermal solution. overly conservative (unnecessarily low) temperature settings may unnecessarily degrade performance due to frequent throttling, while overly aggressive (dangerously high) temperature settings may fail to protect the part against permanent thermal damage. 5.21.2 pch thermal throttling occasionally the pch may operate in conditions that exceed its maximum operating temperature. in order to protect itself and the system from thermal failure, the pch is capable of reducing its overall power consumption and as a result, lower its temperature. this is achieved by: ? forcing the sata device and inte rface in to a lower power state ? reducing the number of active lanes on the dmi interface ? reducing the intel manageability engine (intel me) clock frequency
functional description 240 datasheet the severity of the throttling response is de fined by four global pch throttling states referred to as t-states. in each t-state, th e throttling response will differ per interface, but will operate concurrently when a global t-state is activated. a t-state corresponds to a temperature range. the t-states are defined in ta b l e 5 - 5 2 . enabling of this feature requires appropri ate intel manageability engine firmware and configuration of the following registers shown in ta b l e 5 - 5 3 . 5.21.3 thermal reporting over system management link 1 interface (smlink1) smlink1 interface in the pch is the smbus lin k to an optional external controller. a smbus protocol is defined on the pch to allow compatible devices such as embedded controller (ec) or sio to obtain system thermal data from sensors integrated into components on the system using the smli nk1 interface. the sensors that can be monitored using the smlink1 include those in the processor, pch and dimms with sensors implemented. this solution allows an external device or controller to use the system thermal data for system thermal management. note: to enable thermal reporting, the thermal data reporting enable and pch/dimm temperature read enables have to be se t in the thermal reporting control (trc) register (see section 22.2 for details on register) there are two uses for the pch's thermal reporting capability: 1. to provide system thermal data to an external controller. the controller can manage the fans and other cooling elements based on this data. in addition, the pch can be programmed by setting appropriate bits in the alert enable (ae) register (see section 22.2 for details on this register) to alert the controller when a device has gone outside of its temperature limits. the alert causes the assertion of the pch temp_alert# (sata5gp/gpi o49/temp_alert#) signal. see section 5.21.3.6 for more details. 2. to provide an interface between the exte rnal controller and host software. this software interface has no direct affect on the pch's thermal collection. it is strictly a software interface to pass information or data. the pch responds to thermal requests only wh en the system is in s0 or s1. once the pch has been programmed, it will start respon ding to a request while the system is in s0 or s1. table 5-52. pch thermal throttle states (t-states) state description t0 normal operation, temperature is less than the t1 trip point temperature t1 temperature is greater than or equal to the t1 trip point temperature, but less than the t2 trip point temperature. the default temperature is tj,max at 108 c t2 temperature is greater than or equal to the t2 trip point temperature, but less than the t3 trip point temperature. the default temperature is 112 c t3 temperature is greater than or equal to the t3 trip point temperature. the default temperature is 116 c table 5-53. pch thermal thrott ling configuration registers register name register location tt ? thermal throttling tbarb+6ch section 22.2.15
datasheet 241 functional description to implement this thermal reporting capability, the platform is required to have appropriate intel me firmware, bios support, and compatible devices that support the smbus protocol. 5.21.3.1 supported addresses the pch supports 2 addresses: i 2 c address for writes and block read address for reads. these addresses need to be distinct. the two addresses may be fixed by the extern al controller, or programmable within the controller. the addresses used by the pch are completely programmable. 5.21.3.1.1 i 2 c address this address is used for writes to the pch. ? the address is set by soft straps which are values stored in spi flash and are defined by the oem. the address can be set to any value the platform requires. ? this address supports all the writes listed in ta b l e 5 - 5 4 . ? smbus reads by the external controller to this address are not allowed and result in indeterminate behavior. 5.21.3.1.2 block read address this address is used for reads from the pch. ? the address is set by soft straps or bios. it can be set to any value the platform requires. ? this address only supports smbus bloc k read command and not byte or word read. ? the block read command is supported as defined in the smbus 2.0 specification, with the command being 40h, and the by te count being provided by the pch following the block read format in the smbus specification. ? writes are not allowed to this address, and result in indeterminate behavior. ? packet error code (pec) may be enable d or not, which is set up by bios.
functional description 242 datasheet 5.21.3.2 i 2 c write commands to the intel ? me ta b l e 5 - 5 4 lists the write commands supported by the intel me. all bits in the write commands must be wr itten to the pch or the operation will be aborted. for example, for 6-bytes write comma nds, all 48 bits must be written or the operation will be aborted. the command format follows the block write format of the smbus specification. 5.21.3.3 block read command the external controller may read thermal information from the pch using the smbus block read command. byte-read and word-read smbus commands are not supported. note that the reads use a different address than the writes. the command format follows the block read format of the smbus specification. the pch and external controller are set up by bios with the length of the read that is supported by the platform. the device must always do reads of the lengths set up by bios. the pch supports any one of the following lengths: 2, 4, 5, 9, 10, 14 or 20 bytes. the data always comes in the order described in ta b l e 5 - 5 4 , where 0 is the first byte received in time on the smbus. table 5-54. i 2 c write commands to the intel ? me transaction slave addr data byte0 (command) data byte 1 (byte count) data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 write processor te m p l i m i t s i 2 c 42h 4h lower limit [15:8] lower limit [7:0] upper limit [15:8] upper limit [7:0] write pch te m p l i m i t s i 2 c 44h 2h lower limit [7:0] upper limit [7:0] write dimm te m p l i m i t s i 2 c 45h 2h lower limit [7:0] upper limit [7:0]
datasheet 243 functional description a 2-byte read would provide both the pch and processor temperature. a device that wants dimm information would read 9 bytes. table 5-55. block read co mmand C byte definition byte definition byte 0 processor package temperature, in absolute degrees celsius (c). this is not relative to some max or limit, but is the maximum in absolute degrees. if the processor temperature collection has errors, this field will be ffh. read value represents bits [7:0] of ptv (processor temperature value) byte 1 the pch temp in degrees c. ffh indicates error condition. read value represents bits [7:0] of itv (internal temperature values) register described in section 22.2 . note: requires trc (thermal reporting co ntrol) register bit [5] to be enabled. see section 22.2 . byte 3:2 reserved byte 4 reserved byte 5 thermal sensor (ts) on dimm 0 if dimm not populated, or if there is no ts on dimm, value will be 0h read value represents bits[7:0] of dtv (dimm temperature values) register described in section 22.2 . note: requires trc (thermal reporting co ntrol) register bit [0] to be enabled. see section 22.2 . byte 6 thermal sensor (ts) on dimm 1 if dimm not populated, or if there is no ts on dimm, value will be 0h read value represents bits[15:8] of dtv (dimm temperature values) register described in section 22.2 . note: requires trc (thermal reporting co ntrol) register bit [1] to be enabled. see section 22.2 . byte 7 thermal sensor (ts) on dimm 2 if dimm not populated, or if there is no ts on dimm, value will be 0h. read value represents bits[23:16] of dtv (dimm temperature values) register described in section 22.2 . note: requires trc (thermal reporting co ntrol) register bit [2] to be enabled. see section 22.2 . byte 8 thermal sensor (ts) on dimm 3 if dimm not populated, or if there is no ts on dimm, value will be 0h. read value represents bits[31:24] of dtv (dimm temperature values) register described in section 22.2 . note: requires trc (thermal reporting co ntrol) register bit [3] to be enabled. byte 9 sequence number. can be used to check if the pch's fw or hw is hung. see section 5.21.3.9 for usage. this byte is updated every time the collected data is updated read value represents bits[23:16] of itv (internal temperature values) register described in section 22.2 . byte 19:10 reserved
functional description 244 datasheet 5.21.3.4 read data format for each of the data fields an error code is listed below. this code indicates that the pch failed in its access to the device. this would be for the case where the read returned no data, or some illegal value. in general that would mean the device is broken. the ec can treat the device that failed the read as broken or with some fail- safe mechanism. 5.21.3.4.1 pch and dimm temperature the temperature readings for the pch, dimm are 8-bit unsigned values from 0?255. the minimum granularity supported by the inte rnal thermal sensor is 1 c. thus, there are no fractional values for the pch or dimm temperatures. note the sensors used within the components do not support values below 0 degrees, so this field is treated as 8 bits (0?255) absolute and not 2's complement (-128 to 127). devices that are not present or that are disabled will be set to 0h. devices that have a failed reading (that is, the read from the device did not return any legal value) will be set to ffh. a failed reading means that the attempt to read that device returned a failure. the failure could have been from a bu s failure or that the device itself had an internal failure. for instance, a system may only have one dimm and it would report only that one value, and the values for the other dimms would all be 00h. 5.21.3.5 thermal data update rate the temperature values are updated every 200 ms in the pch, so reading more often than that simply returns the same data mult iple times. also, the data may be up to 200 ms old if the external controller reads the data right before the next update window. 5.21.3.6 temperature comparator and alert the pch has the ability to alert the external controller when temperatures are out of range. this is done using the pch temp_alert# signal. the alert is a simple comparator. if any device's temperature is outside the limit range for that device, then the signal is asserted (electrical low). note that this alert does not use the sml1alert#. the pch supports 4 ranges: 1. pch range - upper and lower limit (8 bits each, in degrees c) for the pch temperature. 2. dimm range - upper and lower limit (8 bits each, in degrees c), applies to all dimms (up to 4 supported) that are enable d. disabled (unpopulated) dimms do not participate in the thermal compares. 3. processor package range - upper and lower limit (8 bits each, in degrees c) the comparator checks if the device is with in the specified range, including the limits. for example, a device that is at 100 degrees when the upper limit is 100 will not trigger the alert. likewise, a device that is at 70 degrees when the lower limit is 70 will not trigger the alert. the compares are done only on devices that have been enabled by bios for checking. since bios knows how many dimms are in the system, it enables the checking only for those devices that are physically present. the compares are done in firmware, so all the compares are executed in one software loop and at the end, if there is any out of bound temperature, the pch?s temp_alert# signal is asserted.
datasheet 245 functional description when the external controller sees the temp_alert# signal low, it knows some device is out of range. it can read the temperatures and then change the limits for the devices. note that it may take up to 250 ms before the actual writes cause the signal to change state. for instance if the pch is at 105 degrees and the limit is 100, the alert is triggered. if the controller changes the limits to 110, the temp_alert# signal may remain low until the next thermal sampling window (every 200 ms) occurs and only then go high, assuming the pch was still within its limits. at boot, the controller can monitor the temp_alert# signal state. when bios has finished all the initialization and enab led the temperature comparators, the temp_alert# signal will be asserted since the default state of the limit registers is 0h; hence, when the pch first reads temperatures, they will be out of range. this is the positive indication that the external cont roller may now read thermal information and get valid data. if the temp_alert# signal is enabled and not asserted within 30 seconds after pltrst#, the external controlle r should assume there is a fatal error and handle accordingly. in general the temp _alert# signal will assert within a 1?4 seconds, depending on the actual bios implementation and flow. note: the temp_alert# assertion is only valid wh en pltrst# is deasserted. the controller should mask the state of this signal when pltrst# is asserted. since the controller may be powered even when the pch and the re st of the platform are not, the signal may glitch as power is being asserted; thus, the controller should wait until pltrst# has deasserted before monitoring the signal. 5.21.3.6.1 special conditions the external controller should have a graceful means of handling the following: 1. temp_alert# asserts, and the controller reads pch, but all temperature values are within limits. in this case, the controller should assume that by the time the controller could read the data, it had changed and moved back within the limits. 2. external controller writes new values to temperature limits, but temp_alert# is still asserted after several hundred msecs. when read, the values are back within limits. in this case, the controller should treat this as case where the temperature changed and caused temp_alert# assertion, and then changed again to be back within limits. 3. there is the case where the external controller writes an update to the limit register, while the pch is collecting the thermal information and updating the thermal registers. the limit change will on ly take affect when the write completes and the intel ? me can process this change. if the intel ? me is already in the process of collecting data and doing the co mpares, then it will continue to use the old limits during this round of compares, and then use the new limits in the next compare window. 4. each smbus write to change the limits is an atomic operation, but is distinct in itself. therefore the external controller could write pch limit, and then write dimm limit. in the middle of those 2 writes, the thermal collecting procedure could be called by the intel ? me, so that the comparisons for the limits are done with the new pch limits but the old dimm limits. note: the limit writes are done when the smbus wr ite is complete; therefore, the limits are updated atomically with respect to the thermal updates and compares. there is never a case where the compares and the thermal upda te are interrupted in the middle by the write of new limits. the thermal updates and compares are done as one non- interruptible routine, and then the limit writ es would change the limit value outside of that routine.
functional description 246 datasheet 5.21.3.7 bios set up in order for the pch to properly report temperature and enable alerts, the bios must configure the pch at boot or from suspen d/resume state by writing the following information to the pch mmio space. this in formation is not configurable using the external controller. ? enables for each of the possible thermal alerts (pch and dimm). note that each dimm is enabled individually. ? enables for reading dimm and pch temperatures. note that each can be enabled individually. ? smbus address to use for each dimm. setting up the temperature calculation equations. 5.21.3.8 smbus rules the pch may nack an incoming smbus transa ction. in certain cases the pch will nack the address, and in other cases it will nack the command depending on internal conditions (such as errors, busy conditions). given that most of the cases are due to internal conditions, the external controller must alias a nack of the command and a nack of the address to the same behavior. the controller must not try to make any determination of the reason for the nack, based on the type of nack (command vs. address). the pch will nack when it is enabled but bu sy. the external controller is required to retry up to 3 times when they are nack'ed to determine if the fw is busy with a data update. when the data values are being update d by the intel me, it will force this nack to occur so that the data is atomically updated to the external controller. in reality if there is a nack because of the pch being busy, in almost all cases the next read will succeed since the update internally takes very little time. the only long delay where there can be a nack is if the internal intel me engine is reset. this is due to some extreme error condition and is therefore rare. in this case the nack may occur for up to 30 seconds. after that, the external controller must assume that the pch will never return good da ta. even in the best of cases, when this internal reset occurs, it will always be a second or 2 to re-enable responding. 5.21.3.8.1 during block read on the block read, the pch will respect th e nack and stop indications from the external controller, but will consider this an error case. it will recover from this case and correctly handle the next smbus request. the pch will honor stop during the block re ad command and cease providing data. on the next block read, the data will start with byte 0 again. however, this is not a recommended usage except for 'emergency cases'. in general the external controller should read the entire length of da ta that was originally programmed. 5.21.3.8.2 power on on the block read, the pch will respect th e nack and stop indications from the external controller, but will consider this an error case. it will recover from this case and correctly handle the next smbus request. the pch will honor stop during the block re ad command and cease providing data. on the next block read, the data will start with byte 0 again. however, this is not a recommended usage except for 'emergency cases'. in general the external controller should read the entire length of da ta that was originally programmed.
datasheet 247 functional description 5.21.3.9 case for considerations below are some corner cases and some possible actions that the external controller could take. note that a 1-byte sequence number is av ailable to the data read by the external controller. each time the pch updates the thermal information it will increment the sequence number. the external controller can use this value as an indication that the thermal fw is actually operating. note that the sequence number will roll over to 00h when it reaches ffh. 1. power on: the pch will not respond to any smbus activity (on smlink1 interface) until it has loaded the thermal firmware (fw), which in general would take 1?4 seconds. during this peri od, the pch will nack any sm bus transaction from the external controller. the load should take 1-4 seconds, but the external controller should design for 30 seconds based on long delays for s4 resume which takes longer than normal power up. this would be an extreme case , but for larger memory footprints and non-optimized recovery times, 30 seconds is a safe number to use for the time- out. recover/failsafe: if the pch has not responded within 30 seconds, the external controller can assume that the system has had a major error and the external controller should ramp the fans to some reasonably high value. the only recover from this is an internal reset on the pch, which is not visible to the external controller. therefore the external controller might choose to poll every 10-60 seconds (some fairly long period) hereafter to see if the pch's thermal reporting has come alive. 2. the pch thermal fw hangs and requires an internal reset which is not visible to the external controller. the pch will nack any smbus transaction from the external controller. the pch may not be able to respond for up to 30 seconds while the fw is being reset and reconfigured. the external controller could choose to poll every 1-10 seconds to see if the thermal fw has been successfully reset and is now providing data. general recovery for this case is about 1 second, but 30 seconds should be used by the external controller at the time-out. recovery/failsafe: same as in case #1. 3. fatal pch error, causes a global reset of all components. when there is a fatal pch error, a global reset may occur, and then case #1 applies. the external controller can observe, if desired, pltrst# assertion as an indication of this event. 4. the pch thermal fw fails or is hung, but no reset occurs the sequence number will not be updated, so the external controller knows to go to failsafe after some number of read s (8 or so) return the same sequence number. the external controller could choose to poll every 1-10 seconds to see if the thermal fw has been successfully reset and working again. in the absence of other errors, the updates for the sequence number should never be longer than 400 ms, so the num ber of reads needed to indicate that there is a hang should be at around 2 se conds. but when there is an error, the sequence number may not get updated for seconds. in the case that the
functional description 248 datasheet external controller sees a nack from the pch, then it should restart its sequence counter, or otherwise be aware that the nack condition needs to be factored into the sequence number usage. the use of sequence numbers is not requ ired, but is provided as a means to ensure correct pch fw operation. 5. when the pch updates the block read data structure, the external controller gets a nack during this period. to ensure atomicity of the smbus data read with respect to the data itself, when the data buffer is being updated, the pc h will nack the block read transaction. the update is only a few micro-seconds, so very short in terms of smbus polling time; therefore, the next read should be successful. the external controller should attempt 3 reads to handle this condition before moving on. if the block read has started (that is, the address is ack'ed) then the entire read will complete successfully, and the pch will update the data only after the smbus read has completed. 6. system is going from s0 to s3/4/5. note that the thermal monitoring fw is fully operational if the system is in s0/s1, so the following only applies to s3/4/5. when the pch detects the os request to go to s3/4/5, it will take the smlink1 controller offline as part of the system preparation. the external controller will see a period where its transactions are getting nack'ed, and then see slp_s3# assert. this period is relatively short (a couple of seconds depending on how long all the devices take to place themselves into the d3 state), and would be far less than the 30 second limit mentioned above. 7. temp_alert# ? since there can be an in ternal reset, the temp_alert# may get asserted after the reset. the external co ntroller must accept this assertion and handle it. 5.21.3.9.1 example algorithm for handling transaction one algorithm for the transaction handling could be summarized as follows. this is just an example to illustrate the above rules. there could be other algorithms that can achieve the same results. 1. perform smbus transaction. 2. if ack, then continue 3. if nack a. try again for 2 more times, in case the pch is busy updating data. b. if 3 successive transactions receive nack, then - ramp fans, assuming some general long reset or failure - try every 1-10 seconds to see if smbus transactions are now working - if they start then return to step 1 - if they continue to fail, then stay in this step and poll, but keep the fans ramped up or implement some other failure recovery mechanism.
datasheet 249 functional description 5.22 intel ? high definition au dio overview (d27:f0) the pch high definition audio (hda) controller communicates with the external codec(s) over the intel high definition audio serial link. the controller consists of a set of dma engines that are used to move sa mples of digitally encoded data between system memory and an external codec(s) . the pch implements four output dma engines and 4 input dma engines. the outp ut dma engines move digital data from system memory to a d-a converter in a co dec. the pch implements a single serial data output signal (hda_sdo) that is conn ected to all external codecs. the input dma engines move digital data from the a-d converter in the codec to system memory. the pch implements four serial digital input signals (hda_sdi[3:0]) supporting up to four codecs. audio software renders outbound and processes inbound data to/from buffers in system memory. the location of individual buffers is described by a buffer descriptor list (bdl) that is fetched and processed by the controller. the data in the buffers is arranged in a predefined format. the output dma engines fetch the digital data from memory and reformat it based on the programmed sample rate, bit/sample and number of channels. the data from the ou tput dma engines is then combined and serially sent to the external codecs over th e intel high definition audio link. the input dma engines receive data from the codecs over the intel high definition audio link and format the data based on the programmable attributes for that stream. the data is then written to memory in the predefined format for software to process. each dma engine moves one stream of data. a single codec can accept or generate multiple streams of data, one for each a-d or d-a converter in the codec. multiple codecs can accept the same output stream processed by a single dma engine. codec commands and responses are also transported to and from the codecs using dma engines. the pch hd audio controller supports the function level reset (flr). 5.22.1 intel ? high definition audi o docking (mobile only) 5.22.1.1 dock sequence note that this sequence is followed when the system is running and a docking event occurs. 1. since the pch supports docking, the dock ing supported (dcksts. ds) bit defaults to a 1. post bios and acpi bios software uses this bit to determine if the hd audio controller supports docking. bios may write a 0 to this r/wo bit during post to effectively turn off the docking feature. 2. after reset in the undocked quiescent stat e, the dock attach (dckctl.da) bit and the dock mate (dcksts.dm) bit are both deasserted. the hda_dock_en# signal is deasserted and hda_dock_rst# is asserted. bit clock, sync and sdo signals may or may no be running at the point in time that the docking event occurs. 3. the physical docking event is signaled to acpi bios software using acpi control methods. this is normally done through a gpio signal on the pch and is outside the scope of this section of the specification. 4. acpi bios software first checks that the docking is supported using dcksts.ds=1 and that the dcksts.dm=0 and then initia tes the docking sequence by writing a 1 to the dckctl.da bit.
functional description 250 datasheet 5. the hd audio controller then asserts the hda_dock_en# signal so that the bit clock signal begins toggling to the dock codec. hda_dock_en# shall be asserted synchronously to bit clock and timed such that bit clock is low, sync is low, and sdo is low. pull-down resistors on these signals in the docking station discharge the signals low so that when the state of the signal on both sides of the switch is the same when the switch is turned on. this reduces the potential for charge coupling glitches on these signals. note that in the pch the first 8 bits of the command field are ?reserved? and always driven to 0's. this creates a predictable point in time to always assert hda_dock_en#. note that the hd audio link reset exit specification that requires that sync and sdo be driven low during bit clock startup is not ensured. note also that the sdo and bit clock signals may not be low while hda_dock_rst# is asserted whic h also violates the specification. 6. after the controller asserts hda_dock_e n# it waits for a minimum of 2400 bit clocks (100 s) and then deasserts hda_dock_rst#. this is done in such a way to meet the hd audio link reset exit sp ecification. hda_dock_rst# deassertion should be synchronous to bit clock and timed such that there are least 4 full bit clocks from the deassertion of hda_dock_rst# to the first frame sync assertion. 7. the connect/turnaround/address frame hardware initialization sequence will now occur on the dock codecs' sdi signals. a dock codec is detected when sdi is high on the last bit clock cycle of the frame sync of a connect frame. the appropriate bit(s) in the state change status (statests) register will be set. the turnaround and address frame initialization sequence then occurs on the dock codecs' sdi(s). 8. after this hardware initialization sequence is complete (approximately 32 frames), the controller hardware sets the dcksts.dm bit to 1 indicating that the dock is now mated. acpi bios polls the dcksts.dm bit and when it detects it is set to 1, conveys this to the os through a plug-n-play irp. this eventually invokes the hd audio bus driver, which then begins it's codec discovery, enumeration, and configuration process. 9. alternatively to step #8, the hd audio bus driver may choose to enable an interrupt by setting the wakeen bits for sdins that didn't originally have codecs attached to them. when a corresponding st atests bit gets set an interrupt will be generated. in this case the hd audio bus dr iver is called directly by this interrupt instead of being notified by the plug-n-play irp. 10. intel hd audio bus driver software ?discovers? the dock codecs by comparing the bits now set in the statests register wi th the bits that were set prior to the docking event. 5.22.1.2 exiting d3/crst# when docked 1. in d3/crst#, crst# is asserted by the hd audio bus driver. crst# asserted resets the dock state machines, but does not reset the dckctl.d a bit. because the dock state machines are reset, the dock is electrically isolated (hda_dock_en# deasserted) and dock_rst# is asserted. 2. the bus driver clears the statests bits, then deasserts crst#, waits approximately 7 ms, then checks the statests bits to see which codecs are present. 3. when crst# is deasserted, the dock stat e machine detects that dckctl.da is still set and the controller hardware sequences through steps to electrically connect the dock by asserting hda_dock_en# and th en eventually deasserts dock_rst#. this completes within the 7ms mentioned in step 2). 4. the bus driver enumerates the codecs present as indicated using the statests bits. 5. note that this process did not require bi os or acpi bios to set the dckctl.da bit.
datasheet 251 functional description 5.22.1.3 cold boot/resume from s3 when docked 1. when booting and resuming from s3, pltrst# switches from asserted to deasserted. this clears the dckctl.da bi t and the dock state machines. because the dock state machines are reset, the dock is electrically isolated (hda_dock_en# deasserted) and dock_rst# is asserted. 2. post bios detects that the dock is attach ed and sets the dckctl .da bit to 1. note that at this point crst# is still asserted so the dock state machine will remain in its reset state. 3. the bus driver clears the statests bits, then deasserts crst#, waits approximately 7ms, then checks the statests bits to see which codecs are present. 4. when crst# is deasserted, the dock stat e machine detects that dckctl.da is still set and the controller hardware sequences through steps to electrically connect the dock by asserting hda_dock_en# and th en eventually deasserts dock_rst#. this completes within the 7ms mentioned in step 3). 5. the bus driver enumerates the codecs pr esent as indicated using the statests bits. 5.22.1.4 undock sequence there are two possible undocking scenarios. the first is the one that is initiated by the user that invokes software and gracefully shuts down the dock codecs before they are undocked. the second is referred to as th e ?surprise undock? where the user undocks while the dock codec is running. both of these situations appear the same to the controller as it is not cognizant of the ?s urprise removal?. but both sequences will be discussed here. 5.22.1.5 normal undock 1. in the docked quiescent state, the dock attach (dckctl.da) bi t and the dock mate (dcksts.dm) bit are both asserted. the hda_dock_en# signal is asserted and hda_dock_rst# is deasserted. 2. the user initiates an undock event through the gui interface or by pushing a button. this mechanism is outside the scope of this section of the document. either way acpi bios software will be invo ked to manage the undock process. 3. acpi bios will call the hd audio bus driver software in order to halt the stream to the dock codec(s) prior to electrical undo cking. if the hd audio bus driver is not capable of halting the stream to the dock ed codec, acpi bios will initiate the hardware undocking sequence as described in the next step while the dock stream is still running. from this standpoint, the result is similar to the ?surprise undock? scenario where an audio glitch may occur to the docked codec(s) during the undock process. 4. the acpi bios initiates the hardware un docking sequence by writing a 0 to the dckctl.da bit. 5. the hd audio controller asserts hda_ dock_rst#. hda_dock_rst# assertion shall be synchronous to bit clock. ther e are no other timing requirements for hda_dock_rst# assertion. note that the hd audio link reset specification requirement that the last frame sync be skipped will not be met. 6. a minimum of 4 bit clocks after hda_ dock_rst# the controller will deassert hda_dock_en# to isolate the dock code c signals from the pch hd audio link signals. hda_dock_en# is deasserted synchronously to bit clock and timed such that bit clock, sync, and sdo are low. 7. after this hardware undocking sequence is complete the controller hardware clears the dcksts.dm bit to 0 indicating that the dock is now un-mated. acpi bios software polls dcksts.dm and when it sees dm set, conveys to the end user that physical undocking can proceed. the controller is now ready for a subsequent docking event.
functional description 252 datasheet 5.22.1.6 surprise undock 1. in the surprise undock case the user undocks before software has had the opportunity to gracefully halt the stream to the dock codec and initiate the hardware undock sequence. 2. a signal on the docking connector is connect ed to the switch that isolates the dock codec signals from the pch hd audio link signals (dock_det# in the conceptual diagram). when the undock event begins to occur the switch will be put into isolate mode. 3. the undock event is communicated to the acpi bios using acpi control methods that are outside the scope of this section of the document. 4. acpi bios software writes a 0 to the dc kctl.da bit. acpi bios then calls the hd audio bus driver using plug-n-play irp. the bus driver then posthumously cleans up the dock codec stream. 5. the hd audio controller hardware is oblivio us to the fact that a surprise undock occurred. the flow from this point on is identical to the normal undocking sequence described in section 0 starting at step 3). it finishes with the hardware clearing the dcksts.dm bit set to 0 indicating that the dock is now un-mated. the controller is now ready for a subsequent docking event. 5.22.1.7 interaction between dock /undock and power management states when exiting from s3, pltrst# will be asse rted. the post bios is responsible for initiating the docking sequence if the dock is already attached when pltrst# is deasserted. post bios writes a 1 to the dc kctl.da bit prior to the hd audio driver deasserting crts# and detecting and enumerating the codecs attached to the hda_dock_rst# signal. the hd audio controller does not directly monitor a hardware signal indicating that a dock is attached. therefore a method outside the scope of this document must be used to cause the post bios to initiate the docking sequence. when exiting from d3, crst# will be assert ed. when crst# bit is ?0? (asserted), the dckctl.da bit is not cleared. the dock state machine will be reset such that hda_dock_en# will be deasserted, hd a_dock_rst# will be asserted and the dcksts.dm bit will be cleared to reflect this state. when the crst# bit is deasserted, the dock state machine will detect that dckctl.da is set to ?1? and will begin sequencing through the dock process. note that this does not require any software intervention. 5.22.1.8 relationship between hda_dock_rst# and hda_rst# hda_rst# will be asserted wh en a pltrst# occurs or when the crst# bit is 0. as long as hda_rst# is asserted, the dock_rst# signal will also be asserted. when pltrst# is asserted, the dckctl.da an d dcksts.dm bits will be get cleared to their default state (0's), and the dock state machine will be reset such that hda_dock_en# will be deasserted, and hd a_dock_rst# will be asserted. after any pltrst#, post bios software is responsible for detecting that a dock is attached and then writing a ?1? to the dckctl.da bit prio r to the hd audio bus driver deasserting crst#. when crst# bit is ?0? (asserted), the dckctl.da bit is not cleared. the dock state machine will be reset such that hda_dock _en# will be deasserted, hda_dock_rst# will be asserted and the dcksts .dm bit will be cleared to reflect this state. when the crst# bit is deasserted, the dock state mach ine will detect that dckctl.da is set to ?1? and will begin sequencing through the dock process. note that this does not require any software intervention.
datasheet 253 functional description 5.23 intel ? me and intel ? me firmware 7.0 in 2005 intel developed a set of manageability services called intel ? active management technology (intel ? amt). to increase features and reduce cost in 2006 intel integrated the operating environment fo r intel amt to run on all intel chipsets: ? a microcontroller and support hw was integrated in the mch ? additional support hw resided in ich this embedded operating environment is ca lled the intel manageability engine (intel me). in 2009 with platform repartitioning intel me was designed to reside in the pch. key properties of intel me: ? connectivity ? integration into i/o subsystem of pch ? delivers advanced i/o functions ?security ? more secure (intel root of trust) & isolated execution ? increased security of flash file system ? modularity & partitioning ? osv, vmm & sw independence ? respond rapidly to competitive changes ?power ? always on always connected ? advanced functions in low power s3-s4-s5 operation ? os independent pm & thermal heuristics intel me fw provides a variety of servic es that range from low-level hardware initialization and provisioning to high-level end-user software based it manageability services. one of intel me fw?s most estab lished and recognizable features is intel active management technology. intel ? active management technology is a set of advanced manageability features developed to meet the evolving demands placed on it to manage a network infrastructure. intel ? amt reduces the total cost of ownership (tco) for it management through features such as asset tracking, remote manageability, and robust policy-based security, resulting in fewer desk-side visits and reduced incident support durations. intel amt extends the manageability capability for it through out of band (oob), allowing asset information, remote diagnostics, recovery, and contain capabilities to be available on client systems even when they are in a low power, or ?off? state, or in situations when the operating system is hung. for more details on various intel me fw features supported by intel me fw, such as intel active management technology , please refer to the relevant fw feature product requirements document (prd).
functional description 254 datasheet 5.23.1 intel ? me requirements intel me is a platform-level solution that utilizes multiple system components including: ? the intel me is the general purpose controlle r that resides in the pch. it operates in parallel to, and is resource-isolated from, the host processor. ? the flash device stores intel me firmware code that is executed by the intel me for its operations. in m0, the highest power stat e, this code is loaded from flash into dram and cached in secure and isolated sram. code that resides in dram is stored in 16 mb of unified memory ar chitecture (uma) memory taken off the highest order rank in channel 0. the pch controls the flash device through the spi interface and internal logic. ? in order to interface with dram, the intel me utilizes the integrated memory controller (imc) present in the processor. dmi serves as the interface for communication between the imc and intel me. this interfacing occurs in only m0 power state. in the lower intel me power state, m3, code is executed exclusively from secure and isolated intel me local ram. ? the lan controller embedded in the pch as well as the intel gigabit platform lan connect device are required for intel me and intel amt network connectivity. ? bios to provide asset detection and post diagnostics (bios and intel amt can optionally share same flash memory device) ? an isv software package, such as landes k*, altiris*, or micr osoft* sms, can be used to take advantage of the platform manageability capabilities of intel amt. figure 5-11. pch intel ? management engine hi gh-level block diagram slp_s3# slp_s4# slp s5# imc dmi slp _ s5# slp_a# slp_lan# pwrok awrok dpwrok processor dmi clk/bclk gbe intel ? me clocks local ram gbe sus pcie* smlink mac phy pch platform circuitry spi spi control spi flash desc gbe fw intel me fw bios
datasheet 255 functional description 5.24 serial peripheral interface (spi) the serial peripheral interface (spi) is a 4-pin interface that provides a lower-cost alternative for system flash versus the firmware hub on the lpc bus. the 4-pin spi interface consists of clock (c lk), master data out (master out slave in (mosi)), master data in (master in slave out (miso)) and an active low chip select (spi_cs[1:0]#). the pch supports up to two spi flash devices using two separate chip select pins. each spi flash device can be up to 16 mb. the pch spi interface supports 20 mhz, 33 mhz, and 50 mhz spi devices. a spi flash device on with chip select 0 with a valid descriptor must be attached directly to the pch. communication on the spi bus is done with a master ? slave protocol. the slave is connected to the pch and is implemented as a tri-state bus. note: if boot bios strap =?00? then lpc is selected as the location for bios. bios may still be placed on lpc, but all platforms with the pch require a spi flash connected directly to the pch's spi bus with a valid descriptor co nnected to chip select 0 in order to boot. note: when spi is selected by the boot bios dest ination strap and a spi device is detected by the pch, lpc based bios flash is disabled. 5.24.1 spi supported feature overview spi flash on the pch has two operationa l modes, descriptor and non-descriptor. 5.24.1.1 non-descriptor mode non-descriptor mode is not supported as a va lid flash descriptor is required for all pch platforms. 5.24.1.2 descriptor mode descriptor mode is required for all skus of the pch. it enables many new features of the chipset: ? integrated gigabit ethernet and host processor for gigabit ethernet software ?intel active management technology ?intel management engine firmware ? pci express* root port configuration ? supports up to two spi components using two separate chip select pins ? hardware enforced security restricting master accesses to different regions ? chipset soft strap regions provides the ability to use flash nvm as an alternative to hardware pull-up/pull-down resistors for the pch and processor ? supports the spi fast read instruction and frequencies of up to 50 mhz ? support single input, dual output fast read ? uses standardized flash instruction set
functional description 256 datasheet 5.24.1.2.1 spi flash regions in descriptor mode the flash is divided into five separate regions: only three masters can access the four regions: host processor running bios code, integrated gigabit ethernet and host processor running gigabit ethernet software, and intel management engine. the only required region is region 0, the flash descriptor. region 0 must be located in the first sector of device 0 (offset 0). flash region sizes spi flash space requirements differ by platfo rm and configuration. the flash descriptor requires one 4 kb or larger block. gbe requ ires two 4 kb or larger blocks. the amount of flash space consumed is dependent on the erase granularity of the flash part and the platform requirements for the intel me and bios regions. the intel me region contains firmware to support intel active management technology and other intel me capabilities. 5.24.2 flash descriptor the maximum size of the flash descriptor is 4 kb. if the block/sector size of the spi flash device is greater than 4 kb, the flash descriptor will only use the first 4 kb of the first block. the flash descriptor requires it s own block at the bottom of memory (00h). the information stored in the flash descr iptor can only be written during the manufacturing process as its read/write permissions must be set to read only when the computer leaves the manufacturing floor. the flash descriptor is made up of eleven sections (see figure 5-12 ). region content 0 flash descriptor 1bios 2 intel management engine 3 gigabit ethernet 4platform data table 5-56. region size versus er ase granularity of flash components region size with 4 kb blocks size with 8 kb blocks size with 64 kb blocks descriptor 4 kb 8 kb 64 kb gbe 8 kb 16 kb 128 kb bios varies by platform varies by platform varies by platform intel me varies by platform varies by platform varies by platform
datasheet 257 functional description 1. the flash signature selects descriptor mode as well as verifies if the flash is programmed and functioning. the data at the bottom of the flash (offset 10h) must be 0ff0a55ah in order to be in descriptor mode. 2. the descriptor map has pointers to the other five descriptor sections as well as the size of each. figure 5-12. flash descriptor sections descriptor map component signature region master pch soft straps 4kb management engine vscc table descriptor upper map oem section reserved 10 h
functional description 258 datasheet 3. the component section has information about the spi flash in the system including: the number of components, density of ea ch, illegal instructions (such as chip erase), and frequencies for read, fast read and write/erase instructions. 4. the region section points to the three other regions as well as the size of each region. 5. the master region contains the security settings for the flash, granting read/write permissions for each region and identifying each master by a requestor id. see section 5.24.2.1 for more information. 6 & 7. the processor and pch soft strap sections contain processor and pch configurable parameters. 8. the reserved region between the top of the processor strap section and the bottom of the oem section is reserved for future chipset usages. 9. the descriptor upper map determines the length and base address of the management engine vscc table. 10. the management engine vscc table holds the jedec id and the vscc information of the entire spi flash su pported by the nvm image. 11. oem section is 256 bytes reserved at th e top of the flash descriptor for use by oem. 5.24.2.1 descriptor master region the master region defines read and write access setting for each region of the spi device. the master region recognizes three masters: bios, gigabit ethernet, and management engine. each master is only a llowed to do direct reads of its primary regions. table 5-57. region access control table master read/write access region processor and bios me gbe controller descriptor n/a n/a n/a bios processor and bios can always read from and write to bios region read / write read / write management engine read / write intel ? me can always read from and write to intel me region read / write gigabit ethernet read / write read / write gbe software can always read from and write to gbe region platform data region n/a n/a n/a
datasheet 259 functional description 5.24.3 flash access there are two types of flash accesses: direct access: ? masters are allowed to do direct read only of their primary region ? gigabit ethernet region can only be directly accessed by the gigabit ethernet controller. gigabit ethernet software must use program registers to access the gigabit ethernet region. ? master's host or management engine virtual read address is converted into the spi flash linear address (fla) using the flash descriptor region base/limit registers program register access: ? program register accesses are not allowed to cross a 4 kb boundary and can not issue a command that might extend across two components ? software programs the fla corresponding to the region desired ? software must read the devices primary region base/limit address to create a fla. 5.24.3.1 direct access security ? requester id of the device must match that of the primary requester id in the master section ? calculated flash linear address must fall between primary region base/limit ? direct write not allowed ? direct read cache contents are reset to 0's on a read from a different master ? supports the same cache flush mechanism in ich7 which includes program register writes 5.24.3.2 register access security ? only primary region masters can access the registers note: processor running gigabit ethernet software can access gigabit ethernet registers ? masters are only allowed to read or wr ite those regions they have read/write permission ? using the flash region access permissions, one master can give another master read/write permissions to their area ? using the five protected range registers, each master can add separate read/write protection above that granted in the flash descriptor for their own accesses ? example: bios may want to protect different regions of bios from being erased ? ranges can extend across region boundaries
functional description 260 datasheet 5.24.4 serial flash device compatibility requirements a variety of serial flash devices exist in the market. for a serial flash device to be compatible with the pch spi bus, it must meet the minimum requirements detailed in the following sections. note: all pch platforms have require intel ? management engine firmware. 5.24.4.1 pch spi-based bios requirements a serial flash device must meet the following minimum requirements when used explicitly for system bios storage. ? erase size capability of at least one of the following: 64 kbytes, 8 kbytes, 4 kbytes, or 256 bytes. ? device must support multiple writes to a page without requiring a preceding erase cycle (refer to section 5.24.5 ) ? serial flash device must ignore the upper address bits such that an address of ffffffh aliases to the top of the flash memory. ? spi compatible mode 0 support (clock phase is 0 and data is latched on the rising edge of the clock). ? if the device receives a command that is not supported or incomplete (less than 8 bits), the device must complete the cycle gracefully without any impact on the flash content. ? an erase command (page, sector, block, chip, etc.) must set all bits inside the designated area (page, sector, block, chip, etc.) to 1 (fh). ? status register bit 0 must be set to 1 when a write, erase or write to status register is in progress and cleared to 0 when a write or erase is not in progress. ? devices requiring the write enable comm and must automatically clear the write enable latch at the end of data program instructions. ? byte write must be supported. the flexibili ty to perform a write between 1 byte to 64 bytes is recommended. ? hardware sequencing requirements are optional in bios only platforms. ? spi flash parts that do not meet hardware sequencing command set requirements may work in bios only platforms using software sequencing. 5.24.4.2 integrated lan firm ware spi flash requirements a serial flash device that will be used for system bios and integrated lan or integrated lan only must meet all the spi based bios requirements plus: ? hardware sequencing ? 4-, 8-, or 64-kb erase ca pability must be supported. 5.24.4.2.1 spi flash unlocking re quirements for integrated lan bios must ensure there is no spi flash ba sed read/write/erase protection on the gbe region. gbe firmware and drivers for the integr ated lan need to be able to read, write and erase the gbe region at all times.
datasheet 261 functional description 5.24.4.3 intel ? management engine firmware spi flash requirements intel management engine firmware must me et the spi flash based bios requirements plus: ? hardware sequencing. ? flash part must be uniform 4-kb erasable block throughout the entire device or have 64-kb blocks with the first block (lowest address) divided into 4-kb or 8-kb blocks. ? write protection scheme must meet spi flash unlocking requirements for intel me. 5.24.4.3.1 spi flash unlockin g requirements for intel ? management engine flash devices must be globally unlocked (read, write and erase access on the me region) from power on by writing 00h to th e flash?s status register to disable write protection. if the status register must be unprotected, it must use the enable write status register command 50h or write enable 06h. opcode 01h (write to status register) must th en be used to write a single byte of 00h into the status register. this must unlock the entire part. if the spi flash?s status register has non-volatile bits that must be written to, bits [5:2] of the flash?s status register must be all 0h to indicate that the flash is unlocked. if bits [5:2] return a non zero values, the in tel me firmware will send a write of 00h to the status register. this must keep the flash part unlocked. if there is no need to execute a write enab le on the status register, then opcodes 06h and 50h must be ignored. after global unlock, bios has the ability to lock down small sections of the flash as long as they do not involve the intel me or gbe region. 5.24.4.4 hardware sequencing requirements ta b l e 5 - 5 8 contains a list of commands and th e associated opcodes that a spi-based serial flash device must support in order to be compatible with hardware sequencing. table 5-58. hardware sequencing commands and opcode requirements commands opcode notes write to status register 01h writes a byte to spi flash?s st atus register. enable write to status register command must be run prior to this command. program data 02h single byte or 64 byte write as determined by flash part capabilities and software. read data 03h write disable 04h read status 05h outputs contents of spi flash?s status register write enable 06h fast read 0bh enable write to status register 50h or 60h enables a bit in the status register to allow an update to the status register erase program mable 256b, 4 kbyte, 8 kbyte or 64 kbyte full chip erase c7h jedec id 9fh see section 5.24.4.4.3 .
functional description 262 datasheet 5.24.4.4.1 single input, dual output fast read the pch now supports the functionality of a single input, dual output fast read. opcode and address phase are shifted in serially to the serial flash si (serial in) pin. data is read out after 8 clocks (dummy bits or wait states) from the both the si and so pin effectively doubling the through put of each fa st read output. in order to enable this functionality, both single input dual output fast read supported and fast read supported must be enabled 5.24.4.4.2 serial flash discoverable parameters (sfdp) as the number of features keeps growing in the serial flash, the need for correct, accurate configuration increases. a new method of determining configuration information is serial flash discoverable parameters (sfdp). information such as vscc values and flash attributes can be read dire ctly from the flash parts. the discoverable parameter read opcode behaves like a fast read command. the opcode is 5ah and the address cycle is 24 bits long. after the opcode 5ah and address are clocked in, there will then be eight clocks (8 wait states) before valid data is clocked out. sfdp is a capability of the flash part, please confirm with target flash vendor to see if it is supported. in order for bios to take advantage of the 5ah opcode it needs to be programmed in the software sequencing registers. 5.24.4.4.3 jedec id since each serial flash device may have unique capabilities and commands, the jedec id is the necessary mechanism for identify ing the device so the uniqueness of the device can be comprehended by the controlle r (master). the jedec id uses the opcode 9fh and a specified implementation an d usage model. this jedec standard manufacturer and device id read method is defined in standard jesd21-c, prn03-nv. 5.24.5 multiple page write usage model the system bios and intel ? management engine firmware usage models require that the serial flash device support multiple writes to a page (minimum of 512 writes) without requiring a preceding erase command. bios commonly uses capabilities such as counters that are used for error logging and system boot progress logging. these counters are typically implemented by using byte-writes to ?increment? the bits within a page that have been designated as the counter. the intel ? me firmware usage model requires the capability for multiple data updates within any given page. these data updates occur using byte-writes without executing a preceding erase to the given page. both the bios and intel ? me firmware multiple page write usage models apply to sequential and non-sequential data writes. note: this usage model requirement is based on any given bit only being written once from a ?1? to a ?0?without requiring the preceding er ase. an erase would be required to change bits back to the 1 state.
datasheet 263 functional description 5.24.5.1 soft flash protection there are two types of flash protection that are not defined in the flash descriptor supported by pch: 1. bios range write protection 2. smi#-based global write protection both mechanisms are logically or?d togeth er such that if any of the mechanisms indicate that the access should be blocked, then it is blocked. ta b l e 5 - 5 9 provides a summary of the mechanisms. a blocked command will appear to software to finish, except that the blocked access status bit is set in this case. 5.24.5.2 bios range write protection the pch provides a method for blocking writes to specific ranges in the spi flash when the protected bios ranges are enabled. this is achieved by checking the opcode type information (which can be locked down by th e initial boot bios) and the address of the requested command against the base and limit fields of a write protected bios range. note: once bios has locked down the protected bios range registers, this mechanism remains in place until the next system reset. 5.24.5.3 smi# based global write protection the pch provides a method for blocking writes to the spi flash when the write protected bit is cleared (that is, protected). this is achieved by checking the opcode type information (which can be locked down by the initial boot bios) of the requested command. the write protect and lock enable bits inte ract in the same manner for spi bios as they do for the fwh bios. 5.24.6 flash device configurations the pch-based platform must have a spi flash connected directly to the pch with a valid descriptor and intel management engine firmware. bios may be stored in other locations such as firmware hub and spi fl ash hooked up directly to an embedded controller for mobile platforms. note this w ill not avoid the direct spi flash connected to pch requirement. table 5-59. flash protec tion mechanism summary mechanism accesses blocked range specific? reset-override or smi#- override? equivalent function on fwh bios range write protection writes yes reset override fwh sector protection write protect writes no smi# override same as write protect in intel ? ichs for fwh
functional description 264 datasheet 5.24.7 spi flash device recommended pinout ta b l e 5 - 6 0 contains the recommended serial flas h device pin-out for an 8-pin device. use of the recommended pin-out on an 8-pin device reduces complexities involved with designing the serial flash device onto a motherboard and allows for support of a common footprint usage model (refer to section 5.24.8.1 ). although an 8-pin device is preferred over a 16-pin device due to footprint compatibility, the following table contains th e recommended serial flash device pin-out for a 16-pin soic. 5.24.8 serial flash device package 5.24.8.1 common footprint usage model in order to minimize platform motherboard redesign and to enable platform bill of material (bom) selectability, many pc system oems design their motherboard with a single common footprint. this common footprint allows population of a soldered down device or a socket that accepts a leadless device. this enables the board manufacturer to support, using selection of the appropriat e bom, either of these solutions on the same system without requiring any board redesign. the common footprint usage model is desirable during system debug and by flash content developers since the leadless device can be easily removed and reprogrammed without damage to device leads. when the board and flash content is mature for high- volume production, both the socketed leadle ss solution and the soldered down leaded solution are available through bom selection. table 5-60. recommended pinout for 8-pin serial flash device pin # signal 1c h i p s s e l e c t 2 data output 3 write protect 4g r o u n d 5 data input 6s e r i a l c l o c k 7h o l d / r e s e t 8 supply voltage table 5-61. recommended pinout for 16-pin serial flash device pin # signal pin # signal 1 hold / reset 9 write protect 2 supply voltage 10 ground 3 no connect 11 no connect 4 no connect 12 no connect 5 no connect 13 no connect 6 no connect 14 no connect 7 chip select 15 serial data in 8 serial data out 16 serial clock
datasheet 265 functional description 5.24.8.2 serial flash devi ce package recommendations it is highly recommended that the common footprint usage model be supported. an example of how this can be accomplished is as follows: ? the recommended pinout for 8-pin seri al flash devices is used (refer to section 5.24.7 ). ? the 8-pin device is supported in either an 8-contact vdfpn (6x5 mm mlp) package or an 8-contact wson (5x6 mm) package. these packages can fit into a socket that is land pattern compatible with the wide body so8 package. ? the 8-pin device is supported in the so8 (150 mil) and in the wide-body so8 (200 mil) packages. the 16-pin device is supported in the so16 (300 mil) package. 5.24.9 pwm outputs (server/workstation only) this signal is driven as open-drain. an external pull-up resistor is integrated into the fan to provide the rising edge of the pwm output signal. the pwm output is driven low during reset, which represents 0% duty cycl e to the fans. after reset deassertion, the pwm output will continue to be driven low until one of the following occurs: ? the internal pwm control register is programmed to a non-zero value by appropriate firmware. ? the watchdog timer expires (enabled and set at 4 seconds by default). ? the polarity of the signal is inverted by firmware. note that if a pwm output will be programmed to inverted polarity for a particular fan, then the low voltage driven during rese t represents 100% duty cycle to the fan. 5.24.10 tach inputs (server/workstation only) this signal is driven as an open-collector or open-drain output from the fan. an external pull-up is expected to be impl emented on the motherboard to provide the rising edge of the tach input. this signal has analog hysteresis and digital filtering due to the potentially slow rise and fall times. this signal has a weak internal pull-up resistor to keep the input buffer from floating if the tach input is not connected to a fan. 5.25 feature capability mechanism a set of registers is included in the pch lpc interface (device 31, function 0, offset e0h?ebh) that allows the system software or bios to easily determine the features supported by the pch. these registers can be accessed through lpc pci configuration space, thus allowing for convenient single point access mechanism for chipset feature detection. this set of registers consists of: ? capability id (fdcap) ? capability length (fdlen) ? capability version and vendor-s pecific capability id (fdver) ? feature vector (fvect)
functional description 266 datasheet 5.26 pch display interfaces and intel ? flexible display interconnect display is divided between processor and pch. the processor houses memory interface, display planes, and pipes while pch has transcoder and display interface or ports. intel? fdi connects the processor and pch display engine. the number of planes, pipes, and transcoders decide the number of simultaneous and concurrent display devices that can be driven on a platform. the pch integrates one analog, lvds (mobile only) and three digital ports b, c, and d. each digital port can transmit data according to one or more protocols. digital port b, c, and d can be configured to drive natively hdmi, displayport, or dvi. digital port b also supports serial digital video out (sdvo) that converts one protocol to another. digital port d can be configured to drive natively embedded displayport (edp). each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. the pch?s analog port uses an integrated 340.4 mhz ramdac that can directly drive a standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit color at 75 hz. the pch sdvo port (configured through digital port b) is capable of driving a 200 mp/s (megapixels/second) rate. each digital port is capable of driving re solutions up to 2560x1600 at 60 hz through displayport and 1920x1200 at 60 hz using hdmi or dvi (with reduced blanking). 5.26.1 analog display inte rface characteristics the analog port provides a rgb signal ou tput along with a hsync and vsync signal. there is an associated display data channel (ddc) signal pair that is implemented using gpio pins dedicated to the analog port . the intended target device is for a moni- tor with a vga connector. display devices such as lcd panels with analog inputs may work satisfactory but no functionality adde d to the signals to enhance that capability. figure 5-13. analog port characteristics
datasheet 267 functional description 5.26.1.1 integrated ramdac the display function contains a ram-based digital-to-analog converter (ramdac) that transforms the digital data from the graphics and video subsystems to analog data for the vga monitor. the pch?s integrated 340. 4 mhz ramdac supports resolutions up to 2048x1536 at 75 hz. three 8-bit dacs provide the r, g, and b signals to the monitor. 5.26.1.1.1 sync signals hsync and vsync signals are digital and conform to ttl signal levels at the connector. since these levels cannot be generated internal to the device, external level shifting buffers are required. these signals can be pola rity adjusted and individually disabled in one of the two possible states. the sync signals should power up disabled in the high state. no composite sync or special flat panel sync support are included. 5.26.1.1.2 vesa/vga mode vesa/vga mode provides compatibility for pre-existing software that set the display mode using the vga crtc registers. timings are generated based on the vga register values and the timing generator registers are not used. 5.26.1.2 ddc (display data channel) ddc is a standard defined by vesa. its purpose is to allow communication between the host system and display. both configuratio n and control information can be exchanged allowing plug- and-play systems to be re alized. support for ddc 1 and 2 is imple- mented. the pch uses the ddc_clk and ddc_ data signals to communicate with the analog monitor. the pch will generate these si gnals at 2.5 v. external pull-up resistors and level shifting circuitry should be implemented on the board. 5.26.2 digital display interfaces the pch can drive a number of digital interfaces natively. the digital ports b, c, and/or d can be configured to drive hdmi, dvi, di splayport, and embedded displayport (port d only). the pch provides a dedicated port for digital port lvds (mobile only). 5.26.2.1 lvds (mobile only) lvds for flat panel is compatible with the ansi/tia/eia-644 specification. this is an electrical standard only defining driver output characteristics and receiver input characteristics. each channel supports transmit clock freque ncy ranges from 25 mhz to 112 mhz, which provides a throughput of up to 784 mbps on each data output and up to 112 mp/s on the input. when using both channels, each carry a portion of the data; thus, doubling the throughput to a maximum theoretical pixel rate of 224 mp/s. there are two lvds transmitter channels (channel a and channel b) in the lvds interface. channel a and channel b consist of 4-data pairs and a clock pair each. the lvds data pair is used to transfer pixel data as well as the lcd timing control signals. figure 5-14 shows a pair of lvds signals and swing voltage.
functional description 268 datasheet logic values of 1s and 0s are represented by the differential voltage between the pair of signals. as shown in the figure 5-15 a serial pattern of 1100011 represents one cycle of the clock. 5.26.2.1.1 lvds pair states the lvds pairs can be put into one of five states: ?active ?powered down hi-z ? powered down 0 v ?common mode ?send zeros when in the active state, several data fo rmats are supported. when in powered down state, the circuit enters a low power state an d drives out 0 v or the buffer is the hi-z state on both the output pins for the entire channel. the common mode hi-z state is both pins of the pair set to the common mo de voltage. when in the send zeros state, the circuit is powered up but sends only zero for the pixel color data regardless what the actual data is with the clock lines and timing signals sending the normal clock and timing data. the lvds port can be enabled/disabled using software. a disabled port enters a low power state. once the port is enabled, indivi dual driver pairs may be disabled based on the operating mode. disabled drivers can be powered down for reduced power consumption or optionally fixed to forced 0s output. individual pairs or sets of lvds pairs can be selectively powered down when not being used. the panel power sequencing can be set to override the selected power state of the drivers during power sequencing. figure 5-14. lvds sign als and swing voltage figure 5-15. lvds cloc k and data relationship
datasheet 269 functional description 5.26.2.1.2 single channel versus dual channel mode in the single channel mode, only channel- a is used. channel-b cannot be used for single channel mode. in the dual channel mode, both channel-a and channel-b pins are used concurrently to drive one lvds display. in single channel mode, channel a can take 18 bits of rgb pixel data, plus 3 bits of timing control (hsync/vsync/de) and output them on three differential data pair outputs; or 24 bits of rgb (plus 4 bits of timi ng control) output on four differential data pair outputs. a dual channel interface converts 36 or 48 bits of color information plus the 3 or 4 bits of timing control respectively and outputs it on six or eight sets of differential data outputs respectively. dual channel mode uses twice the number of lvds pairs and transfers the pixel data at twice the rate of the single channel. in gene ral, one channel will be used for even pixels and the other for odd pixel data. the first pixel of the line is determined by the display enable going active and that pixel will be sent out channel-a. all horizontal timings for active, sync, and blank will be limited to be on two pixel boundaries in the two channel modes. note: platforms using the pch for integrated graphi cs support 24-bpp display panels of type 1 only (compatible with vesa lvds color mapping). 5.26.2.1.3 panel power sequencing this section provides details for the power sequence timing relationship of the panel power, the backlight enable and the lvds data timing delivery. to meet the panel power timing specification requirements two signals, lfp_vdd_en and lfp_bklt_en, are provided to control the timing sequenci ng function of the panel and the backlight power supplies. a defined power sequence is recommended when enabling the panel or disabling the panel. the set of timing parameters can vary from panel to panel vendor, provided that they stay within a predefined range of va lues. the panel vdd power, the backlight on/ off state and the lvds clock and data lines are all managed by an internal power sequencer. note: support for programming parameters tx and t1 through t5 using software is provided. figure 5-16. panel power sequencing power on sequence from off state and power off sequence after full on panel vdd enable panel backlight enable clock/data lines t1+t2 t5 t3 valid t4 panel on off off tx t4
functional description 270 datasheet 5.26.2.1.4 lvds ddc the display pipe selected by the lvds display port is programmed with the panel timing parameters that are determined by installe d panel specifications or read from an onboard edid rom. the programmed timing va lues are then ?locked? into the registers to prevent unwanted corruption of the values. from that point on, the display modes are changed by selecting a different source size for that pipe, programming the vga registers, or selecting a source size and enabling the vga. the lvds ddc helps to reads the panel timing parameters or panel edid. 5.26.2.2 high definition multimedia interface the high-definition multimedia interface (h dmi) is provided for transmitting uncom- pressed digital audio and video signals from dvd players, set-top boxes and other audiovisual sources to television sets, projectors and other video displays. it can carry high quality multi-channel audio data and all standard and high-definition consumer electronics video formats. hdmi display interface connecting the pch and display devices utilizes transition minimized differential signaling (tmds) to carry audiovisual information through the same hdmi cable. hdmi includes three separate communication s channels: tmds, ddc, and the optional cec (consumer electronics control) (not supported by the pch). as shown in figure 5-17 the hdmi cable carries four differenti al pairs that make up the tmds data and clock channels. these channels are used to carry video, audio, and auxiliary data. in addition, hdmi carries a vesa ddc. the ddc is used by an hdmi source to deter- mine the capabilities and characteristics of the sink. audio, video and auxiliary (control/status) data is transmitted across the three tmds data channels. the video pixel clock is tran smitted on the tmds clock channel and is used by the receiver for data recovery on the three data channels. the digital display data signals driven natively through the pch are ac coupled and needs level shifting to convert the ac coupled signals to the hdmi compliant digital signals. pch hdmi interface is designed as per high -definition multimedia interface specifica- tion 1.4a. the pch supports high-definit ion multimedia interface compliance test specification 1.4a. figure 5-17. hdmi overview
datasheet 271 functional description 5.26.2.3 digital video interface (dvi) the pch digital ports can be configured to drive dvi-d. dvi uses tmds for transmitting data from the transmitter to the receiver which is similar to the hdmi protocol but the audio and cec. refer to the hdmi section for more information on the signals and data transmission. to drive dvi-i through the back panel the vga ddc signals is connected along with the digital data and clock signals from one of the digital ports. when a sys- tem has support for a dvi-i port, then either vga or the dvi-d through a single dvi-i connector can be driven but not both simultaneously. the digital display data signals driven natively through the pch are ac coupled and needs level shifting to convert the ac coupled signals to the hdmi compliant digital sig- nals. 5.26.2.4 displayport* displayport is a digital communication interface that utilizes differential signaling to achieve a high bandwidth bus interface designed to support connections between pcs and monitors, projectors, and tv displays. displayport is also suitable for display connections between consumer electronics devices such as high definition optical disc players, set top boxes, and tv displays. a displayport consists of a main link, auxilia ry channel, and a hot plug detect signal. the main link is a uni-directional, high-b andwidth, and low latency channel used for transport of isochronous data streams such as uncompressed video and audio. the auxiliary channel (aux ch) is a half-duplex bidirectional channel used for link manage- ment and device control. the hot plug detect (hpd) signal serves as an interrupt request for the sink device. pch is designed as per vesa displayport standard version 1.1a. the pch supports vesa displayport* phy compliance test spec ification 1.1 and vesa displayport* link layer compliance test specification 1.1. figure 5-18. displayport overview
functional description 272 datasheet 5.26.2.5 embedded displayport embedded displayport (edp*) is a embedd ed version of the displayport standard oriented towards applications such as note book and all-in-one pcs. edp is supported only on digital port d. like displayport, embedded displayport also consists of a main link, auxiliary channel, and a optional hot plug detect signal. the edp support on desktop pch is possible be cause of the addition of the panel power sequencing pins: l_vdd, l_bklt_en and l_blkt_ctrl. the edp on the pch can be configured for 2 or 4 lanes. pch supports embedded displayport* (edp*) standard version 1.1. 5.26.2.6 displayport aux channel a bi-directional ac coupled aux channel inte rface replaces the i2c for edid read, link management and device control. i 2 c-to-aux bridges are required to connect legacy display devices. 5.26.2.7 displayport hot-plug detect (hpd) the pch supports hpd for hot-plug sink even ts on the hdmi and displayport interface. 5.26.2.8 integrated audio ov er hdmi and displayport displayport and hdmi interfaces on pch support audio. ta b l e 5 - 5 9 shows the supported audio technologies on the pch. pch will continue to support silent stream. s ilent stream is a integrated audio feature that enables short audio streams such as system events to be heard over the hdmi and displayport monitors. pch supports silent streams over the hdmi and displayport interfaces at 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz and 192 khz sampling rates. 5.26.2.9 serial digital video out (sdvo) serial digital video out (sdvo) sends display data in serialized format which then can be converted into appropriate display protocol using a sdvo device. serial digital video out (sdvo) supports sdvo-lvds only on the pch. though the sdvo electrical interface is based on the pci express interfac e, the protocol and ti mings are completely unique. the pch utilizes an exte rnal sdvo device to translate from sdvo protocol and timings to the desired display format and timings. sdvo is supported only on digital port b of the pch. table 5-59. pch supported audio fo rmats over hdmi and displayport* audio formats hdmi displayport ac-3 - dolby* digital yes no dolby digital plus yes no dts-hd* yes no lpcm, 192 khz/24 bit, 8 channel yes yes (two channel - up to 96 khz 24 bit) dolby truehd, dts-hd master audio* (losses blu-ray disc* audio format) yes no
datasheet 273 functional description 5.26.2.9.1 control bus communication to sdvo registers and if utilized, add2 proms and monitor ddcs, are accomplished by using the sdvoctrldata and sdvoctrlclk signals through the sdvo device. these signals run up to 400 khz and connect directly to the sdvo device. the sdvo device is then responsible for routing the ddc and prom data streams to the appropriate location. consult sdvo device data sheets for level shifting require- ments of these signals. figure 5-19. sdvo conceptual block diagram sdvo b 3 rd party sdvo external device green b red b blue b tv clock in control data control clock stall interrupt pch lvds panel
functional description 274 datasheet 5.26.3 mapping of digital display interface signals table 5-60. pch digital port pin mapping port description displayport* signals hdmi* signals sdvo signals pch display port pin details port b dpb_lane3 tmdsb_clk sdvob_clk ddpb_[3]p dpb_lane3# tmdsb_clkb sdvob_clk# ddpb_[3]n dpb_lane2 tmdsb_data0 sdvob_blue ddpb_[2]p dpb_lane2# tmdsb_data0b sdvob_blue# ddpb_[2]n dpb_lane1 tmdsb_data1 sdvob_green ddpb_[1]p dpb_lane1# tmdsb_data1b sdvob_green# ddpb_[1]n dpb_lane0 tmdsb_data2 sdvob_red ddpb_[0]p dpb_lane0# tmdsb_data2b sdvob_red* ddpb_[0]n dpb_hpd tmdsb_hpd ddpb_hpd dpb_aux ddpb_auxp dpb_auxb ddpb_auxn port c dpc_lane3 tmdsc_clk ddpc_[3]p dpc_lane3# tmdsc_clkb ddpc_[3]n dpc_lane2 tmdsc_data0 ddpc_[2]p dpc_lane2# tmdsc_data0b ddpc_[2]n dpc_lane1 tmdsc_data1 ddpc_[1]p dpc_lane1# tmdsc_data1b ddpc_[1]n dpc_lane0 tmdsc_data2 ddpc_[0]p dpc_lane0# tmdsc_data2b ddpc_[0]n dpc_hpd tmdsc_hpd ddpc_hpd dpc_aux ddpc_auxp dpc_auxc ddpc_auxn port d dpd_lane3 tmdsd_clk ddpd_[3]p dpd_lane3# tmdsd_clkb ddpd_[3]n dpd_lane2 tmdsd_data0 ddpd_[2]p dpd_lane2# tmdsd_data0b ddpd_[2]n dpd_lane1 tmdsd_data1 ddpd_[1]p dpd_lane1# tmdsd_data1b ddpd_[1]n dpd_lane0 tmdsd_data2 ddpd_[0]p dpd_lane0# tmdsd_data2b ddpd_[0]n dpd_hpd tmdsd_hpd ddpd_hpd dpd_aux ddpd_auxp dpd_auxd ddpd_auxn
datasheet 275 functional description 5.26.4 multiple display configurations the following multiple display configurat ion modes are supported (with appropriate driver software): ? single display is a mode with one display port activated to display the output to one display device. ?intel ? dual display clone is a mode with two display ports activated to drive the display content of same color depth setting but potentially different refresh rate and resolution settings to all the active display devices connected. ? extended desktop is a mode with two display ports activated used to drive the content with potentially different color de pth, refresh rate, and resolution settings on each of the active display devices connected. ta b l e 5 - 6 1 describes the valid interoperability between display technologies. 5.26.5 high-bandwidth digita l content protection (hdcp) hdcp is the technology for protecting high definition content against unauthorized copy or unreceptive between a source (computer, digital set top boxes, etc.) and the sink (panels, monitor, and tvs). the pch support s hdcp 1.4 for content protection over wired displays (hdmi, dvi, and displayport). the hdcp 1.4 keys are integrated into the pch and customers are not required to physically configure or handle the keys. table 5-61. display co-existence table display not attached dac integrated lvds integrated displayport* hdmi*/ dvi edp* vga not attached xs s s s s dac vga s xs 1 , c, e a a s 1 , c, e integrated lvds ss 1 , c, e xs 1 , c, e s 1 , c, e x integrated displayport sas 1 , c, e a a s 1 , c, e hdmi/dvi sas 1 , c, e a s 1 , c, e s 1 , c, e sdvo lvds ss 1 , c, e s 1 , c, e s 1 , c, e s 1 , c, e a edp ss 1 , c, e xs 1 , c, e s 1 , c, e x ? a = single pipe single display, intel ? dual display clone (only 24 -bpp), or extended desktop mode ? c = clone mode ? e = extended desktop mode ? s = single pipe single display ?s 1 = single pipe single display with one display device disabled ? x = unsupported/not applicable
functional description 276 datasheet 5.26.6 intel ? flexible display interconnect intel ? fdi connects the display engine in the processor with the display interfaces on the pch. the display data from the frame buff er is processed in the display engine of the processor and sent to the pch over the in tel fdi where it is transcoded as per the display protocol and driven to the display monitor. intel fdi has two channels a and b. each ch annel has 4 lanes and total combined is 8 lanes to transfer the data from the processor to the pch. depending on the data bandwidth the interface is dynamically configured as x1, x2 or x4 lanes. intel fdi supports lane reversal and lane polarity reversal. 5.27 intel ? virtualization technology intel virtualization technology (intel ? vt) makes a single system appear as multiple independent systems to software. this allows for multiple, independent operating systems to be running simultaneously on a single system. intel vt comprises technology components to support virt ualization of platforms based on intel architecture microprocessors and chipsets. the first revision of this technology (intel vt-x) added hardware support in the processor to improve the virtualization performance and robustness. the second revision of this specification (intel vt-d) adds chipset hardware implementation to improve i/o performance and robustness. the intel vt-d specification and other vt documents can be referenced here: http:// www.intel.com/technology/platform-te chnology/virtualization/index.htm 5.27.1 intel ? vt-d objectives the key intel vt-d objectives are domain based isolation and hardware based virtualization. a domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. virtualization allows for the creation of one or more partitions on a single system. this could be multiple partitions in the same os or there can be multiple operating system instances running on the same system offering benefits such as system consolidation, legacy migration, activity partitioning or security. 5.27.2 intel ? vt-d features supported ? the following devices and functions support flr in the pch: ? high definition audio (device 27: function 0) ? sata host controller 1 (device 31: function 2) ? sata host controller 2 (device 31: function 5) ? usb2 (ehci) host controller 1 (device 29: function 0) ? usb2 (ehci) host controller 2 (device 26: function 0) ? gbe lan host controller (device 25: function 0) ? interrupt virtualization support for ioxapic ? virtualization support for hpets
datasheet 277 functional description 5.27.3 support for function level reset (flr) in pch intel vt-d allows system software (vmm/os) to assign i/o devices to multiple domains. the system software, then, requires ways to reset i/o devices or their functions within, as it assigns/re-assigns i/o devices from one domain to another. the reset capability is required to ensure the devices have undergone proper re-initialization and are not keeping the stale state. a standard ability to reset i/o devices is also useful for the vmm in case where a guest domain with a ssigned devices has become unresponsive or has crashed. pci express defines a form of device hot reset which can be initiated through the bridge control register of the root/switch port to which the device is attached. how- ever, the hot reset cannot be applied selectively to specific device functions. also, no similar standard functionality exists for resetting root-complex integrated devices. current reset limitations ca n be addressed through a function level reset (flr) mecha- nism that allows software to independently reset specific device functions. 5.27.4 virtualization support for pchs ioxapic the intel vt-d architecture extension requires interrupt messages to go through the similar address remapping as any other memo ry requests. this is to allow domain isolation for interrupts such that a device assigned in one domain is not allowed to generate interrupts to another domain. the address remapping for intel vt-d is based on the bus:device:function field associated with the requests. hence, it is re quired for the internal ioxapic to initiate the interrupt messages using a unique bus:device:function. the pch supports bios programmable unique bus:device:function for the internal ioxapic. the bus:device:function field does not change the ioxapic functionality in anyway, nor promoting ioxapic as a stand-alone pci device. the field is only used by the ioxapic in the following: ? as the requestor id when initiating interrupt messages to the processor ? as the completer id when responding to the reads targeting the ioxapic?s memory-mapped i/o registers 5.27.5 virtualization support fo r high precision event timer (hpet) the intel vt-d architecture extension requires interrupt messages to go through the similar address remapping as any other memo ry requests. this is to allow domain isolation for interrupts such that a device assigned in one domain is not allowed to generate interrupts to another domain. the address remapping for intel vt-d is based on the bus:device:function field associated with the requests. hence, it is required for the hpet to initiate the direct fsb interrupt messages using unique bus:device:function. the pch supports bios programmable unique bus:device:function for each of the hpet timers. the bus:device:function field does not change the hpet functionality in anyway, nor promoting it as a stand-alone pci device. the field is only used by the hpet timer in the following: ? as the requestor id when initiating direct interrupt messages to the processor ? as the completer id when responding to the reads targeting its memory-mapped registers ? the registers for the programmable bus:device:function for hpet timer 7:0 reside under the device 31:function 0 lp c bridge?s configuration space.
functional description 278 datasheet
datasheet 279 ballout definition 6 ballout definition this chapter contains the pch ballout information. 6.1 desktop pch ballout this section contains the desktop pch ballout. figure 6-1 , figure 6-2 , figure 6-3 , and figure 6-4 show the ballout from a top of the package quadrant view. ta b l e 6 - 1 is the bga ball list, sorted alphabetically by signal name. note: references to pwm[3:0], tach[7:0], sst, nmi#, smi# are for server/workstation skus only. pin names pwm[3:0], tach[7:0], sst, nmi#, smi# are reserved on desktop skus. see chapter 2 for further details. figure 6-1. desktop pch ballo ut (top view - upper left) bu bt br bp bn bm bl bk bj bh bg bf be bd bc bb ba ay aw av au at ar ap an am al ak 1 vss_nctf vss_nctf vss v5ref vss crt_ddc _data vccadac crt_blu e 2 vss_nctf ad14 ad21 c/be2# gnt3# / gpio55 ad24 clkoutf lex3 / gpio67 vssadac crt_vsy nc crt_gre en xclk_rc omp 3 vss perr# ad9 ad13 vss crt_ddc _clk dac_iref vss 4 vss_nctf pirqh# / gpio5 c/be0# ad23 ad15 ad22 crt_hsy nc vss 5 req1# / gpio50 pirqd# vss pirqb# req0# clkoutf lex1 / gpio65 clkoutf lex2 / gpio66 vss vccaclk 6 vss_nctf serr# vss vss vss vss ad16 ad18 vss vss vss vss vss crt_red crt_irtn vss 7 ad2 c/be1# 8 ad12 req2# / gpio52 par ad29 trdy# ad28 gnt1# / gpio51 vss refclk14 in ddpd_ct rldata 9 ad7 ad10 pirqe# / gpio2 devsel# ad27 vss ad26 pirqf# / gpio3 clkoutf lex0 / gpio64 vss ddpd_ct rlclk 10 vss pirqa# ad11 11 ad19 ad5 irdy# frame# vss req3# / gpio54 clkout_ pci0 vss vss 12 gnt2# / gpio53 ad8 vss ad31 ad6 ad4 vss stop# vss vss clkout_ pci2 vss ddpc_ct rlclk 13 ad3 c/be3# ad25 14 vss ad20 pcirst# clkout_ pci4 clkout_ pci1 ddpc_ct rldata 15 pirqg# / gpio4 tach7 / gpio71 pirqc# fwh0 / lad0 vss ad17 ad0 clkin_pci loopbac k vss gnt0# pme# vss vss sdvo_ct rlclk 16 tach4 / gpio68 tach3 / gpio7 vss 17 tach0 / gpio17 tach6 / gpio70 ldrq0# fwh1 / lad1 fwh4 / lframe# ad1 vcc3_3 vcc3_3 plock# ad30 clkout_ pci3 vss sdvo_ct rldata 18 tach5 / gpio69 vss vss vss vss 19 vss tach1 / gpio1 pwm3 20 pwm2 vss fwh2 / lad2 fwh3 / lad3 vss vcc3_3 vss ldrq1# / gpio23 nc_1 vcc3_3 vcc3_3 vss vss vss 21 pwm1 pwm0 22 hda_bcl k vss vss hda_sdin 2 hda_sdin 3 vss hda_sdin 1 hda_sdin 0 hda_rst# tach2 / gpio6 vss vss vcc3_3 vss vccasw vss 23 hda_sdo hda_syn c vss 24 vccio vss vccasw vccasw vccasw 25 v5ref_su s usbrbias # usbrbias usbp10n usbp10p vss vss vss hda_doc k_en# / gpio33 hda_doc k_rst# / gpio13 vccio 26 vss usbp9n vss vccio vss vccasw vccasw vss 27 usbp9p usbp8n usbp13p usbp13n vss usbp12n usbp12p vss tp11 vccio 28 vss vccsushd a vss vccasw vccasw vccasw
280 datasheet ballout definition figure 6-2. desktop pch ballout (top view - lower left) 29 vss usbp8p usbp5n 30 usbp5p vccsus3_3 vccasw vccasw vss vss 31 usbp4p vss usbp11p usbp11n vss usbp7n usbp7p vss vss vccsus3_3 32 usbp3p usbp4n vss vccsus3_3 vccasw vcccore vcccore vcccore 33 usbp3n vss usbp2n usbp6n usbp6p vss vss vss usbp1n usbp1p vccsus3_3 34 vss vccasw vcccore vcccore vcccore 35 vccsus3_3 vss usbp2p 36 vss vss vccsus3_3 vccsus3_3 vccsus3_3 vss usbp0n usbp0p vss tp17 tp18 vccasw vccasw vccasw vss vss 37 dpwrok srtcrst# 38 intruder # rsmrst# pwrok vss clkin_do t_96p clkin_do t_96n vss vccio vss vss vccsus3_3 vccasw vcc3_3 vcc3_3 39 vss rtcx1 rtcx2 40 vss vccdsw3_ 3 vccsus3_3 vccio vccio 41 rtcrst# intvrmen vss oc5# / gpio9 oc2# / gpio41 vss oc1# / gpio40 slp_a# vss dcpsusby p dcpsus vccio vss 42 vccrtc dswvrme n vss 43 pwrbtn# oc4# / gpio43 oc0# / gpio59 oc3# / gpio42 gpio27 gpio31 vss slp_sus# sst jtag_tck pcieclkr q2# / gpio20/ smi# vss vss vss 44 wake# vss pcieclkr q6# / gpio45 sata5rx p sata3rx p vss 45 oc6# / gpio10 susack# oc7# / gpio14 46 suswarn #/ suspwrd nack/ gpio30 sml1ale rt# / pchhot# / gpio74 tp10 sml1dat a / gpio75 sml1clk / gpio58 drampw rok vss apwrok dcpsst batlow# / gpio72 sata5rx n sata3rx n vss 47 smbclk vss jtag_td o vss susclk / gpio62 vss vss vss vss 48 vss pltrst# ri# 49 sml0ale rt# / gpio60 smbdata smbaler t# / gpio11 slp_lan# / gpio29 cl_rst1# tp12 vss sata5txp sata4txp sata4rx n sata2rx p 50 sml0dat a lan_phy_ pwr_ctr l / gpio12 slp_s5# / gpio63 cl_data1 jtag_tm s cl_clk1 sata5txn sata4txn sata4rx p sata2rx n 51 sml0clk gpio8 52 vss_nctf vss slp_s4# vss vss vss sys_rese t# jtag_tdi vss sata1gp / gpio19 serirq vss vss vccspi vss vss 53 gpio57 gpio24 / proc_mis sing slp_s3# sys_pwr ok sata3gp / gpio37 sclock / gpio22 sdataou t1 / gpio48 spi_mosi sata2txp 54 vss_nctf dcprtc sus_stat # / gpio61 pcieclkr q5# / gpio44 sload / gpio38 sata0gp / gpio21 spi_clk vss 55 pcieclkr q7# / gpio46 gpio15 gpio28 sdataou t0 / gpio39 sata2gp / gpio36 bmbusy# / gpio0 spi_miso sata3txp 56 dcprtc_n ctf init3_3v# stp_pci# / gpio34 rcin# spkr clkrun# / gpio32 sata5gp / gpio49/ therm_a lert# sata4gp / gpio16 spi_cs1# sata3txn sata2txn 57 vss_nctf vss_nctf gpio35/ nmi# sataled# a20gate vss spi_cs0# vss bu bt br bp bn bm bl bk bj bh bg bf be bd bc bb ba ay aw av au at ar ap an am al ak
datasheet 281 ballout definition figure 6-3. desktop pch ballout (top view - upper right) aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a vccvrm clkout_ pcie7p vccadpll a vss ddpb_hp d ddpd_hp d vss vss_nct f vss_nct f 1 clkout_ pcie5p clkout_ pcie7n vccadpll b clkout_ pcie6p sdvo_int p vccvrm ddpc_hp d ddpc_0p ddpc_1p ddpc_3n vss_nct f 2 xtal25_i n clkout_ pcie5n clkout_ pcie6n sdvo_st allp sdvo_int n ddpb_3n ddpc_0n ddpc_2p vss 3 vss vss vss vss ddpc_1n ddpc_3p vss vss_nct f 4 xtal25_o ut vss clkout_ pcie1n clkout_ pcie1p sdvo_st alln ddpb_3p vss ddpc_2n ddpd_0p ddpd_0n 5 vss vss clkout_ pcie0n clkout_ pcie0p vss vss vss vss ddpd_au xn ddpd_au xp vss vss vss vss ddpd_1p vss_nct f 6 ddpd_1n ddpd_2p 7 clkout_ peg_a_n vss clkout_ pcie3p clkout_ pcie4p sdvo_tv clkinp ddpb_au xp vss ddpb_2n ddpb_2p vss 8 clkout_ peg_a_p vss clkout_ pcie3n clkout_ pcie4n sdvo_tv clkinn ddpb_au xn vss vss vss ddpd_2n vss 9 perp8 pern8 vss 10 vss clkout_ peg_b_p vss vss vss vss ddpb_1p ddpd_3p ddpd_3n 11 l_bkltc tl clkout_ peg_b_n clkout_ pcie2n tp20 ddpc_au xn ddpb_0n ddpb_1n vss pern7 perp7 vss vss vcc3_3 12 petp7 petp8 petn8 13 vss vss clkout_ pcie2p tp19 ddpc_au xp ddpb_0p 14 vccdiffc lkn vccdiffc lkn vss vss vss vss pern5 perp5 perp6 pern6 vss petn7 vss petp6 15 vss petp5 petn6 16 l_vdd_e n vccdiffc lkn tp9 tp7 vss vss pern4 perp4 vss perp3 pern3 petp4 petn5 17 l_bklte n vss tp8 tp6 petn4 18 vss vss vccaplld mi2 19 vccclkdm i vss vccssc vccssc vss vccio vss vss perp2 pern2 vss perp1 pern1 vss vccio 20 petn3 petp3 21 vss vss vss vss vss vccio vccio vss vss tp1 vss tp24 tp28 vss vss petn2 petp2 22 petp1 vss vss 23 vccasw vccasw vcccore vcccore vss vccio 24 vccio vss vss vss vss tp27 tp23 vss petn1 tp36 tp32 25 vccasw vccasw vss vcccore vss vccio vss tp31 vss 26 vccio vss clkin_gn d1_n clkin_gn d1_p vss tp26 tp22 vss tp34 tp35 27 vccasw vccasw vcccore vcccore vss vccio tp30 28
282 datasheet ballout definition figure 6-4. desktop pch ballo ut (top view - lower right) tp33 tp29 vss 29 vss vss vcccore vcccore vss vccio vccio 30 vccio vccsus3_ 3 clkout_ dmi_p clkout_ dmi_n vss tp2 tp25 tp21 dmi_zco mp dmi_irco mp 31 vcccore vcccore vcccore vcccore dcpsus vccio vss vss dmi2rbia s 32 vccio vss clkin_d mi_p clkin_d mi_n vss tp3 vss vss vss dmi0rxn dmi0rxp 33 vcccore vcccore vcccore vss vccio vccio 34 vss vss dmi1rxp 35 vcccore vss vcccore vss vccio vccio vccio vss vss vss vss tp5 dmi0txn dmi0txp vss dmi2rxp dmi1rxn 36 dmi3rxn dmi2rxn 37 vccio vccio vss vss vss vss vss vss dmi1txp dmi1txn tp4 vss dmi2txp dmi2txn dmi3rxp 38 vss vss dcpsus 39 vccio vccio vss vss vss 40 vccio tp14 vss reserved vss vss dmi3txp dmi3txn vss fdi_rxp2 fdi_rxn2 vccdmi vccdmi 41 vss fdi_rxn0 vss 42 vss tp15 vss vss reserved vss fdi_rxp7 fdi_rxn7 vss fdi_rxn6 fdi_rxp6 fdi_rxp1 vss fdi_rxp0 43 vss sata0tx p reserved reserved reserved reserved 44 fdi_rxn1 vss fdi_rxn4 45 vss sata0tx n reserved vss reserved vss vss reserved vss fdi_int vss fdi_rxn3 fdi_rxp4 46 sata1tx p vss vss vss vss df_tvs fdi_rxp3 fdi_rxn5 47 reserved vss peci vss 48 sata1tx n tp13 reserved vss reserved vss reserved reserved fdi_lsyn c0 fdi_rxp5 vss 49 vss tp16 reserved reserved reserved reserved reserved reserved reserved vss 50 fdi_lsyn c1 fdi_fsyn c0 51 vss vss sata3rc ompo sata3rbi as vss vss clkin_gn d0_p vss clkout_i tpxdp_n clkout_i tpxdp_p vss vss reserved reserved fdi_fsyn c1 ts_vss2 52 sataico mpo vss sata1rx n clkin_gn d0_n vss reserved vss reserved procpw rgd vccaplle xp 53 sata3co mpi vss vccvrm vss vss vss vccafdip ll ts_vss1 54 sataico mpi clkin_sa ta_n sata0rx p vss vccdfter m clkout_ dp_p reserved pmsynch v_proc_i o 55 clkin_sa ta_p vss sata0rx n sata1rx p vccaplls ata vccvrm clkout_d p_n reserved reserved thrmtri p# v_proc_i o_nctf 56 vss vcc3_3 vss vss vccdfter m vss reserved ts_vss3 ts_vss4 57 aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a
datasheet 283 ballout definition table 6-1. desktop pch ballout by signal name desktop pch ball map ball # a20gate bb57 ad0 bf15 ad1 bf17 ad2 bt7 ad3 bt13 ad4 bg12 ad5 bn11 ad6 bj12 ad7 bu9 ad8 br12 ad9 bj3 ad10 br9 ad11 bj10 ad12 bm8 ad13 bf3 ad14 bn2 ad15 be4 ad16 be6 ad17 bg15 ad18 bc6 ad19 bt11 ad20 ba14 ad21 bl2 ad22 bc4 ad23 bl4 ad24 bc2 ad25 bm13 ad26 ba9 ad27 bf9 ad28 ba8 ad29 bf8 ad30 av17 ad31 bk12 apwrok bc46 batlow# / gpio72 av46 bmbusy# / gpio0 aw55 c/be0# bn4 c/be1# bp7 c/be2# bg2 c/be3# bp13 cl_clk1 ba50 cl_data1 bf50 cl_rst1# bf49 clkin_dmi_n p33 clkin_dmi_p r33 clkin_dot_96n bd38 clkin_dot_96p bf38 clkin_gnd0_n w53 clkin_gnd0_p v52 clkin_gnd1_n r27 clkin_gnd1_p p27 clkin_pciloopback bd15 clkin_sata_n af55 clkin_sata_p ag56 clkout_dmi_n p31 clkout_dmi_p r31 clkout_dp_n n56 clkout_dp_p m55 clkout_itpxdp_n r52 clkout_itpxdp_p n52 clkout_pci0 at11 clkout_pci1 an14 clkout_pci2 at12 clkout_pci3 at17 clkout_pci4 at14 clkout_pcie0n ae6 clkout_pcie0p ac6 clkout_pcie1n aa5 clkout_pcie1p w5 clkout_pcie2n ab12 clkout_pcie2p ab14 clkout_pcie3n ab9 clkout_pcie3p ab8 clkout_pcie4n y9 clkout_pcie4p y8 clkout_pcie5n af3 clkout_pcie5p ag2 clkout_pcie6n ab3 clkout_pcie6p aa2 clkout_pcie7n ae2 clkout_pcie7p af1 clkout_peg_a_n ag8 clkout_peg_a_p ag9 clkout_peg_b_n ae12 clkout_peg_b_p ae11 clkoutflex0 / gpio64 at9 clkoutflex1 / gpio65 ba5 clkoutflex2 / gpio66 aw5 desktop pch ball map ball # clkoutflex3 / gpio67 ba2 clkrun# / gpio32 bc56 crt_blue am1 crt_ddc_clk aw3 crt_ddc_data aw1 crt_green an2 crt_hsync ar4 crt_irtn am6 crt_red an6 crt_vsync ar2 dac_iref at3 dcprtc br54 dcprtc_nctf bt56 dcpsst ba46 dcpsus aa32 dcpsus at41 dcpsus a39 dcpsusbyp av41 ddpb_0n r12 ddpb_0p r14 ddpb_1n m12 ddpb_1p m11 ddpb_2n k8 ddpb_2p h8 ddpb_3n m3 ddpb_3p l5 ddpb_auxn r9 ddpb_auxp r8 ddpb_hpd t1 ddpc_0n j3 ddpc_0p l2 ddpc_1n g4 ddpc_1p g2 ddpc_2n f5 ddpc_2p f3 ddpc_3n e2 ddpc_3p e4 ddpc_auxn u12 ddpc_auxp u14 ddpc_ctrlclk al12 ddpc_ctrldata al14 ddpc_hpd n2 ddpd_0n b5 ddpd_0p d5 ddpd_1n d7 desktop pch ball map ball #
284 datasheet ballout definition ddpd_1p c6 ddpd_2n c9 ddpd_2p b7 ddpd_3n b11 ddpd_3p e11 ddpd_auxn r6 ddpd_auxp n6 ddpd_ctrlclk al9 ddpd_ctrldata al8 ddpd_hpd m1 devsel# bh9 dmi_ircomp b31 dmi_zcomp e31 dmi0rxn d33 dmi0rxp b33 dmi0txn j36 dmi0txp h36 dmi1rxn a36 dmi1rxp b35 dmi1txn p38 dmi1txp r38 dmi2rbias a32 dmi2rxn b37 dmi2rxp c36 dmi2txn h38 dmi2txp j38 dmi3rxn e37 dmi3rxp f38 dmi3txn m41 dmi3txp p41 dpwrok bt37 drampwrok bg46 dswvrmen br42 fdi_fsync0 b51 fdi_fsync1 c52 fdi_int h46 fdi_lsync0 e49 fdi_lsync1 d51 fdi_rxn0 c42 fdi_rxn1 f45 fdi_rxn2 h41 fdi_rxn3 c46 fdi_rxn4 b45 fdi_rxn5 b47 fdi_rxn6 j43 fdi_rxn7 m43 desktop pch ball map ball # fdi_rxp0 b43 fdi_rxp1 f43 fdi_rxp2 j41 fdi_rxp3 d47 fdi_rxp4 a46 fdi_rxp5 c49 fdi_rxp6 h43 fdi_rxp7 p43 frame# bc11 fwh0 / lad0 bk15 fwh1 / lad1 bj17 fwh2 / lad2 bj20 fwh3 / lad3 bg20 fwh4 / lframe# bg17 gnt0# ba15 gnt1# / gpio51 av8 gnt2# / gpio53 bu12 gnt3# / gpio55 be2 gpio15 bm55 gpio24 / proc_missing bp53 gpio27 bj43 gpio28 bj55 gpio31 bg43 gpio35 / nmi# bj57 gpio57 bt53 gpio8 bp51 hda_bclk bu22 hda_dock_en# / gpio33 bc25 hda_dock_rst# / gpio13 ba25 hda_rst# bc22 hda_sdin0 bd22 hda_sdin1 bf22 hda_sdin2 bk22 hda_sdin3 bj22 hda_sdo bt23 hda_sync bp23 init3_3v# bn56 intruder# bm38 intvrmen bn41 irdy# bf11 jtag_tck ba43 jtag_tdi bc52 jtag_tdo bf47 jtag_tms bc50 l_bkltctl ag12 desktop pch ball map ball # l_bklten ag18 l_vdd_en ag17 lan_phy_pwr_ctrl / gpio12 bk50 ldrq0# bk17 ldrq1# / gpio23 ba20 ts_vss1 a54 ts_vss2 a52 ts_vss3 f57 ts_vss4 d57 nc_1 ay20 reserved m48 reserved k50 reserved k49 reserved ab46 reserved g56 df_tvs r47 reserved ab50 reserved y50 reserved ab49 reserved ab44 reserved u49 reserved r44 reserved u50 reserved u46 reserved u44 reserved h50 reserved k46 reserved l56 reserved j55 reserved f53 reserved h52 reserved e52 reserved y44 reserved l53 reserved y41 reserved r50 reserved m50 reserved m49 reserved u43 reserved j57 oc0# / gpio59 bm43 oc1# / gpio40 bd41 oc2# / gpio41 bg41 oc3# / gpio42 bk43 oc4# / gpio43 bp43 oc5# / gpio9 bj41 desktop pch ball map ball #
datasheet 285 ballout definition oc6# / gpio10 bt45 oc7# / gpio14 bm45 par bh8 pcieclkrq2# / gpio20 / smi# av43 pcieclkrq5# / gpio44 bl54 pcieclkrq6# / gpio45 av44 pcieclkrq7# / gpio46 bp55 pcirst# av14 peci h48 pern1 j20 pern2 p20 pern3 h17 pern4 p17 pern5 n15 pern6 j15 pern7 j12 pern8 h10 perp1 l20 perp2 r20 perp3 j17 perp4 m17 perp5 m15 perp6 l15 perp7 h12 perp8 j10 perr# bm3 petn1 f25 petn2 c22 petn3 e21 petn4 f18 petn5 b17 petn6 a16 petn7 f15 petn8 b13 petp1 f23 petp2 a22 petp3 b21 petp4 e17 petp5 c16 petp6 b15 petp7 f13 petp8 d13 pirqa# bk10 pirqb# bj5 desktop pch ball map ball # pirqc# bm15 pirqd# bp5 pirqe# / gpio2 bn9 pirqf# / gpio3 av9 pirqg# / gpio4 bt15 pirqh# / gpio5 br4 plock# ba17 pltrst# bk48 pme# av15 pmsynch f55 procpwrgd d53 pwm0 bn21 pwm1 bt21 pwm2 bm20 pwm3 bn19 pwrbtn# bt43 pwrok bj38 rcin# bg56 refclk14in an8 req0# bg5 req1# / gpio50 bt5 req2# / gpio52 bk8 req3# / gpio54 av11 ri# bj48 rsmrst# bk38 rtcrst# bt41 rtcx1 br39 rtcx2 bn39 sata0gp / gpio21 bc54 sata0rxn ac56 sata0rxp ab55 sata0txn ae46 sata0txp ae44 sata1gp / gpio19 ay52 sata1rxn aa53 sata1rxp aa56 sata1txn ag49 sata1txp ag47 sata2gp / gpio36 bb55 sata2rxn al50 sata2rxp al49 sata2txn al56 sata2txp al53 sata3compi ae54 sata3gp / gpio37 bg53 sata3rbias ac52 desktop pch ball map ball # sata3rcompo ae52 sata3rxn an46 sata3rxp an44 sata3txn an56 sata3txp am55 sata4gp / gpio16 au56 sata4rxn an49 sata4rxp an50 sata4txn at50 sata4txp at49 sata5gp / gpio49 / therm_alert# ba56 sata5rxn at46 sata5rxp at44 sata5txn av50 sata5txp av49 sataicompi aj55 sataicompo aj53 sataled# bf57 sclock / gpio22 ba53 sdataout0 / gpio39 bf55 sdataout1 / gpio48 aw53 sdvo_ctrlclk al15 sdvo_ctrldata al17 sdvo_intn t3 sdvo_intp u2 sdvo_stalln u5 sdvo_stallp w3 sdvo_tvclkinn u9 sdvo_tvclkinp u8 serirq av52 serr# br6 sload / gpio38 be54 slp_a# bc41 slp_lan# / gpio29 bh49 slp_s3# bm53 slp_s4# bn52 slp_s5# / gpio63 bh50 slp_sus# bd43 smbalert# / gpio11 bn49 smbclk bt47 smbdata br49 sml0alert# / gpio60 bu49 sml0clk bt51 sml0data bm50 desktop pch ball map ball #
286 datasheet ballout definition sml1alert# / pchhot# / gpio74 br46 sml1clk / gpio58 bj46 sml1data / gpio75 bk46 spi_clk ar54 spi_cs0# at57 spi_cs1# ar56 spi_miso at55 spi_mosi au53 spkr be56 srtcrst# bn37 sst bc43 stop# bc12 stp_pci# / gpio34 bl56 sus_stat# / gpio61 bn54 susack# bp45 susclk / gpio62 ba47 suswarn#/ suspwrdnack/ gpio30 bu46 sys_pwrok bj53 sys_reset# be52 tach0 / gpio17 bt17 tach1 / gpio1 br19 tach2 / gpio6 ba22 tach3 / gpio7 br16 tach4 / gpio68 bu16 tach5 / gpio69 bm18 tach6 / gpio70 bn17 tach7 / gpio71 bp15 thrmtrip# e56 tp1 p22 tp2 l31 tp3 l33 tp4 m38 tp5 l36 tp6 y18 tp7 y17 tp8 ab18 tp9 ab17 tp10 bm46 tp11 ba27 tp12 bc49 tp13 ae49 tp14 ae41 tp15 ae43 tp16 ae50 tp17 ba36 desktop pch ball map ball # tp18 ay36 tp19 y14 tp20 y12 tp21 h31 tp22 j27 tp23 j25 tp24 l22 tp25 j31 tp26 l27 tp27 l25 tp28 j22 tp29 c29 tp30 f28 tp31 c26 tp32 b25 tp33 e29 tp34 e27 tp35 b27 tp36 d25 trdy# bc8 usbp0n bf36 usbp0p bd36 usbp1n bc33 usbp1p ba33 usbp2n bm33 usbp2p bm35 usbp3n bt33 usbp3p bu32 usbp4n br32 usbp4p bt31 usbp5n bn29 usbp5p bm30 usbp6n bk33 usbp6p bj33 usbp7n bf31 usbp7p bd31 usbp8n bn27 usbp8p br29 usbp9n br26 usbp9p bt27 usbp10n bk25 usbp10p bj25 usbp11n bj31 usbp11p bk31 usbp12n bf27 usbp12p bd27 desktop pch ball map ball # usbp13n bj27 usbp13p bk27 usbrbias bm25 usbrbias# bp25 v_proc_io d55 v_proc_io_nctf b56 v5ref bf1 v5ref_sus bt25 vcc3_3 af57 vcc3_3 bc17 vcc3_3 bd17 vcc3_3 bd20 vcc3_3 al38 vcc3_3 an38 vcc3_3 au22 vcc3_3 a12 vcc3_3 au20 vcc3_3 av20 vccaclk al5 vccadac at1 vccadplla ab1 vccadpllb ac2 vccafdipll c54 vccaplldmi2 a19 vccapllexp b53 vccapllsata u56 vccasw au32 vccasw av36 vccasw au34 vccasw ag24 vccasw ag26 vccasw ag28 vccasw aj24 vccasw aj26 vccasw aj28 vccasw al24 vccasw al28 vccasw an22 vccasw an24 vccasw an26 vccasw an28 vccasw ar24 vccasw ar26 vccasw ar28 vccasw ar30 desktop pch ball map ball #
datasheet 287 ballout definition vccasw ar36 vccasw ar38 vccasw au30 vccasw au36 vccclkdmi aj20 vcccore ac24 vcccore ac26 vcccore ac28 vcccore ac30 vcccore ac32 vcccore ae24 vcccore ae28 vcccore ae30 vcccore ae32 vcccore ae34 vcccore ae36 vcccore ag32 vcccore ag34 vcccore aj32 vcccore aj34 vcccore aj36 vcccore al32 vcccore al34 vcccore an32 vcccore an34 vcccore ar32 vcccore ar34 vccdiffclkn ae15 vccdiffclkn ae17 vccdiffclkn ag15 vccdmi e41 vccdmi b41 vccdsw3_3 av40 vccio av24 vccio av26 vccio ay25 vccio ay27 vccio ag41 vccio al40 vccio an40 vccio an41 vccio aj38 vccio y36 vccio v36 vccio y28 desktop pch ball map ball # vccio ae40 vccio ba38 vccio ag38 vccio ag40 vccio aa34 vccio aa36 vccio f20 vccio f30 vccio v25 vccio v27 vccio v31 vccio v33 vccio y24 vccio y26 vccio y30 vccio y32 vccio y34 vccio v22 vccio y20 vccio y22 vccdfterm t55 vccdfterm t57 vccrtc bu42 vccspi an52 vccssc ac20 vccssc ae20 vccsus3_3 u31 vccsus3_3 av30 vccsus3_3 av32 vccsus3_3 ay31 vccsus3_3 ay33 vccsus3_3 bj36 vccsus3_3 bk36 vccsus3_3 bm36 vccsus3_3 at40 vccsus3_3 au38 vccsus3_3 bt35 vccsushda av28 vccvrm aj1 vccvrm r56 vccvrm r54 vccvrm r2 vss ae56 vss br36 vss c12 vss ay22 desktop pch ball map ball # vss a26 vss a29 vss a42 vss a49 vss a9 vss aa20 vss aa22 vss aa24 vss aa26 vss aa28 vss aa30 vss aa38 vss ab11 vss ab15 vss ab40 vss ab41 vss ab43 vss ab47 vss ab52 vss ab57 vss ab6 vss ac22 vss ac34 vss ac36 vss ac38 vss ac4 vss ac54 vss ae14 vss ae18 vss ae22 vss ae26 vss ae38 vss ae4 vss ae47 vss ae8 vss ae9 vss af52 vss af6 vss ag11 vss ag14 vss ag20 vss ag22 vss ag30 vss ag36 vss ag43 vss ag44 desktop pch ball map ball #
288 datasheet ballout definition vss ag46 vss ag5 vss ag50 vss ag53 vss ah52 vss ah6 vss aj22 vss aj30 vss aj57 vss ak52 vss ak6 vss al11 vss al18 vss al20 vss al22 vss al26 vss al30 vss al36 vss al41 vss al46 vss al47 vss am3 vss am52 vss am57 vss an11 vss an12 vss an15 vss an17 vss an18 vss an20 vss an30 vss an36 vss an4 vss an43 vss an47 vss an54 vss an9 vss ar20 vss ar22 vss ar52 vss ar6 vss at15 vss at18 vss at43 vss at47 vss at52 desktop pch ball map ball # vss at6 vss at8 vss au24 vss au26 vss au28 vss au5 vss av12 vss av18 vss av22 vss av34 vss av38 vss av47 vss av6 vss aw57 vss ay38 vss ay6 vss b23 vss ba11 vss ba12 vss ba31 vss ba41 vss ba44 vss ba49 vss bb1 vss bb3 vss bb52 vss bb6 vss bc14 vss bc15 vss bc20 vss bc27 vss bc31 vss bc36 vss bc38 vss bc47 vss bc9 vss bd25 vss bd33 vss bf12 vss bf20 vss bf25 vss bf33 vss bf41 vss bf43 vss bf46 vss bf52 desktop pch ball map ball # vss bf6 vss bg22 vss bg25 vss bg27 vss bg31 vss bg33 vss bg36 vss bg38 vss bh52 vss bh6 vss bj1 vss bj15 vss bk20 vss bk41 vss bk52 vss bk6 vss bm10 vss bm12 vss bm16 vss bm22 vss bm23 vss bm26 vss bm28 vss bm32 vss bm40 vss bm42 vss bm48 vss bm5 vss bn31 vss bn47 vss bn6 vss bp3 vss bp33 vss bp35 vss br22 vss br52 vss bu19 vss bu26 vss bu29 vss bu36 vss bu39 vss c19 vss c32 vss c39 vss c4 vss d15 desktop pch ball map ball #
datasheet 289 ballout definition vss d23 vss d3 vss d35 vss d43 vss d45 vss e19 vss e39 vss e54 vss e6 vss e9 vss f10 vss f12 vss f16 vss f22 vss f26 vss f32 vss f33 vss f35 vss f36 vss f40 vss f42 vss f46 vss f48 vss f50 vss f8 vss g54 vss h15 vss h20 vss h22 vss h25 vss h27 vss h33 vss h6 vss j1 vss j33 vss j46 vss j48 vss j5 vss j53 vss k52 vss k6 vss k9 vss l12 vss l17 vss l38 vss l41 desktop pch ball map ball # vss l43 vss m20 vss m22 vss m25 vss m27 vss m31 vss m33 vss m36 vss m46 vss m52 vss m57 vss m6 vss m8 vss m9 vss n4 vss n54 vss r11 vss r15 vss r17 vss r22 vss r4 vss r41 vss r43 vss r46 vss r49 vss t52 vss t6 vss u11 vss u15 vss u17 vss u20 vss u22 vss u25 vss u27 vss u33 vss u36 vss u38 vss u41 vss u47 vss u53 vss v20 vss v38 vss v6 vss w1 vss w55 vss w57 desktop pch ball map ball # vss y11 vss y15 vss y38 vss y40 vss y43 vss y46 vss y47 vss y49 vss y52 vss y6 vss al43 vss al44 vss r36 vss p36 vss r25 vss p25 vss_nctf a4 vss_nctf a6 vss_nctf b2 vss_nctf bm1 vss_nctf bm57 vss_nctf bp1 vss_nctf bp57 vss_nctf bt2 vss_nctf bu4 vss_nctf bu52 vss_nctf bu54 vss_nctf bu6 vss_nctf d1 vss_nctf f1 vssadac au2 wake# bc44 xclk_rcomp al2 xtal25_in aj3 xtal25_out aj5 desktop pch ball map ball #
290 datasheet ballout definition 6.2 mobile pch ballout this section contains the pch ballout. figure 6-5 , figure 6-6 , figure 6-7 and figure 6-8 show the ballout from a top of the package quadrant view. ta b l e 6 - 2 is the bga ball list, sorted alphabetically by signal name. figure 6-5. mobile pch ballo ut (top view - upper left) 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 bj vss_nctf vss_nctf vss_nctf ddpd_3n perp7 pern6 perp3 perp1 tp28 clkin_gnd 1_n vss tp2 bh vss_nctf vss ddpd_hpd vss perp5 vss vss vss vcc3_3 vss bg vss_nctf tp24 vss ddpd_3p vss pern7 perp6 pern5 pern3 pern1 vss tp32 clkin_gnd 1_p vss vss tp1 bf vss_nctf vccadpllb ddpd_1n ddpd_2n vss vss pern4 perp2 tp31 vss vss vss be vss_nctf ddpd_1p ddpd_2p vss pern8 perp4 pern2 tp27 tp30 tp25 vss bd vss_nctf vccadplla vss bc vss vss vss perp8 vss vss vss tp26 tp29 vss bb ddpc_3p ddpc_3n vss ddpd_0p ddpd_0n petp7 vss petp5 petp4 petn2 vss vss tp34 ba ddpc_2p ddpc_2n ay ddpc_0p ddpc_0n vss ddpc_1p ddpc_1n vss petn7 petp8 petn5 petn4 petp2 tp36 vss tp38 aw vss vss petn8 vss vss vss tp40 vss vss av ddpb_3p ddpb_3n ddpb_1p ddpb_1n vss ddpb_0n ddpb_0p vss petp6 petn3 petn1 vss tp39 tp33 au ddpb_2n ddpb_2p petn6 petp3 petp1 vss tp35 tp37 at ddpb_aux n ddpb_aux p vss ddpd_aux n ddpd_aux p vss ddpb_hpd vss ddpc_hpd vss vss vss vss vss ar vss ap ddpc_aux p ddpc_aux n vss sdvo_tvcl kinp sdvo_tvcl kinn vss sdvo_intp sdvo_intn vss vcctx_lvd s vcctx_lvd s vss vss vss vccio an lvdsa_dat a#0 lvdsa_dat a0 vccio vccio vss vss vccio vccio am lvdsa_dat a1 lvdsa_dat a#1 vss vss vss sdvo_stal ln sdvo_stal lp vss vcctx_lvd s vcctx_lvd s vss al vss vss vss vss vccio vss vss ak lvdsa_dat a2 lvdsa_dat a#2 vss tp9 tp8 vss lvdsa_clk lvdsa_clk # vss vssalvds vccalvds aj lvdsa_dat a#3 lvdsa_dat a3 vss vss vcccore vcccore vcccore vcccore ah lvdsb_dat a1 lvdsb_dat a#1 vss lvdsb_dat a#0 lvdsb_dat a0 vss vss vss tp6 tp7 vss ag vss vccdiffclk n vccssc vss vcccore vcccore vcccore af lvdsb_dat a#2 lvdsb_dat a2 vss lvdsb_dat a#3 lvdsb_dat a3 vss lvdsb_clk # lvdsb_clk vss lvd_ibg lvd_vbg vccdiffclk n vccdiffclk n vss vss vss vss
datasheet 291 ballout definition figure 6-6. mobile pch ballout (top view - lower left) ae lvd_vrefh lvd_vrefl ad vccaclk vss vss vss vss vss vss vss vss vss vss vss vss vccasw vccasw vss vss ac vss vss vss vccasw vccasw vccasw vccasw ab clkout_pc ie1n clkout_pc ie1p tp19 tp20 vss clkout_pe g_b_n clkout_pe g_b_p vss clkout_pe g_a_p clkout_pe g_a_n vccclkdmi aa clkout_pc ie2n clkout_pc ie2p vss vss vccasw vccasw vccasw vccasw y vccvrm xclk_rco mp vss clkout_pc ie4p clkout_pc ie4n vss clkout_pc ie0n clkout_pc ie0p vss clkout_pc ie3n clkout_pc ie3p w vss vss vccasw vccasw vccasw vss vccasw v xtal25_ou t xtal25_in clkout_pc ie5p clkout_pc ie5n vss clkout_pc ie6p clkout_pc ie6n vss clkout_pc ie7n clkout_pc ie7p vss vcc3_3 vcc3_3 vss vss vss vss u vccadac vssadac t crt_red vss vss l_ctrl_cl k dac_iref crt_irtn l_ddc_clk crt_ddc_c lk vcc3_3 vss vss vcc3_3 vss vss vccio vccio vccio r vss p crt_green vss ddpc_ctrl clk l_bkltctl vss ddpc_ctrl data vss l_ctrl_da ta sdvo_ctrl clk nc_1 v5ref vccsushda vss vccio vccio n crt_blue vss hda_bclk hda_dock _rst# / gpio13 tp11 usbp7n vccio m crt_vsync crt_hsync vss l_vdd_en ddpd_ctrl clk vss crt_ddc_d ata sdvo_ctrl data vss ddpd_ctrl data vss vss vss usbp7p v5ref_sus l vss vss hda_sync usbp11n usbp8n vss vss k clkoutfle x3 / gpio67 l_ddc_dat a vss refclk14in clkoutfle x0 / gpio64 clkout_pc i3 pirqa# vss pirqb# ldrq1# / gpio23 hda_rst# usbp11p usbp8p usbp3n vss j clkout_pc i2 l_bklten h clkout_pc i0 clkoutfle x2 / gpio66 vss clkin_pcil oopback clkout_pc i1 clkout_pc i4 pirqc# gpio6 vss vss vss usbp3p vss g vss pirqe# / gpio2 pirqf# / gpio3 pirqd# vss hda_sdin1 usbp12n usbp9n vss vss f vss_nctf clkoutfle x1 / gpio65 gnt3# / gpio55 vss e vss_nctf gnt2# / gpio53 req3# / gpio54 gpio7 ldrq0# hda_sdin0 usbp12p usbp9p usbp4n vss d vss_nctf gnt1# / gpio51 pirqh# / gpio5 vss gpio17 vss fwh4 / lframe# vss vss vss usbp4p vss c vss_nctf req1# / gpio50 req2# / gpio52 pirqg# / gpio4 gpio70 gpio68 fwh0 / lad0 fwh3 / lad3 hda_dock _en# / gpio33 hda_sdin2 usbrbias# usbp13n usbp10n usbp6n usbp5n usbp2n b vss_nctf vss gpio69 vss fwh2 / lad2 vss usbrbias vss usbp6p vss a vss_nctf vss_nctf vss_nctf gpio1 gpio71 fwh1 / lad1 hda_sdo hda_sdin3 usbp13p usbp10p usbp5p usbp2p 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
292 datasheet ballout definition figure 6-7. mobile pch ballo ut (top view - upper right) 25242322212019181716151413121110987654321 dmi_zcom p vccapllex p dmi3rxp dmi2rxp tp4 fdi_rxn0 fdi_rxn5 fdi_rxp6 v_proc_io vss_nctf vss_nctf vss_nctf bj tp3 vccaplld mi2 dmi2rbias vss vss vss fdi_rxn3 vss fdi_rxp7 vss vss_nctf bh dmi_ircom p vss vss vss dmi3rxn dmi2rxn vss tp5 fdi_rxp0 fdi_rxp3 fdi_rxp5 fdi_rxn6 fdi_rxn7 vss vccafdipl l reserved vss_nctf bg vss vss vss clkin_dmi _n vss fdi_rxp2 vss vss vss reserved reserved vss_nctf bf dmi0rxp vss dmi1rxn clkin_dmi _p vss fdi_rxn2 fdi_rxp4 vss reserved vss_nctf be vss reserved vss vss_nctf bd dmi0rxn vss dmi1rxp vss vss vss fdi_rxn4 fdi_fsync 1 reserved vss bc vss vss vss dmi2txn vss fdi_rxp1 vss fdi_lsync 1 reserved reserved vss reserved reserved bb reserved reserved ba dmi0txp vss dmi1txp dmi2txp tp23 fdi_rxn1 vss procpwr gd thrmtrip# vss reserved reserved vss reserved df_tvs ay dmi0txn vss dmi1txn vss fdi_int vss vss aw vss clkout_d mi_n vss dmi3txn vss fdi_lsync 0 fdi_fsync 0 vss reserved vss reserved reserved vss reserved reserved av vss clkout_d mi_p vccdmi dmi3txp peci reserved reserved au vccio vss vccdmi vss vccvrm vss reserved vss reserved reserved vss reserved reserved reserved reserved at vss ar vccio vccio vccio vss vccio vccvrm pmsynch vss vss sata1txn sata1txp vss sata0txn sata0txp vss vss vss ap vccsus3_3 dcpsus vccio vccio vccio vccio vss vss an vss clkout_d p_p clkout_d p_n vss sata1rxn sata1rxp vss tp15 tp14 sata0rxn sata0rxp am dcpsus vss vss vss vss vss vss al clkout_it pxdp_n clkout_it pxdp_p vss ts_vss2 ts_vss4 vss clkin_sat a_n clkin_sat a_p vss vss vccapllsa ta ak vss vcccore vss vss vccdfter m vccdfter m vss vcc3_3 aj vccio vccio tp13 vss vs_tss3 ts_vss1 vss sata2txn sata2txp vss sata3rbia s ah vcccore vcccore vcccore vss vccdfter m vccdfter m vss ag vss vcccore vcccore vss vccio vss vccio vccio vss vccvrm vss vss vss vss vss sata3txn sata3txp af
datasheet 293 ballout definition figure 6-8. mobile pch ballo ut (top view - lower right) vss vss ae vss vcccore vcccore vss vccio vss vss vss vss vss vss vss sata2rxn sata2rxp vss sata4txn sata4txp ad vss vcccore vss vss vccio vccio vss ac vss sata3com pi sata3rco mpo vss sata3rxp sata3rxn vss vss vss sata5txn sata5txp ab vccasw vcccore vccasw vccasw vss vcc3_3 vss vss aa spi_cs0# tp16 vss sataicom po sataicom pi vss sata4rxn sata4rxp vss sata5rxn sata5rxp y vccasw vccasw vccasw vss vss vcc3_3 vss w vccsus3_3 vccsus3_3 vccasw dcpsus vss dcpsst sata0gp / gpio21 sdataout 1 / gpio48 dcpsusbyp vss pcieclkrq 2# / gpio20 sata2gp / gpio36 vss serirq spi_mosi sata5gp / gpio49/ therm_al ert# vccspi v spi_miso sata4gp / gpio16 u vccsus3_3 vccsus3_3 vccasw vccasw dcpsus vccdsw3_3 init3_3v# pcieclkrq 6# / gpio45 vss cl_data1 spkr vss bmbusy# / gpio0 sclock / gpio22 vss spi_clk spi_cs1# t vss r vccsus3_3 vccsus3_3 vccsus3_3 vss vss sys_pwro k vss cl_rst1# gpio28 vss rcin# a20gate sataled# sata1gp / gpio19 p vss vccsus3_3 vccsus3_3 vss dcprtc susclk / gpio62 clkrun# / gpio32 sload / gpio38 n vss vss tp22 vss sml1data / gpio75 vss vss peg_a_cl krq# / gpio47 vss cl_clk1 sata3gp / gpio37 vss sdataout 0 / gpio39 pcieclkrq 1# / gpio18 m tp18 pwrok vss vss oc4# / gpio43 pcieclkrq 5# / gpio44 pcieclkrq 4# / gpio26 apwrok vss l tp17 intruder# oc1# / gpio40 vss suswarn# / suspwrdn ack/ gpio30 slp_lan# / gpio29 pcieclkrq 7# / gpio46 pme# vss jtag_tdi gpio35 sys_reset # stp_pci# / gpio34 k jtag_tck pcieclkrq 0# / gpio73 j vss vss acpresen t / gpio31 vss vss smbclk vss vss jtag_tms vss slp_s4# tp12 jtag_tdo h clkin_dot _96n srtcrst# vss vss slp_sus# vss sml0data slp_a# sus_stat# / gpio61 gpio15 g slp_s3# vss vss_nctf f clkin_dot _96p dpwrok pwrbtn# vss gpio27 sml1clk / gpio58 smbalert # / gpio11 batlow# / gpio72 gpio24 peg_b_cl krq# / gpio56 vss_nctf e vss vss rtcrst# vss vss oc6# / gpio10 vss slp_s5# / gpio63 vss gpio57 vss vss_nctf d usbp1n usbp0n vss rsmrst# rtcx2 tp10 intvrmen oc3# / gpio42 oc7# / gpio14 sml1aler t# / pchhot# / gpio74 susack# gpio8 smbdata sml0clk pltrst# lan_phy_p wr_ctrl / gpio12 vss_nctf c usbp1p vss tp21 vss oc2# / gpio41 vss drampwr ok vss wake# vss vss_nctf b usbp0p vccrtc rtcx1 dswvrme n oc5# / gpio9 oc0# / gpio59 sml0aler t# / gpio60 ri# pcieclkrq 3# / gpio25 vss_nctf vss_nctf vss_nctf a 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
294 datasheet ballout definition table 6-2. mobile pch ballout by signal name mobile pch ball name ball # a20gate p4 acpresent / gpio31 h20 apwrok l10 batlow# / gpio72 e10 bmbusy# / gpio0 t7 cl_clk1 m7 cl_data1 t11 cl_rst1# p10 clkin_dmi_n bf18 clkin_dmi_p be18 clkin_dot_96n g24 clkin_dot_96p e24 clkin_gnd1_n bj30 clkin_gnd1_p bg30 clkin_pciloopbac k h45 clkin_sata_n ak7 clkin_sata_p ak5 clkout_dmi_n av22 clkout_dmi_p au22 clkout_dp_n am12 clkout_dp_p am13 clkout_itpxdp_n ak14 clkout_itpxdp_p ak13 clkout_pci0 h49 clkout_pci1 h43 clkout_pci2 j48 clkout_pci3 k42 clkout_pci4 h40 clkout_pcie0n y40 clkout_pcie0p y39 clkout_pcie1n ab49 clkout_pcie1p ab47 clkout_pcie2n aa48 clkout_pcie2p aa47 clkout_pcie3n y37 clkout_pcie3p y36 clkout_pcie4n y43 clkout_pcie4p y45 clkout_pcie5n v45 clkout_pcie5p v46 clkout_pcie6n v40 clkout_pcie6p v42 clkout_pcie7n v38 clkout_pcie7p v37 clkout_peg_a_n ab37 clkout_peg_a_p ab38 clkout_peg_b_n ab42 clkout_peg_b_p ab40 clkoutflex0 / gpio64 k43 clkoutflex1 / gpio65 f47 clkoutflex2 / gpio66 h47 clkoutflex3 / gpio67 k49 clkrun# / gpio32 n3 crt_blue n48 crt_ddc_clk t39 crt_ddc_data m40 crt_green p49 crt_hsync m47 crt_irtn t42 crt_red t49 crt_vsync m49 dac_iref t43 dcprtc n16 dcpsst v16 dcpsus al24 dcpsus t17 dcpsus v19 dcpsus an23 dcpsusbyp v12 ddpb_0n av42 ddpb_0p av40 ddpb_1n av45 ddpb_1p av46 ddpb_2n au48 ddpb_2p au47 ddpb_3n av47 ddpb_3p av49 ddpb_auxn at49 ddpb_auxp at47 ddpb_hpd at40 ddpc_0n ay47 ddpc_0p ay49 ddpc_1n ay43 mobile pch ball name ball # ddpc_1p ay45 ddpc_2n ba47 ddpc_2p ba48 ddpc_3n bb47 ddpc_3p bb49 ddpc_auxn ap47 ddpc_auxp ap49 ddpc_ctrlclk p46 ddpc_ctrldata p42 ddpc_hpd at38 ddpd_0n bb43 ddpd_0p bb45 ddpd_1n bf44 ddpd_1p be44 ddpd_2n bf42 ddpd_2p be42 ddpd_3n bj42 ddpd_3p bg42 ddpd_auxn at45 ddpd_auxp at43 ddpd_ctrlclk m43 ddpd_ctrldata m36 ddpd_hpd bh41 dmi_ircomp bg25 dmi_zcomp bj24 dmi0rxn bc24 dmi0rxp be24 dmi0txn aw24 dmi0txp ay24 dmi1rxn be20 dmi1rxp bc20 dmi1txn aw20 dmi1txp ay20 dmi2rbias bh21 dmi2rxn bg18 dmi2rxp bj18 dmi2txn bb18 dmi2txp ay18 dmi3rxn bg20 dmi3rxp bj20 dmi3txn av18 dmi3txp au18 dpwrok e22 mobile pch ball name ball #
datasheet 295 ballout definition drampwrok b13 dswvrmen a18 fdi_fsync0 av12 fdi_fsync1 bc10 fdi_int aw16 fdi_lsync0 av14 fdi_lsync1 bb10 fdi_rxn0 bj14 fdi_rxn1 ay14 fdi_rxn2 be14 fdi_rxn3 bh13 fdi_rxn4 bc12 fdi_rxn5 bj12 fdi_rxn6 bg10 fdi_rxn7 bg9 fdi_rxp0 bg14 fdi_rxp1 bb14 fdi_rxp2 bf14 fdi_rxp3 bg13 fdi_rxp4 be12 fdi_rxp5 bg12 fdi_rxp6 bj10 fdi_rxp7 bh9 fwh0 / lad0 c38 fwh1 / lad1 a38 fwh2 / lad2 b37 fwh3 / lad3 c37 fwh4 / lframe# d36 gnt1# / gpio51 d47 gnt2# / gpio53 e42 gnt3# / gpio55 f46 gpio1 a42 gpio6 h36 gpio7 e38 gpio8 c10 gpio15 g2 gpio17 d40 gpio24 e8 gpio27 e16 gpio28 p8 gpio35 k4 gpio57 d6 gpio68 c40 gpio69 b41 mobile pch ball name ball # gpio70 c41 gpio71 a40 hda_bclk n34 hda_dock_en# / gpio33 c36 hda_dock_rst# / gpio13 n32 hda_rst# k34 hda_sdin0 e34 hda_sdin1 g34 hda_sdin2 c34 hda_sdin3 a34 hda_sdo a36 hda_sync l34 init3_3v# t14 intruder# k22 intvrmen c17 jtag_tck j3 jtag_tdi k5 jtag_tdo h1 jtag_tms h7 l_bkltctl p45 l_bklten j47 l_ctrl_clk t45 l_ctrl_data p39 l_ddc_clk t40 l_ddc_data k47 l_vdd_en m45 lan_phy_pwr_ctr l / gpio12 c4 ldrq0# e36 ldrq1# / gpio23 k36 lvd_ibg af37 lvd_vbg af36 lvd_vrefh ae48 lvd_vrefl ae47 lvdsa_clk ak40 lvdsa_clk# ak39 lvdsa_data#0 an48 lvdsa_data#1 am47 lvdsa_data#2 ak47 lvdsa_data#3 aj48 lvdsa_data0 an47 lvdsa_data1 am49 lvdsa_data2 ak49 mobile pch ball name ball # lvdsa_data3 aj47 lvdsb_clk af39 lvdsb_clk# af40 lvdsb_data#0 ah45 lvdsb_data#1 ah47 lvdsb_data#2 af49 lvdsb_data#3 af45 lvdsb_data0 ah43 lvdsb_data1 ah49 lvdsb_data2 af47 lvdsb_data3 af43 ts_vss1 ah8 ts_vss2 ak11 ts_vss3 ah10 ts_vss4 ak10 nc_1 p37 reserved av5 reserved ay7 reserved av7 reserved au3 reserved bg4 df_tvs ay1 reserved au2 reserved at4 reserved bb5 reserved bb3 reserved bb7 reserved be8 reserved bd4 reserved bf6 reserved at3 reserved at1 reserved ay3 reserved at5 reserved av3 reserved av1 reserved bb1 reserved ba3 reserved at10 reserved bc8 reserved at8 reserved av10 reserved ay5 reserved ba2 mobile pch ball name ball #
296 datasheet ballout definition reserved at12 reserved bf3 oc0# / gpio59 a14 oc1# / gpio40 k20 oc2# / gpio41 b17 oc3# / gpio42 c16 oc4# / gpio43 l16 oc5# / gpio9 a16 oc6# / gpio10 d14 oc7# / gpio14 c14 pcieclkrq0# / gpio73 j2 pcieclkrq1# / gpio18 m1 pcieclkrq2# / gpio20 v10 pcieclkrq3# / gpio25 a8 pcieclkrq4# / gpio26 l12 pcieclkrq5# / gpio44 l14 pcieclkrq6# / gpio45 t13 pcieclkrq7# / gpio46 k12 peci au16 peg_a_clkrq# / gpio47 m10 peg_b_clkrq# / gpio56 e6 pern1 bg34 pern2 be34 pern3 bg36 pern4 bf36 pern5 bg37 pern6 bj38 pern7 bg40 pern8 be38 perp1 bj34 perp2 bf34 perp3 bj36 perp4 be36 perp5 bh37 perp6 bg38 perp7 bj40 perp8 bc38 petn1 av32 mobile pch ball name ball # petn2 bb32 petn3 av34 petn4 ay34 petn5 ay36 petn6 au36 petn7 ay40 petn8 aw38 petp1 au32 petp2 ay32 petp3 au34 petp4 bb34 petp5 bb36 petp6 av36 petp7 bb40 petp8 ay38 pirqa# k40 pirqb# k38 pirqc# h38 pirqd# g38 pirqe# / gpio2 g42 pirqf# / gpio3 g40 pirqg# / gpio4 c42 pirqh# / gpio5 d44 pltrst# c6 pme# k10 pmsynch ap14 procpwrgd ay11 pwrbtn# e20 pwrok l22 rcin# p5 refclk14in k45 req1# / gpio50 c46 req2# / gpio52 c44 req3# / gpio54 e40 ri# a10 rsmrst# c21 rtcrst# d20 rtcx1 a20 rtcx2 c20 sata0gp / gpio21 v14 sata0rxn am3 sata0rxp am1 sata0txn ap7 sata0txp ap5 mobile pch ball name ball # sata1gp / gpio19 p1 sata1rxn am10 sata1rxp am8 sata1txn ap11 sata1txp ap10 sata2gp / gpio36 v8 sata2rxn ad7 sata2rxp ad5 sata2txn ah5 sata2txp ah4 sata3compi ab13 sata3gp / gpio37 m5 sata3rbias ah1 sata3rcompo ab12 sata3rxn ab8 sata3rxp ab10 sata3txn af3 sata3txp af1 sata4gp / gpio16 u2 sata4rxn y7 sata4rxp y5 sata4txn ad3 sata4txp ad1 sata5gp / gpio49/ therm_alert# v3 sata5rxn y3 sata5rxp y1 sata5txn ab3 sata5txp ab1 sataicompi y10 sataicompo y11 sataled# p3 sclock / gpio22 t5 sdataout0 / gpio39 m3 sdataout1 / gpio48 v13 sdvo_ctrlclk p38 sdvo_ctrldata m39 sdvo_intn ap39 sdvo_intp ap40 sdvo_stalln am42 sdvo_stallp am40 sdvo_tvclkinn ap43 sdvo_tvclkinp ap45 mobile pch ball name ball #
datasheet 297 ballout definition serirq v5 sload / gpio38 n2 slp_a# g10 slp_lan# / gpio29 k14 slp_s3# f4 slp_s4# h4 slp_s5# / gpio63 d10 slp_sus# g16 smbalert# / gpio11 e12 smbclk h14 smbdata c9 sml0alert# / gpio60 a12 sml0clk c8 sml0data g12 sml1alert# / pchhot# / gpio74 c13 sml1clk / gpio58 e14 sml1data / gpio75 m16 spi_clk t3 spi_cs0# y14 spi_cs1# t1 spi_miso u3 spi_mosi v4 spkr t10 srtcrst# g22 stp_pci# / gpio34 k1 sus_stat# / gpio61 g8 susack# c12 susclk / gpio62 n14 suswarn#/ suspwrdnack/ gpio30 k16 sys_pwrok p12 sys_reset# k3 thrmtrip# ay10 tp1 bg26 tp2 bj26 tp3 bh25 tp4 bj16 tp5 bg16 tp6 ah38 tp7 ah37 tp8 ak43 mobile pch ball name ball # tp9 ak45 tp10 c18 tp11 n30 tp12 h3 tp13 ah12 tp14 am4 tp15 am5 tp16 y13 tp17 k24 tp18 l24 tp19 ab46 tp20 ab45 tp21 b21 tp22 m20 tp23 ay16 tp24 bg46 tp25 be28 tp26 bc30 tp27 be32 tp28 bj32 tp29 bc28 tp30 be30 tp31 bf32 tp32 bg32 tp33 av26 tp34 bb26 tp35 au28 tp36 ay30 tp37 au26 tp38 ay26 tp39 av28 tp40 aw30 usbp0n c24 usbp0p a24 usbp1n c25 usbp1p b25 usbp2n c26 usbp2p a26 usbp3n k28 usbp3p h28 usbp4n e28 usbp4p d28 usbp5n c28 usbp5p a28 mobile pch ball name ball # usbp6n c29 usbp6p b29 usbp7n n28 usbp7p m28 usbp8n l30 usbp8p k30 usbp9n g30 usbp9p e30 usbp10n c30 usbp10p a30 usbp11n l32 usbp11p k32 usbp12n g32 usbp12p e32 usbp13n c32 usbp13p a32 usbrbias b33 usbrbias# c33 v_proc_io bj8 v5ref p34 v5ref_sus m26 vcc3_3 aj2 vcc3_3 t34 vcc3_3 aa16 vcc3_3 w16 vcc3_3 t38 vcc3_3 bh29 vcc3_3 v33 vcc3_3 v34 vccaclk ad49 vccadac u48 vccadplla bd47 vccadpllb bf47 vccafdipll bg6 vccalvds ak36 vccaplldmi2 bh23 vccapllexp bj22 vccapllsata ak1 vccasw t19 vccasw v21 vccasw t21 vccasw aa19 vccasw aa21 mobile pch ball name ball #
298 datasheet ballout definition vccasw aa24 vccasw aa26 vccasw aa27 vccasw aa29 vccasw aa31 vccasw ac26 vccasw ac27 vccasw ac29 vccasw ac31 vccasw ad29 vccasw ad31 vccasw w21 vccasw w23 vccasw w24 vccasw w26 vccasw w29 vccasw w31 vccasw w33 vccclkdmi ab36 vcccore aa23 vcccore ac23 vcccore ad21 vcccore ad23 vcccore af21 vcccore af23 vcccore ag21 vcccore ag23 vcccore ag24 vcccore ag26 vcccore ag27 vcccore ag29 vcccore aj23 vcccore aj26 vcccore aj27 vcccore aj29 vcccore aj31 vccdiffclkn af33 vccdiffclkn af34 vccdiffclkn ag34 vccdmi au20 vccdmi at20 vccdsw3_3 t16 vccio n26 vccio p26 mobile pch ball name ball # vccio p28 vccio t27 vccio t29 vccio af13 vccio ac16 vccio ac17 vccio ad17 vccio af14 vccio ap17 vccio an19 vccio al29 vccio af17 vccio t26 vccio ah13 vccio ah14 vccio an16 vccio an17 vccio an21 vccio an26 vccio an27 vccio ap21 vccio ap23 vccio ap24 vccio ap26 vccio at24 vccio an33 vccio an34 vccdfterm ag16 vccdfterm ag17 vccdfterm aj16 vccdfterm aj17 vccrtc a22 vccspi v1 vccssc ag33 vccsus3_3 an24 vccsus3_3 t23 vccsus3_3 t24 vccsus3_3 v23 vccsus3_3 v24 vccsus3_3 n20 vccsus3_3 n22 vccsus3_3 p20 vccsus3_3 p22 mobile pch ball name ball # vccsus3_3 p24 vccsushda p32 vcctx_lvds am37 vcctx_lvds am38 vcctx_lvds ap36 vcctx_lvds ap37 vccvrm y49 vccvrm af11 vccvrm ap16 vccvrm at16 vss aj3 vss n24 vss bg29 vss h5 vss aa17 vss aa2 vss aa3 vss aa33 vss aa34 vss ab11 vss ab14 vss ab39 vss ab4 vss ab43 vss ab5 vss ab7 vss ac19 vss ac2 vss ac21 vss ac24 vss ac33 vss ac34 vss ac48 vss ad10 vss ad11 vss ad12 vss ad13 vss ad14 vss ad16 vss ad19 vss ad24 vss ad26 vss ad27 vss ad33 mobile pch ball name ball #
datasheet 299 ballout definition vss ad34 vss ad36 vss ad37 vss ad38 vss ad39 vss ad4 vss ad40 vss ad42 vss ad43 vss ad45 vss ad46 vss ad47 vss ad8 vss ae2 vss ae3 vss af10 vss af12 vss af16 vss af19 vss af24 vss af26 vss af27 vss af29 vss af31 vss af38 vss af4 vss af42 vss af46 vss af5 vss af7 vss af8 vss ag19 vss ag2 vss ag31 vss ag48 vss ah11 vss ah3 vss ah36 vss ah39 vss ah40 vss ah42 vss ah46 vss ah7 vss aj19 mobile pch ball name ball # vss aj21 vss aj24 vss aj33 vss aj34 vss ak12 vss ak3 vss ak38 vss ak4 vss ak42 vss ak46 vss ak8 vss al16 vss al17 vss al19 vss al2 vss al21 vss al23 vss al26 vss al27 vss al31 vss al33 vss al34 vss al48 vss am11 vss am14 vss am36 vss am39 vss am43 vss am45 vss am46 vss am7 vss an2 vss an29 vss an3 vss an31 vss ap12 vss ap13 vss ap19 vss ap28 vss ap30 vss ap32 vss ap38 vss ap4 vss ap42 mobile pch ball name ball # vss ap46 vss ap8 vss ar2 vss ar48 vss at11 vss at13 vss at18 vss at22 vss at26 vss at28 vss at30 vss at32 vss at34 vss at39 vss at42 vss at46 vss at7 vss au24 vss au30 vss av11 vss av16 vss av20 vss av24 vss av30 vss av38 vss av4 vss av43 vss av8 vss aw14 vss aw18 vss aw2 vss aw22 vss aw26 vss aw28 vss aw32 vss aw34 vss aw36 vss aw40 vss aw48 vss ay12 vss ay22 vss ay28 vss ay4 vss ay42 mobile pch ball name ball #
300 datasheet ballout definition vss ay46 vss ay8 vss b11 vss b15 vss b19 vss b23 vss b27 vss b31 vss b35 vss b39 vss b43 vss b7 vss bb12 vss bb16 vss bb20 vss bb22 vss bb24 vss bb28 vss bb30 vss bb38 vss bb4 vss bb46 vss bc14 vss bc18 vss bc2 vss bc22 vss bc26 vss bc32 vss bc34 vss bc36 vss bc40 vss bc42 vss bc48 vss bd3 vss bd46 vss bd5 vss be10 vss be22 vss be26 vss be40 vss bf10 vss bf12 vss bf16 vss bf20 mobile pch ball name ball # vss bf22 vss bf24 vss bf26 vss bf28 vss bf30 vss bf38 vss bf40 vss bf8 vss bg17 vss bg21 vss bg22 vss bg24 vss bg33 vss bg41 vss bg44 vss bg8 vss bh11 vss bh15 vss bh17 vss bh19 vss bh27 vss bh31 vss bh33 vss bh35 vss bh39 vss bh43 vss bh7 vss c22 vss d12 vss d16 vss d18 vss d22 vss d24 vss d26 vss d3 vss d30 vss d32 vss d34 vss d38 vss d42 vss d8 vss e18 vss e26 vss f3 mobile pch ball name ball # vss f45 vss g14 vss g18 vss g20 vss g26 vss g28 vss g36 vss g48 vss h10 vss h12 vss h16 vss h18 vss h22 vss h24 vss h26 vss h30 vss h32 vss h34 vss h46 vss k18 vss k26 vss k39 vss k46 vss k7 vss l18 vss l2 vss l20 vss l26 vss l28 vss l36 vss l48 vss m12 vss m14 vss m18 vss m22 vss m24 vss m30 vss m32 vss m34 vss m38 vss m4 vss m42 vss m46 vss m8 mobile pch ball name ball #
datasheet 301 ballout definition vss n18 vss n47 vss p11 vss p16 vss p18 vss p30 vss p40 vss p43 vss p47 vss p7 vss r2 vss r48 vss t12 vss t31 vss t33 vss t36 vss t37 vss t4 vss t46 vss t47 vss t8 vss v11 vss v26 vss v27 vss v29 vss v31 vss v36 vss v39 vss v43 vss v7 vss w17 vss w19 vss w2 vss w27 vss w34 vss w48 vss y12 vss y38 vss y4 vss y42 vss y46 vss y8 vss v17 vss ap3 mobile pch ball name ball # vss ap1 vss be16 vss bc16 vss bg28 vss bj28 vss_nctf a4 vss_nctf a44 vss_nctf a45 vss_nctf a46 vss_nctf a5 vss_nctf a6 vss_nctf b3 vss_nctf b47 vss_nctf bd1 vss_nctf bd49 vss_nctf be1 vss_nctf be49 vss_nctf bf1 vss_nctf bf49 vss_nctf bg2 vss_nctf bg48 vss_nctf bh3 vss_nctf bh47 vss_nctf bj4 vss_nctf bj44 vss_nctf bj45 vss_nctf bj46 vss_nctf bj5 vss_nctf bj6 vss_nctf c2 vss_nctf c48 vss_nctf d1 vss_nctf d49 vss_nctf e1 vss_nctf e49 vss_nctf f1 vss_nctf f49 vssadac u47 vssalvds ak37 wake# b9 xclk_rcomp y47 xtal25_in v47 xtal25_out v49 mobile pch ball name ball #
ballout definition 302 datasheet 6.3 mobile sff pch ballout figure 6-9 , figure 6-10 , figure 6-11 and figure 6-12 show the ballout from a top of the package quadrant view. figure 6-9. mobile sff pch package (top view C upper left) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 bl vss_ nct f vss_ nct f vss_ nct f ddpd _2p ddpd _3n perp8 perp7 perp5 perp4 perp2 perp1 tp31 tp32 tp30 bk vss ddpd _hpd vss perp6 vss perp3 vss vss vss vcc3 _3 vss bj vss_ nct f vss_ nct f tp21 ddpd _2n ddpd _3p pern8 pern7 pern5 pern4 pern2 pern1 tp27 tp28 tp26 bh vss_ nct f tp41 vss vss vss vss pern6 vss pern3 vss vss vss vss vss bg ddpd _0n ddpd _0p bf vss vss ddpc _2n ddpc _2p ddpd _1n vc c a d plla petp6 petp4 petn3 tp36 tp35 tp33 be ddpc _3p ddpc _3n ddpc _hpd vss vss vss vss vss vss vss vss vss bd ddpc _1p ddpc _1n ddpd _1p vc c a d pllb petn6 petn4 petp3 tp40 tp39 tp37 bc ddpc _0p ddpc _0n vss vss vss vss vss vss vss vss vss bb vss vss ddpb _2p ddpb _2n tp42 petp8 petp7 petp5 petn2 petn1 tp34 clkin _gnd1 _n ba ddpb _3p ddpb _3n vss vss vss vss vss vss vss vss vss ay ddpb _0p ddpb _0n ddpb _1p ddpb _1n ddpb _hpd petn8 petn7 petn5 petp2 petp1 tp38 clkin _gnd1 _p aw ddpb _auxn ddpb _auxp vss vss vss vss vss vcci o vcca plld mi2 vss vss av vss vss au ddpc _auxn ddpc _auxp ddpd _auxn ddpd _auxp sdvo_ tvclk inp sdvo_ tvclk inn vss vcci o dcpsu s dcps us vccio vccio at sdvo_ intn sdvo_ intp vss vss vss vss ar sdvo_ stall n sdvo_ stall p lvdsa _data #0 lvdsa _data 0 tp 9 tp8 vss vss dcpsu s vss vccio vccio ap vss vss vss vss vss vccclk dmi vss vss vss vss vss vccio an lvdsa _data 1 lvdsa _data #1 lvdsa _data 2 lvdsa _data #2 tp 6 tp7 am lvdsb _data #0 lvdsb _data 0 vss vccc ore vccc ore vss vss vccs us3 _ 3 al lvdsb _data 1 lvdsb _data #1 vss vss vss vss ak vss vss lvdsa _clk lvdsa _clk# lvdsa _data 3 lvdsa _data #3 vss vss vccc ore vccc ore vccc ore vss aj lvdsb _data #2 lvdsb _data 2 vss vss vss vss vcctx _lvds vss vss vccc ore vccc ore vccc ore ah lvdsb _data #3 lvdsb _data 3 lvdsb _clk# lvdsb _clk lvd_i bg lvd_v bg ag lvd_v refh lvd_v refl vss vss vss vcctx _lvds vcctx _lvds vss vc c a l vd s vss vss vccc ore af vss vss clko ut_pe g_a _p clko ut_pe g_a _n clko ut_pe g_b _p clko ut_pe g_b_n vcctx _lvds vss vc c a l vd s vss vss vss
datasheet 303 ballout definition figure 6-10. mobile sff pch package (top view C lower left) ball o clko ut_pc ie1p clko ut_pc ie1n vss vss vss vccd iffc lkn vccd iffc lkn vss vssa lv ds vc c a s w vc c a s w vc c a s w ad clko ut_pc ie0p clko ut_pc ie0n tp 20 tp19 clko ut_pc ie2p clko ut_pc ie2n ac vccac lk xclk _ rcom p vss vss vss vc c vr m vccd iffc lkn vccss c vssa lv ds vc c a s w vc c a s w vc c a s w ab vss vss clko ut_pc ie6p clko ut_pc ie6n clko ut_pc ie5p clko ut_pc ie5n vss vss vss vc c a s w vc c a s w vc c a s w aa clko ut_pc ie3p clko ut_pc ie3n vss vss vss vss y clko ut_pc ie4p clko ut_pc ie4n vss vss vss vc c a s w vc c a s w vc c a s w w xta l 2 5_out xta l 2 5_in clko ut_pc ie7p clko ut_pc ie7n sdvo_ ctrlc lk tp23 v vs s a _ dac vss vss vss vss vc c 3 _ 3 vc c 3 _ 3 vss vss vc c s u shda vss vss u vccad ac vss crt_r ed ddpc _ctrl data ddpd _ctrl data nc_1 vc c 3 _ 3 vccsu s3_3 vc c s u s3_3 vss vc cp usb vccp usb t ddpc _ctrl clk crt_i rtn vss vss vss vc c 3 _ 3 r dac_i ref crt_d dc_cl k crt_g reen sdvo_ ctrld ata l_ctr l_clk vcc3_ 3 vss vccsu s3_3 vc c s u s3_3 vss vccsu s3_3 vc c s u s3_3 p vss vss n crt_v sync crt_d dc_d ata vss vss vss vss v5ref vss vss vss vc c s u s3_3 m crt_h sync ddpd _ctrl clk crt_b lue l_bkl ten l_vdd _en l_ctr l_dat a v5ref _sus hda_ dock _rst# usbp1 3n tp 11 usbp 8n usbp 4n l l_ddc _clk l_bkl tctl vss vss vss vss vss vss vss vss vss k vss vss l_ddc _data req2# / gp io5 tach4 / gpio6 fwh4 / lfra me# hda_ sdo hda_ dock _en# / usbp1 3p tp24 usbp 8p usbp 4p j clko utfle x3 / refcl k14in vss clko ut_pc i3 vss vss vss vss vss vss vss h clko utfle x0 / clko ut_pc i2 gnt2# / gpio5 ldrq0 # hda_ sync hda_ bclk usbp1 1n usbp1 2n usbp 3n usbp 6n g clko ut_pc i0 clko utfle x2 / req1# / gp io5 clko ut_pc i4 vss vss vss vss vss vss vss vss f vss vss req3# / gp io5 pirqg # / gp io4 gnt1# / gpio5 pirqh # / gp io5 ldrq1 # / gpio2 hda_ rst# usbp1 1p usbp1 2p usbp 3p usbp 6p e clkin _pcil oop b clko ut_pc i1 d vss_ nct f pirqa # clko utfle x1 / vss gnt3# / gp io5 vss ta ch6 / gp io7 vss hda_ sdin0 vss usbp 7n vss usbp 5n vss c vss_ nct f vss_ nct f pirqb # pirqc # pirqd # tach2 / gpio6 pirqf # / gp io3 fwh2 / lad2 fwh3 / lad3 hda_ sdin2 usbr bias# usbp1 0n usbp 9n usbp 2n b vss tach0 / gpio1 vss ta ch1 / gp io1 vss hda_ sdin1 vss usbp 7p vss usbp 5p vss a vss_ nct f vss_ nct f vss_ nct f pirqe # / gp io2 ta ch3 / gp io7 tach5 / gpio6 tach7 / gp io7 fwh1 / lad1 fwh0 / lad0 hda_ sdin3 usbr bias usbp1 0p usbp 9p usbp 2p 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
ballout definition 304 datasheet figure 6-11. mobile sff pch pa ckage (top view C upper right) 25242322212019181716151413121110987654321 tp29 dmi1r xn dmi0r xn dmi2r xp dmi3r xn fdi_r xp 1 fdi_r xn0 fdi_r xp 3 fdi_r xp 6 tp22 rsvd vss_ nct f vss_ nct f vss_ nct f bl tp2 vss dmi2r bias vss tp 4 vss fdi_l sync0 vss fdi_f sync1 rsvd bk tp25 dmi1r xp dmi0r xp dmi2r xn dmi3r xp fdi_r xn1 fdi_r xp 0 fdi_r xn3 fdi_r xn6 rsvd rsvd rsvd vss_ nct f vss_ nct f bj tp1 vss tp3 vss tp 5 vss fdi_f sync0 vss fdi_l sync1 vss rsvd rsvd vss_ nct f bh rsvd rsvd bg vss dmi0t xp dmi_z comp clkin _dmi_ p vss fdi_r xp 2 fdi_r xn7 rsvd rsvd vss vss bf vss vss vss vss vss vss vss vss vss rsvd rsvd rsvd be vss dmi0t xn dmi_i rcom p clkin _dmi_ n vss fdi_r xn2 fdi_r xp 7 rs vd rs vd bd vss vss vss vss vss vss vss thrm trip# df_tv s rsvd rsvd bc clko ut_d mi_n dmi1t xn dmi2t xn dmi3t xn fdi_r xp 4 fdi_r xp 5 fdi_in t pmsy nch rsvd vss vss bb vss vss vss vss vss vss vss vss vss rsvd rsvd ba clko ut_d mi_p dmi1t xp dmi2t xp dmi3t xp fdi_r xn4 fdi_r xn5 vss rs vd rs vd rs vd rs vd ay vss vss vccvr m vc c vr m vccdm i vss vss vss vss rsvd rsvd aw vss vss av vccio vccio vcca dmi_v rm vcca f di_vr m vss vccdm i peci proc pwrg d rsvd rsvd sata0 txn sata0 txp au vcci o vss vss vss tp14 tp15 at vccio vccio vss vss vss vcci o clko ut_it pxdp_ clko ut_it pxdp_ vss vss sata1 txn sata1 txp ar vss vss vss vc c a p llexp vss vc c a f dipll vccaf dipll vss vss vss vss vss ap clko ut_dp _p clko ut_dp _n sata1 rxp sata1 rxn sata0 rxn sata0 rxp an vss vccdm i vc c i o vss v_p ro c_io vss tp13 vcc a pll_s ata3 am vccdf term vss vss vss sata2 txn sata2 txp al vss vss vc c i o vss vss vc c df term ts_vs s3 ts_vs s1 clkin _sata _n clkin _sata _p vss vss ak vccc ore vccc ore vccc ore vss vcci o vc c df term vccdf term vss vss vss sata5 txn sata5 txp aj ts_vs s2 ts_vs s4 sata4 txn sata4 txp sata3 rbias vss ah vccc ore vccc ore vccc ore vss vss vcci o vcci o vss vss vss sata3 txn sata3 txp ag vss vccc ore vccc ore vss vccv rm vc c i o sata3 compi sata3 rcom po vss vcc3 _3 vss vss af
datasheet 305 ballout definition figure 6-12. mobile sff pch package (top view C lower right) vss vccc ore vccc ore vccv rm vss vss vss vss vss vss sata4 rxn sata4 rxp ae spi_c lk tp16 sata3 rxn sata3 rxp sata2 rxn sata2 rxp ad vss vccc ore vccc ore vc c 3 _ 3 vss vcci o vcci o vss vss vss sata5 rxn sata5 rxp ac vss vccc ore vccc ore vc c 3 _ 3 vss vcci o satai compi satai comp o spi_c s0# spi_c s1# vss vss ab vccio vss vss vss sata4 gp / gp io1 sata5 gp / gpio4 aa vc c a s w vccas w vc c a s w vc c s p i vss vss serir q spi_m iso y gp io3 5 satal ed# spi_m osi sata2 gp / gp io3 sclo ck / gp io2 bmbu sy# / gpio0 w vc c a s w vccas w vc c a s w vc c a s w vss vss dc psu s vss vss vss vss vss v vccio vccio vc c a s w vc c a s w dcpss t dcprt c jtag_ tdi sdat a out0 / pciec lkrq1 # / rcin# a20ga te sdat aout1 / u vss vss vss vss pciec lkrq2 # / clkr un# / gp io3 t vccio vccio vss vc c a s w vss dcprt c vc c ds w3_3 dc psu sb y p peg_a _clkr q# / init3_ 3v# stp_p ci# / gp io3 sata1 gp / gpio1 r vss vss p vss vss vss vc c io vc c rt c vss vss vss vss sloa d / gp io3 spkr n clkin _dot_ 96n pwro k pciec lkrq4 # / jtag_ tck jtag_ tms jtag_ tdo sys_p wrok cl_rs t1# sata3 gp / gp io3 pciec lkrq0 # / sata0 gp / gp io2 m vss vss vss vss vss vss vss vss vss cl_cl k1 sys_r es et# l clkin _dot_ 96p intru der# pwrb tn# gp io5 7 gp io2 4 / mem_ sml0 clk slp_s 4# pciec lkrq5 # / gp io1 5 vss vss k vss vss vss vss vss vss vss vss vss pciec lkrq6 # / cl_da ta1 j usbp 0p sml0 alert # / acpr es ent / gp io8 oc7# / gp io1 4 smba lert# / batlo w# / gpio7 pciec lkrq7 # / pme# h vss vss vss vss vss vss vss vss vss sus_ stat# / apwr ok gpio2 8 g usbp 0n dswv rmen rtcr st# smbc lk susa ck# ri# smbd ata pltrs tb# slp_s 5# / gp io6 vss vss f tp12 vss_ nct f e tp18 vss tp10 vss oc3# / gpio4 2 vss sml1c lk / gp io5 vss wa k e # vss slp_s 3# susc lk / gp io6 vss_ nct f d usbp1 n oc6# / gpio1 0 intvr men rtcx2 oc0# / gp io5 9 gp io2 7 susw arn# / susp sml1d ata / gp io7 sml1a lert# / slp_a # lan_p hy_p wr_ c peg_b _clkr q# / vss_ nct f c tp17 vss rsmr st# vss oc5# / gpio9 vss dram pwro k vss pciec lkrq3 # / vss b usbp1 p srtc rst# dpwr ok rtcx1 oc1# / gp io4 0 slp_s us# oc2# / gpio4 1 oc4# / gp io4 3 sml0 data slp_l an# / gpio2 vss_ nct f vss_ nct f a 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ballout definition 306 datasheet
datasheet 307 package information 7 package information 7.1 desktop pch package ? fcbga package ? package size: 27 mm x 27 mm ? ball count: 942 ? ball pitch: 0.7 mm the desktop pch package in formation is shown in figure 7-1 . note: all dimensions, unless otherwise specified, are in millimeters.
package information 308 datasheet figure 7-1. desktop pch package drawing
datasheet 309 package information 7.2 mobile pch package ? fcbga package ? package size: 25 mm x 25 mm ? ball count: 989 ? ball pitch: 0.6 mm the mobile pch package information is shown in figure 7-2 note: all dimensions, unless otherwise specified, are in millimeters.
package information 310 datasheet figure 7-2. mobile pch package drawing
datasheet 311 package information 7.3 mobile sff pch package ? fcbga package ? package size: 22 mm x 22 mm ? ball count: 1017 ? ball pitch: 0.59 mm the mobile sff pch package information is shown in figure 7-3 note: all dimensions, unless otherwise specified, are in millimeters.
package information 312 datasheet figure 7-3. mobile sf f pch package drawing
datasheet 313 electrical characteristics 8 electrical characteristics this chapter contains the dc and ac charac teristics for the pch. ac timing diagrams are included. 8.1 thermal specifications 8.1.1 desktop storage specificat ions and thermal design power (tdp) for desktop thermal information, refer to the intel ? 6 series chipset and up server / workstation platform controller hub (pch) ? thermal and mechanical specifications design guide 8.1.2 mobile storage specificatio ns and thermal design power (tdp) notes: 1. refers to a component device that is not assembled in a board or socket and is not electrically connected to a vo ltage reference or i/o signal. 2. specified temperatures are not to exceed valu es based on data collected. exceptions for surface mount reflow are specified by the a pplicable jedec standard. non-adherence may affect pch reliability. 3. t absolute storage applies to the unassembled componen t only and does not apply to the shipping media, moisture barrier bags, or desiccant. 4. intel branded products are specified and cert ified to meet the following temperature and humidity limits that are give n as an example only (non-o perating temperature limit: -40 c to 70 c and humidity: 50% to 90%, no n-condensing with a maximum wet bulb of 28 c.) post board attach st orage temperature limits are not specified for non-intel branded boards. 5. the jedec j-jstd-020 moisture level rating an d associated handling practices apply to all moisture sensitive devices remove d from the moisture barrier bag. table 8-1. storage conditions and therma l junction operating temperature limits parameter description min max notes t absolute storage the non-operating device storage temperature. damage (latent or otherwise) may occur when exceeded for any length of time. -25 c 125 c 1,2,3 t sustained storage the ambient storage temperature (in shipping media) for a sustained period of time. -5 c 40 c 4,5 rh sustained storage the maximum device storage relative humidity for a sustained period of time. 60% @ 24 c 5,6 time sustained storage a prolonged or extend ed period of time; typically associated with customer shelf life. 0 months 6 months 6 tj (mobile only) mobile thermal junction operating te m p e ra t u r e l i m i t s 0 c 108 c 7
electrical characteristics 314 datasheet 6. nominal temperature and humidity conditions and durations are give n and tested within the constraints imposed by t sustained storage and customer shel f life in applicable intel boxes and bags. 7. the thermal solution needs to ensure that the temperature does not exceed the maximum junction temperature (tj,max) limit. 8.2 absolute maximum ratings ta b l e 8 - 3 specifies absolute maximum and minimum ratings. at conditions outside functional operation condition limits, bu t within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. if a device is returned to conditions within functional op eration limits after having been subjected to conditions outside these limits (but within the absolute maximum and minimum ratings) the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. at conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. moreover, if a device is subjected to these conditions for any length of time, it will ei ther not function or its reliability will be severely degraded when returned to cond itions within the functional operating condition limits. although the pch contains protective circuitry to resist damage from electrostatic discharge (esd), precautions should always be taken to avoid high static voltages or electric fields. table 8-2. mobile thermal design power sku thermal design power (tdp) notes standard 3.9 w sff 3.4 w low power (intel ? um67 chipset) 3.4 w table 8-3. pch absolute maximum ratings parameter maximum limits voltage on any 5 v tolerant pin with respect to ground (v5ref = 5 v) -0.5 to v5ref + 0.5 v voltage on any 3.3 v pin with respect to ground -0.5 to vcc3_3 + 0.4 v voltage on any 1.8 v tolerant pin with re spect to ground -0.5 to vccvrm + 0.5 v voltage on any 1.5 v pin with respec t to ground -0.5 to vccvrm + 0.5 v voltage on any 1.05 v tolerant pin with re spect to ground -0.5 to vcccore + 0.5 v 1.05 v supply voltage with respect to vss -0.5 to 1.3 v 1.8 v supply voltage with respect to vss -0.5 to 1.98 v 3.3 v supply voltage with respect to vss -0.5 to 3.7 v 5.0 v supply voltage with respect to vss -0.5 to 5.5 v v_proc_io supply voltage with respect to vss -0.5 to 1.3 v 1.5 v supply voltage for the analog pll with respect to vss -0.5 to 1.65 v 1.8 v supply voltage for the analog pll with respect to vss -0.5 to 1.98 v
datasheet 315 electrical characteristics 8.3 pch power supply range 8.4 general dc characteristics notes: 1. g3 state shown to provide an estimate of battery life. table 8-4. pch power supply range power supply minimum nominal maximum 1.0 v 0.95 v 1.00 v 1.05 v 1.05 v 1.00 v 1.05 v 1.10 v 1.5 v 1.43 v 1.50 v 1.58 v 1.8 v 1.71 v 1.80 v 1.89 v 3.3 v 3.14 v 3.30 v 3.47 v 5 v 4.75 v 5.00 v 5.25 v table 8-5. measured i cc (desktop only) voltage rail voltage (v) s0 iccmax current integrated graphics 5 (a) s0 iccmax current external graphics 5 (a) s0 idle current integrated graphics 4,5 (a) s0 idle current external graphics 5 (a) sx iccmax current 5 (a) sx idle current (a) g3 v_proc_io 1.05 / 1.0 0.001 0.001 0.001 0.001 0 0 ? v5ref 5 0.001 0.001 0.001 0.001 0 0 ? v5ref_sus 5 0.001 0.001 0.001 0.001 0.001 0.001 ? vcc3_3 3.3 0.267 0.267 0.047 0.047 0 0 ? vccadac 3 3.3 0.068 0.001 0.001 0.001 0 0 ? vccadplla 1.05 0.08 0.02 0.065 0.005 0 0 ? vccadpllb 1.05 0.08 0.02 0.01 0.01 0 0 ? vcccore 1.05 2.1 1.94 0.6 0.42 0 0 ? vccdmi 1.05 0.057 0.057 0.002 0.002 0 0 ? vccio 3 1.05 4.35 3.69 0.86 0.53 0 0 ? vccasw 1.05 1.31 1.31 0.353 0.353 0.703 0.350 ? vccspi 3.3 0.02 0.02 0.001 0.001 0.015 0.001 ? vccdsw3_3 3.3 0.002 0.002 0.001 0.001 0.002 0.001 ? vccdfterm 1.8 0.002 0.002 0.001 0.001 0 0 ? vccrtc 3.3 n/a n/a n/a n/a n/a n/a 6 a see notes 1, 2 vccsus3_3 3.3 0.097 0.097 0.009 0.009 0.142 0.033 ? vccsushda 3.3 0.01 0.01 0.001 0.001 0.001 0.001 ? vccvrm 1.8 0.175 0.135 0.129 0.089 0 0 ? vccclkdmi 1.05 0.08 0.08 0.08 0.08 0 0 ? vccssc 1.05 0.105 0.105 0.03 0.03 0 0 ? vccdiffclkn 1.05 0.055 0.055 0.05 0.05 0 0 ?
electrical characteristics 316 datasheet 2. icc (rtc) data is taken with vccrtc at 3.0 v while the system in a mechanical off (g3) state at room temperature. 3. numbers based on a worst-case of 3 displays - 2 disp layport and 1 crt, even though only 2 display pipes are enabled at any one time. if no crt is used, vccadac contribution can be ignored. 4. s0 idle is based on 1 displayport panel used on display pipe a. 5. s0 iccmax measurements taken at 110 c and s0 idle/sx iccmax measurements taken at 50 c. table 8-6. measured i cc (mobile only) (sheet 1 of 2) voltage rail voltage (v) s0 iccmax current integrated graphics 5 (a) s0 iccmax current external graphics 5 (a) s0 idle current integrated graphics 4,5 (a) s0 idle current external graphics 5 (a) sx iccmax current 5 (a) sx idle current (a) g3 v_proc_io 1.05 / 1.0 0.001 0.001 0.001 0.001 0 0 ? v5ref 5 0.001 0.001 0.001 0.001 0 0 ? v5ref_sus 5 0.001 0.001 0.001 0.001 0.001 0.001 ? vcc3_3 3.3 0.228 0.228 0.035 0.035 0 0 ? vccadac3 3.3 0.001 0.001 0.001 0.001 0 0 ? vccadplla 1.05 0.075 0.01 0.07 0.005 0 0 ? vccadpllb 1.05 0.075 0.01 0.01 0.005 0 0 ? vcccore (internal suspend vr mode using intvrmen) 1.05 1.3 1.14 0.36 0.28 0 0 ? vcccore (external suspend vr mode using intvrmen) 1.05 1.2 1.04 0.31 0.23 0 0 ? vccdmi 1.05 / 1.0 0.042 0.042 0.001 0.001 0 0 ? vccio3 1.05 3.709 3.187 0.458 0.319 0 0 ? vccasw 1.05 0.903 0.903 0.203 0.203 0.603 0.23 ? vccspi 3.3 0.01 0.01 0.001 0.001 0.01 0.01 vccdsw3_3 3.3 0.001 0.001 0.001 0.001 0.003 0.001 ? vccdfterm 1.8 0.002 0.002 0.001 0.001 0 0 ? vccrtc 3.3 n/a n/a n/a n/a n/a n/a 6 ua see notes 1, 2 vccsus3_3 (internal suspend vr mode using intvrmen) 3.3 0.065 0.065 0.009 0.009 0.119 0.031 ?
datasheet 317 electrical characteristics notes: 1. g3 state shown to provide an estimate of battery life 2. icc (rtc) data is taken with vccrtc at 3.0 v while the system in a mechanical off (g3) state at room temperature. 3. numbers based on 2 display configuration - 1 external displayport and 1 lvds display. if vga is used, vccadac s0 iccmax in integrated graphics co ntribution is 63 ma. 4. s0 idle is based on 1 lvds display used on display pipe a. 5. s0 iccmax measurements taken at 110c and s0 idle/sx ic cmax measurements taken at 50c. 6. this applies to external suspend vr powered mode for dcpsus. in internal suspend vr mode, dcpsus is a no connect and hence iccmax is not applicable. 7. sx idle current measurem ent is based on sx/m3 and assumes vccasw is powered vccsus3_3 (external suspend vr mode using intvrmen) 3.3 0.065 0.065 0.005 0.005 0.059 0.014 ? vccsushda 3.3 0.01 0.01 0.001 0.001 0.001 0.001 ? vccvrm 1.5 0.167 0.127 0.124 0.075 0 0 ? vccclkdmi 1.05 0.075 0.075 0.065 0.065 0 0 vccssc 1.05 0.095 0.095 0.095 0.095 0 0 vccdiffclkn 1.05 0.055 0.055 0.05 0.05 0 0 vccalvds 3.3 0.001 0.001 0.001 0.001 0 0 vcctx_lvds 3 1.8 0.04 0.001 0.04 0.001 0 0 dcpsus (external suspend vr mode using intvrmen) 6 1.05 0.1 0.1 0.05 0.05 0.06 0.017 table 8-6. measured i cc (mobile only) (sheet 2 of 2) voltage rail voltage (v) s0 iccmax current integrated graphics 5 (a) s0 iccmax current external graphics 5 (a) s0 idle current integrated graphics 4,5 (a) s0 idle current external graphics 5 (a) sx iccmax current 5 (a) sx idle current (a) g3
electrical characteristics 318 datasheet table 8-7. dc characteristic input signal association (sheet 1 of 2) symbol associated signals vih1/vil1 (5v tolerant) pci signals (desktop only): ad[31:0], c/be[3:0]#, devsel#, frame#, irdy#, par, perr#, ploc k#, req[3:0]#, serr#, stop#, trdy# interrupt signals: pirq[d:a]#, pirq[h:e]# gpio signals: gpio[54, 52, 50, 5:2] vih2/vil2 digital display port hot plug detect: ddpb_hpd, ddpc_hpd, ddpd_hpd vih3/vil3 power management signals: pwrbtn#, ri#, sys_reset#, wake#, susack# mobile only: ac_present, clkrun# gpio signals: gpio[71:61, 57, 48, 39, 38, 34, 31:29, 24, 22, 17, 7, 6, 1] desktop only: gpio32 thermal/fan control signals: tach[7:0] (server/workstation only) vih4/vil4 clock signals: clkin_pciloopback, pcieclkrq[7:6]#, pcieclkrq[2], pcieclkrq[5] mobile only: peg_a_clkrq#, pe g_b_clkrq#, pcieclkrq[1:0], pcieclkrq[4:3] processor signals: a20gate pci signals: pme# interrupt signals: serirq power management signals: bmbusy# mobile only: batlow# sata signals: sata[5:0]gp spi signals: spi_miso strap signals: spkr, gnt[3:1]#, (str ap purposes only) lpc/firmware hub signals: lad[3:0]/fwh[3:0], ldrq0#, ldrq1#, gpio signals: gpio[73, 72, 59, 56, 55, 53, 51, 49, 47:40, 37:35, 33, 28:25, 23, 21:18, 16:14, 10:8, 0] desktop only: gpio12 usb signals: oc[7:0]# vih5/vil5 smbus signals: smbclk, smbdata, smbalert# system management signals: sml[1:0]clk(1), sml[1:0]data(1) gpio signals: gpio[75, 74, 60, 58, 11] vih6/vil6 jtag signals: jtag_tdi, jtag_tms, jtag_tck vih7/vil7 processor signals: thrmtrip# vimin8gen1/ vimax8gen1, vimin8gen2/ vimax8gen2 pci express* data rx signals: per[p,n][8:1] (2.5 gt/s and 5.0 gt/s) vih9/vil9 real time cl ock signals: rtcx1 vimin10 -gen1i/ vimax10-gen1i sata signals: sata[5:0]rx[p,n] (1.5 gb/s internal sata) vimin10 -gen1m/ vimax10-gen1m sata signals: sata[5:0]rx[p,n] (1.5 gb/s external sata) vimin10 -gen2i/ vimax10-gen2i sata signals: sata[5:0]rx[p,n] (3.0 gb/s internal sata) vimin10 -gen2m/ vimax10-gen2m sata signals: sata[5:0]rx[p,n] (3.0 gb/s external sata)
datasheet 319 electrical characteristics notes: 1. v di = | usbpx[p] ? usbpx[n] 2. includes vdi range 3. applies to low-speed/high-speed usb 4. pci express mvdiff p-p = 2*|petp[x] ? petn[x]| 5. sata vdiff, rx (vimax10/min10) is measured at the sata connector on the receiver side (generally, the motherboard connector), where sata mvdiff p-p = 2*|sata[x]rxp ? sata[x]rxn| 6. vccrtc is the voltage applied to the vccrtc well of the pch. when the system is in a g3 state, this is generally supplied by the coin ce ll battery, but for s5 and greater, this is generally vccsus3_3. 7. cl_vref = 0.12*(vccsus3_3) 8. this is an ac characteri stic that represents transi ent values for these signals. 9. applies to high-speed usb 2.0. vih11/vil11 intel high definition audio signals: hda_sdin[3:0] (3.3v mode) strap signals: hda_sdo, hda_sync (strap purposes only) gpio signals : gpio13 note: see vil_hda/vih_hda for high definition audio low voltage mode vih12 (absolute maximum) / vil12 (absolute minimum) / vclk_in_cross(abs) clock signals: clkin_dmi_[p,n], clkin_dot96[p,n], clkin_sata_[p,n]] vih13/vil13 miscellaneous signals: rtcrst# vih14/vil14 power management signals: pwrok, rsmrst#, dpwrok system management signals: intruder# miscellaneous signals: intvrmen, srtcrst# vih15/vil15 digital display control signals: crt_ddc_clk, crt_ddc_data sdvo_ctrlclk, sdvo_ctrldata, ddpc_ctrlclk, ddpc_ctrldata, ddpd_ctrlclk, ddpd_ctrldata mobile only: l_bklten, l_bkltctl, l_ddc_clk, l_ddc_data vih16/vil16 processor interface: rcin# power management signals: sys_pwrok, apwrok vih_cl/vil_cl controller link: cl_clk1, cl_data1 vdi / vcm / vse (5v tolerant) usb signals: usbp[13:0][p,n] (low-speed and full-speed) v hssq / v hsdsc / v hscm (5v tolerant) usb signals: usbp[13:0][p,n] (in high-speed mode) vih_hda / vil_hda intel ? high definition audio signals: hda_sdin[3:0] strap signals: hda_sdo, hda_sync (strap purposes only) note: only applies when running in low voltage mode (1.5 v) vih_sst/vil_sst sst (server/workstation only) vih_fdi/vil_fdi intel ? flexible display interface signals: fdi_rx[p,n][7:0] vaux-diff-p-p digital display port aux si gnal (receiving side): ddp[d:b]_aux[p,n] vih_xtal25/ vil_xtal25 25mhz crystal input xtal25_in vimin17-gen3i/ vimax17-gen3i sata signals: sata[5:0]rx[p,n] (6.0 gb/s internal sata) table 8-7. dc characteri stic input signal association (sheet 2 of 2) symbol associated signals
electrical characteristics 320 datasheet table 8-8. dc input charac teristics (she et 1 of 3) symbol parameter min max unit notes vil1 input low voltage ?0.5 0.3 3.3 v v 10 vih1 input high voltage 0.5 3.3 v v5ref + 0.5 v 10 vil2 input low voltage ? .8 v vih2 input high voltage 2 ? v vil3 input low voltage ?0.5 0.8 v vih3 input high voltage 2.0 3.3 v + 0.5 v 10 vil4 input low voltage ?0.5 0.3 3.3 v v 10 vih4 input high voltage 0.5 3.3 v 3.3 v + 0.5 v 10 vil5 input low voltage 0 0.8 v vih5 input high voltage 2.1 3.3 v + 0.5 v 10 vil6 input low voltage -0.5 0.35 v 11 vih6 input high voltag e 0.75 1.05 v + 0.5 v 11 vil7 input low voltage 0 0.25 v_proc_io v vih7 input high voltage 0.75 v_proc_io v_proc_io v vimin8gen1 minimum input voltage 175 ? mvdiffp-p 4 vimax8gen1 maximum input voltage ? 1200 mvdiffp-p 4 vimin8gen2 minimum input voltage 100 ? mvdiffp-p 4 vimax8gen2 maximum input voltage ? 1200 mvdiffp-p 4 vil9 input low voltage ?0.5 0.10 v vih9 input high voltage 0.50 1.2 v vimin10- gen1i minimum input voltage - 1.5 gb/s internal sata 325 ? mvdiffp-p 5 vimax10- gen1i maximum input voltage - 1.5 gb/s internal sata ? 600 mvdiffp-p 5 vimin10- gen1m minimum input voltage - 1.5 gb/s esata 240 ? mvdiffp-p 5 vimax10- gen1m maximum input voltage - 1.5 gb/s esata ? 600 mvdiffp-p 5 vimin10- gen2i minimum input voltage - 3.0 gb/s internal sata 275 ? mvdiffp-p 5 vimax10- gen2i maximum input voltage - 3.0 gb/s internal sata ? 750 mvdiffp-p 5 vimin10- gen2m minimum input voltage - 3.0 gb/s esata 240 ? mvdiffp-p 5 vimax10- gen2m maximum input voltage - 3.0 gb/s esata ? 750 mvdiffp-p 5 vil11 input low voltage 0 0.35 3.3 v v 10 vih11 input high voltage 0.65 3.3 v 3.3 + 0.5v v 10 vil12 (absolute minimum) input low voltage -0.3 ? v
datasheet 321 electrical characteristics vih12 (absolute maximum) input high voltage ? 1.150 v vil13 input low voltage ? 0.5 0.78 v vih13 input high voltage 2.3 vccrtc + 0.5 v 6 vil14 input low voltage ? 0.5 0.78 v vih14 input high voltage 2.0 vccrtc + 0.5 v 6 vil15 input low voltage ? 0.5 0.3 3.3 v v 10 vih15 input high voltage 0.7 3.3 v 3.3 v + 0.5 v 10 vil16 input low voltage ? 0.5 0.8 v 10 vih16 input high voltage 2.1 3.3 v + 0.5 v 10 vil_cl input low voltage ? 0.3 cl_vref - 0.075 v 7 vih_cl input high voltage cl_vref + 0.075 1.2 v 7 vclk_in_cross (abs) absolute crossing point 0.250 0.550 v vdi differential input sensitivity 0.2 ? v 1,3 vcm differential common mode range 0.8 2.5 v 2,3 vse single-ended receiver threshold 0.8 2.0 v 3 vhssq hs squelch detection threshold 100 150 mv 9 vhsdsc hs disconnect detection threshold 525 625 mv 9 vhscm hs data signaling common mode voltage range ?50 500 mv 9 vil_hda input low voltage 0 0.4 vcc_hda v vih_hda input high volt age 0.6 vcc_hda 1.5 v vil_sst (server/ workstation only) input low voltage -0.3 0.4 v vih_sst (server/ workstation only) input high voltage 1.1 1.5 v vil_peci input low voltage -0.15 0.275 v_proc_io v vih_peci input high voltage 0.725 v_proc_io v_proc_io + 0.15 v vil_fdi minimum input voltage 175 ? mvdiffp-p vih_fdi maximum input voltage ? 1000 mvdiffp-p table 8-8. dc input charac teristics (sheet 2 of 3) symbol parameter min max unit notes
electrical characteristics 322 datasheet notes: 1. v di = | usbpx[p] ? usbpx[n] 2. includes vdi range 3. applies to low-speed/full-speed usb 4. pci express mvdiff p-p = 2*|petp[x] ? petn[x]| 5. sata vdiff, rx (vimax10/min10) is measured at the sata connector on the receiver side (generally, the motherboard connector), where sata mv diff p-p = 2*|sata[x]rxp ? sata[x]rxn|. 6. vccrtc is the voltage applied to the vccrtc well of the pch. when the system is in a g3 state, this is generally supplied by the coin cell battery, but for s5 and greater, this is generally vccsus3_3. 7. cl_vref = 0.12*(vccsus3_3). 8. this is an ac characteri stic that represents transient values for these signals. 9. applies to high-speed usb 2.0. 10. 3.3 v refers to vccsus3_3 for si gnals in the suspend well, vcc3_3 for signals in the core well and to vccdsw3_3 for signals in the dsw well. see ta b l e 3 - 2 , or ta b l e 3 - 3 for signal and power well association. 11. 1.05 v refers to vccio or vcccore fo r signals in the core well and to vc casw for signals in the me well. see ta b l e 3 - 2 or ta b l e 3 - 3 for signal and power well association. 12. vpk-pk min for xtal25 = 500 mv. vaux-diff-p-p digital display port auxiliary signal peak-to-peak voltage at receiving device 0.32 1.36 vdiffp-p vil_xtal25 minimum input voltage -0.25 0.15 v 12 vih_xtal25 maximum input voltage 0.7 1.2 v 12 vimin17- gen3i minimum input voltage - 6.0 gb/s internal sata 240 ? mvdiffp-p 5 vimax17- gen3i maximum input voltage - 6.0 gb/s internal sata ? 1000 mvdiffp-p 5 table 8-8. dc input charac teristics (she et 3 of 3) symbol parameter min max unit notes
datasheet 323 electrical characteristics table 8-9. dc characteristic output signal assoc iation (sheet 1 of 2) symbol associated signals voh1/vol1 processor signal: pmsynch, procpwrgd voh2/vol2 lpc/firmware hub signals: lad[3:0]/fwh[3:0], lframe#/fwh[4], init3_3v# power management signal: lan_phy_pwr_ctrl intel ? high definition audio signals: hda_dock_en# (mobile only), hda_dock_rst# (mobile only) pci signals: ad[31:0], c/be[3:0], devse l#, frame#, irdy#, par, pcirst#, gnt[3:0]#, pme#(1) interrupt signals: pirq[d:a], pirq[h:e]#(1) gpio signals: gpio[73, 72, 59, 56, 55:50, 49, 47:40, 37:35, 33, 28:25, 23, 21:18, 16:12, 10:8, 5:2, 0] spi signals: spi_cs0#, spi_cs1#, spi_mosi, spi_clk miscellaneou s signals: spkr voh3/vol3 smbus signals: smbclk(1), smbdata(1) system management signals: sml[1:0]clk(1), sml[1:0]data(1), sml0alert#, sml1alert# gpio signals: gpio[75, 74, 60, 58, 11] voh4/vol4 power management signals: slp_s3#, slp_s4#, slp_s5#, slp_a#, slp_lan#, susclk, sus_stat#, su spwrdnack, slp_sus#, stp_pci# mobile only: clkrun# sata signals: sataled#, sclock, sload, sdataout0, sdataout1 gpio signals: gpio[71:68, 63:61, 57, 48, 39, 38, 34, 31, 30, 29, 24, 22, 17, 7, 6, 1] desktop only: gpio32 controller link: cl_rst1# interrupt signals: serirq voh5/vol5 usb signals: usbp[13:0][p,n] in low-speed and full-speed modes vol6/vol6 (fast mode) digital display control signals: crt_ddc_clk, crt_ddc_data sdvo_ctrlclk, sdvo_ctrldata, ddpc_ctrlclk, ddpc_ctrldata, ddpd_ctrlclk, ddpd_ctrldata mobile only: l_ctrl_clk, l_ct rl_data, l_vdd_en, l_bklten, l_bkltctl, l_ddc_clk, l_ddc_data, note: fast mode is not applicable to l_vdd_en voh6 l_vdd_en, l_bklten, l_bkltctl vomin7 -gen1i,m/ vomax7-gen1i,m sata signals: sata[5:0]rx[p,n] (1.5 gb/s internal and external sata) vomin7 -gen2i,m/ vomax7-gen2i,m sata signals: sata[5:0]rx[p,n] (3.0 gb/s internal and external sata) vomin8/vomax8 digital display ports when configured as hdmi/dvi: ddpb_[3:0][p,n], ddpc_[3:0][p,n], ddpd_[3:0][p,n] sdvo signals: sdvo_int[p,n ], sdvo_tvclkin[p,n], sdvo_stall[p,n] voh9/vol9 power management signal: pltrst#
electrical characteristics 324 datasheet note: 1. these signals are open-drain. vhsoi vhsoh vhsol vchirpj vchirpk usb signals: usbp[13:0][p:n] in high-speed mode voh_hda/ vol_hda intel ? high definition audio signals: hda_rst#, hda_sdo, hda_sync vol_jtag jtag signals: jtag_tdo voh_pciclk/ vol_pciclk single ended clock interface output signals: clkout_pci[4:0], clkoutflex[3:0] gpio signals: [67:64] vol_sgpio sgpio signals: sclock, sload, sdataout0, sdataout1 voh_pwm/ vol_pwm thermal and fan control signals: pwm[3:0] (server/workstation only) voh_crt/vol_crt display signals: crt_hsync, crt_vsync voh_cl1/vol_cl1 controller link signals: cl_clk1, cl_data1 voh_sst/vol_sst (server/workstation only) sst signal: sst vaux-diff-p-p digital display port aux signal (transmit side): ddp[d:b]_aux[p,n] voh_fdi//vol_fdi intel ? fdi signals: fdi_fsync_[1:0],fdi_lsync_[1:0],fdi_int vomin10 -gen3i/ vomax10-gen3i sata signals: sata[5:0]rx[p,n] (6.0 gb/s internal sata) v omin11- pciegen12 v omax11- pciegen12 pci express* data tx signals: pet[p,n][8:1] (gen1 and gen2) table 8-9. dc characteristic output signal association (sheet 2 of 2) symbol associated signals
datasheet 325 electrical characteristics table 8-10. dc output charac teristics (sheet 1 of 2) symbol parameter min max unit i ol / i oh notes v ol1 output low voltage 0 0.255 v 3 ma v oh1 output high voltage v_proc_io - 0.3 v_proc_io v -3 ma v ol2 output low voltage ? 0.1 3.3 v v 1.5 ma 7 v oh2 output high voltage 0.9 3.3 v 3.3 v -0.5 ma 7 v ol3 output low voltage 0 0.4 v 3 ma v oh3 output high voltage 3.3 v - 0.5 ? v 4 ma 1, 7 v ol4 output low voltage ? 0.4 v 6 ma v oh4 output high voltage 3.3 v - 0.5 3.3 v v -2 ma 7 v ol5 output low voltage ? 0.4 v 5 ma v oh5 output high voltage 3.3 v ? 0.5 ? v -2 ma 7 v ol6 output low voltage 0 400 mv 3 ma 2 v ol6 (fast mode) output low voltage 0 600 mv 6 ma 2 v oh6 output high voltage 3.3 v ? 0.5 3.3 v -2 ma 7, 2 v omin7- gen1i,m minimum output voltage 400 ? mvdif fp-p 3 v omax7- gen1i,m maximum output voltage ? 600 mvdif fp-p 3 v omin7- gen2i,m minimum output voltage 400 ? mvdif fp-p 3 v omax7- gen2i,m maximum output voltage ? 700 mvdif fp-p 3 v omin8 output low voltage 400 ? mvdif fp-p v omax8 output high voltage ? 600 mvdif fp-p v ol9 output low voltage ? 0.1 3.3 v v 1.5 ma 7 v oh9 output high voltage 0.9 3.3 v 3.3 v -2.0 ma 7 vhsoi hs idle level ?10.0 10.0 mv vhsoh hs data signaling high 360 440 mv vhsol hs data signaling low ?10.0 10.0 mv vchirpj chirp j level 700 1100 mv vchirpk chi r p k level ?900 ?500 mv vol_hda output low voltage ? 0.1 vccsushda v 1.5 ma voh_hda output high voltage 0.9 vccsushda ? v -0.5 ma vol_pwm (server/ workstation only) output low voltage ? 0.4 v 8 ma voh_pwm (server/ workstation only) output high voltage ? ? 1 vol_sgpio output low voltage ? 0.4 v
electrical characteristics 326 datasheet notes: 1. the serr#, pirq[h:a], smbdata, smbclk, sm l[1:0]clk, sml[1:0]data, sml[1:0]alert# and pwm[3:0] signals has an open-dra in driver and sataled# has an open-collector driver, and the v oh specification does not apply. this signal must have external pull-up resistor. 2. pci express mvdiff p-p = 2*|petp[x] ? petn[x]| 3. sata vdiff, tx (v omin7 /v omax7 ) is measured at the sata connector on the transmit side (generally, the motherboard connector), where sata mv diff p-p = 2*|sata[x]txp ? sata[x]txn| vol_crt output low voltage ? 0.5 v 8 ma voh_crt output high voltage 2.4 ? v 8 ma vol_cl1 output low voltage ? 0.15 v 1 ma voh_cl1 output high voltage .61 .98 v vol_sst (server/ workstation only) output low voltage 0 0.3 v 0.5 ma voh_sst (server/ workstation only) output high voltage 1.1 1.5 v -6 ma vol_peci output low voltage ? 0.25 v_proc_io v 0.5 ma voh_peci output high voltage 0.75 v_proc_io v_proc_io -6 ma vol_hda output low voltag e ? 0.1 vcchda v 1.5 ma vol_jtag output low voltage 0 0.1 1.05 v v 1.5 ma v_clkout_swi ng differential output swing 300 ? mv v_clkout_cro ss clock cross-over point 300 550 mv v_clkoutmin min output voltage -0.3 ? v v_clkoutmax max output voltage 1.15 v v vol_pciclk output low voltage ? 0.4 v -1 ma voh_pciclk output high voltage 2.4 ? v 1 ma vaux-diff-p-p digital display port auxiliary signal peak-to- peak voltage at transmitting device 0.39 1.38 vdiffp -p vol_fdi output low voltage -.1 0.2 3.3 v v 4.1 ma 7 voh_fdi output high voltage 0.8 3.3 v 1.2 v 4.1 ma 7 v omin10- gen3i minimum output voltage 200 ? mvdif fp-p 3 v omax10- gen3i maximum output voltage ? 900 mvdif fp-p 3 v omin11- pciegen12 output low voltage 800 ? mvdif fp-p 2 v omax11- pciegen12 output high voltage ? 1200 mvdif fp-p 2 table 8-10. dc output charac teristics (sheet 2 of 2) symbol parameter min max unit i ol / i oh notes
datasheet 327 electrical characteristics 4. maximum iol for procpwrgd is 12ma for short du rations (<500 ms per 1.5 s) and 9 ma for long durations. 5. for init3_3v only, for low current devices, the following applies: v ol5 max is 0.15 v at an i ol5 of 2 ma. 6. 3.3 v refers to vccsus3_3 for signals in the suspen d well, to vcc3_3 for signals in the core well, to vccdsw3_3 for those signals in the deep s4/s5 well. see ta b l e 3 - 2 or ta b l e 3 - 3 for signal and power well association. 7. 3.3 v refers to vccsus3_3 for signals in the susp end well, to vcc3_3 for signals in the core well, vccdsw3_3 for signals in the deep s4/s5 well. see ta b l e 3 - 2 , or ta b l e 3 - 3 for signal and power well association. table 8-11. other dc charac teristics (sheet 1 of 2) symbol parameter min nom max unit notes v_proc_io processor i/f .95 1.0 1.05 v 1 v_proc_io processor i/f .998 1.05 1.10 v 1 v5ref pch core well reference voltage 4.75 5 5.25 v 1 vcc3_3 i/o buffer voltage 3.14 3.3 3.47 v 1 vccvrm internal pll and vrms (1.5v fo r mobile) 1.455 1.5 1.545 v 1, 3 vccvrm 1.8 v internal pll and vrms (1.8 v for desktop) 1.746 1.8 1.854 v 1, 3 v5ref_sus suspend well referenc e voltage 4.75 5 5.25 v 1 vccsus3_3 suspend well i/o buffer voltage 3.14 3.3 3.47 v 1 vcccore internal logic voltage .998 1.05 1.10 v 1 vccio core well i/o buffers .998 1.05 1.10 v 1 vccdmi dmi buffer voltage .95 1.0 1.05 v 1 vccdmi dmi buffer voltage .998 1.05 1.10 v 1 vccclkdmi dmi clock buffer voltage .998 1.05 1.10 1 vccspi 3.3 v supply for spi controller logic 3.14 3.3 3.47 v 1 vccasw 1.05 v supply for intel ? management engine and integrated lan .998 1.05 1.10 v 1 vccrtc (g3-s0) battery voltage 2 ? 3.47 v 1 vccsushda high definition audio controller suspend voltage 3.14 3.3 3.47 v 1 vccsushda (low voltage) high definition audio controller low voltage mode suspend voltage 1.43 1.5 1.58 v 1 vccadplla display pll a power .998 1.05 1.10 1 vccadpllb display pll b power .998 1.05 1.10 1 vccadac display dac analog power. this power is supplied by the core well. 3.14 3.3 3.47 1 vccalvds analog power supply for lvds (mobile only) 3.14 3.3 3.47 1 vcctx_lvds i/o power supply for lv ds. (mobile only) 1.71 1.8 1.89 vccssc spread modulators power supply .998 1.05 1.10 v 1 vccdiffclkn differential clock buffers power supply .998 1.05 1.10 v 1 vccdfterm 1.8v power supply for df_tvs 1.71 1.8 1.89 v 1 vccaclk analog power supply for in ternal pll .998 1.05 1.10 v 1
electrical characteristics 328 datasheet notes: 1. the i/o buffer supply voltage is measured at the pch package pins. the tolerances shown in ta b l e 8 - 1 1 are inclusive of all noise from dc up to 20 mhz. in testing, the voltage rails should be measured with a bandwidth limited oscilloscope that has a rolloff of 3 db/decade above 20 mhz. 2. includes single ended clocks refc lk14in, clkoutflex[3:0] and pciclkin. 3. includes only dc tolerance. ac tolerance will be 2% in addition to this range. 8.5 display dc characteristics vccapllexp analog power supply for dmi pll .998 1.05 1.10 v 1 vccfdipll analog power supply for fdi pll .998 1.05 1.10 v 1 vccdsw3_3 3.3 v supply for de ep s4/s5 wells 3.14 3.3 3.47 1 i li1 pci_3v hi-z state data line leakage ?10 ? 10 a (0 v < vin < vcc3_3) i li2 pci_5v hi-z state data line leakage ?70 ? 70 a max v in = 2.7 v min v in = 0.5 v i li3 input leakage current ? all other ?10 ? 10 a 2 c in input capacitance ? all other ? ? tbd pf f c = 1 mhz c out output capacitance ? ? tbd pf f c = 1 mhz c i/o i/o capacitance ? ? 10 pf f c = 1 mhz typical value c l xtal25_in 3 pf c l rtcx1 6 pf table 8-12. signal groups signal group associated signals note lvds lvdsa_data[3:0], lvdsa_data#[3:0], lvdsa_clk, lvdsa_clk#, lvdsb_data[3:0], lvdsb_data#[3:0], lvdsb_clk, lvdsb_clk# crt dac crt_red, crt_green, crt_bl ue, crt_irtn, crt_tvo_iref digital displayport auxilliary ddp[d:b]_aux[p,n] table 8-13. crt dac signal group dc char acteristics: functional operating range (vccadac = 3.3 v 5%) (sheet 1 of 2) parameter min nom max unit notes dac resolution ?8?bits 1 max luminance (full-scale) 0.665 0.7 0.77 v 1, 2, 4 white video level voltage min luminance ?0?v 1, 3, 4 black video level voltage lsb current ?73.2?ua 4, 5 integral linearity (inl) -1 ? 1 lsb 1, 6 table 8-11. other dc characteristics (sheet 2 of 2) symbol parameter min nom max unit notes
datasheet 329 electrical characteristics notes: 1. measured at each r, g, b te rmination according to the vesa test procedure ? evaluation of analog display graphics subsystems proposal (version 1, draft 4, december 1, 2000). 2. max steady-state amplitude 3. min steady-state amplitude 4. defined for a double 75- ? termination. 5. set by external refe rence resistor value. 6. inl and dnl measured and ca lculated according to vesa video signal standards. 7. max full-scale voltage difference among r,g, b outputs (percentage of steady-state full- scale voltage). differential linearity (dnl) -1 ? 1 lsb 1, 6 video channel-chan nel voltage ampli- tude mismatch ?? 6% 7 monotonicity yes table 8-13. crt dac signal group dc char acteristics: function al operating range (vccadac = 3.3 v 5%) (sheet 2 of 2) parameter min nom max unit notes table 8-14. lvds interface: functional operating ra nge (vccalvds = 1.8 v 5%) symbol parameter min nom max unit vod differential output voltage 250 350 450 mv ? vod change in vod between complementary output states ?? 50mv vos offset voltage 1.125 1.25 1.375 v ? vos change in vos between complementary output states ?? 50mv ios output short circuit current ?-3.5-10ma ioz output tri-state current ? 1 10 a vcm(ac) ac common mode noise 150 mv table 8-15. display port auxiliary signal group dc characteristics symbol parameter min nom max unit vaux-diff-p-p aux peak-to-peak voltage at a transmit- ting devices 0.39 ? 1.38 v aux peak-to-peak volt age at a receiving devices 0.32 ? 1.36 v vaux-term-r aux ch termination dc resistance ?100 ? ? v-aux-dc-cm aux dc common mode voltage 0? 2v v-aux_turn-cm aux turn around common mode voltage ?0.4 v
electrical characteristics 330 datasheet 8.6 ac characteristics notes: 1. specified at the measurement point into a ti ming and voltage compliance test load and measured over any 250 consecutive tx uis. (a lso refer to the transm itter compliance eye diagram) 2. a t tx-eye = 0.70 ui provides for a total sum of deterministic and rand om jitter budget of t txjitter-max = 0.30 ui for the transmit ter collected over any 250 consecutive tx uis. the t txeye-median-to-max-jitter specification ensures a jitter di stribution in which the median and the maximum deviation from the median is le ss than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately eq ual as opposed to the averaged time value. 3. specified at the measurement point and measured over any 250 consecutive uis. the test load documented in the pci express* specification 2.0 should be used as the rx device when taking measurements (als o refer to the receiver compliance eye diagram). if the clocks to the rx and tx are not derived fr om the same referenc e clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 4. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the t rx- eye-median-to--max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less th an half of the total 0.6 ui jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is appr oximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived fr om the same referenc e clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 5. nominal unit interval is 400 ps for 2.5 gt/s and 200 ps for 5 gt/s. table 8-16. pci express* interface timings symbol parameter min max unit figures notes transmitter and re ceiver timings ui unit interval ? pci express* gen 1 (2.5 gt/s) 399.88 400.12 ps 5 ui unit interval ? pci express* gen 2 (5.0 gt/s) 199.9 200.1 ps 5 t tx-eye minimum transmission eye width 0.7 ? ui 8-28 1,2 t tx-rise/fall (gen1) d+/d- tx out put rise/fall time ?0.125 ui 1,2 t tx-rise/fall (gen2) d+/d- tx out put rise/fall time ?0.15 ui 1,2 t rx-eye minimum receiver eye width 0.40 ? ui 8-29 3,4
datasheet 331 electrical characteristics notes: 1. specified at the measurement point into a ti ming and voltage compli ance test load and measured over any 250 consecutive tx uis. (a lso refer to the transm itter compliance eye diagram) 2. a t tx-eye = 0.70 ui provides for a total sum of de terministic and random jitter budget of t txjitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the t txeye-median-to-max-jitter specification ensures a jitter di stribution in which the median and the maximum deviation from the median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter me dian describes the point in ti me where the number of jitter points on either side is a pproximately equal as opposed to the averaged time value. notes: 1. specified at the measurement point into a ti ming and voltage compli ance test load and measured over any 250 consecutive tx uis. (a lso refer to the transm itter compliance eye diagram) 2. a t tx-eye = 0.70 ui provides for a total sum of de terministic and random jitter budget of t txjitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the t txeye-median-to-max-jitter specification ensures a jitter di stribution in which the median and the maximum deviation from the median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter me dian describes the point in ti me where the number of jitter points on either side is a pproximately equal as opposed to the averaged time value. table 8-17. hdmi interface timings (ddp[d:b][3:0])timings symbol parameter min max unit figures notes transmitter and re ceiver timings ui unit interval 600 4000 ps t tx-eye minimum transmission eye width 0.8 ? ui 1,2 t tx-rise/fall d+/d- tx out put rise/fall time ?0.125ui 1,2 tmds clock jitter ?0.25ui t-skew- intra-pair intra pair skew at source connector ?0.15t bit t-skew- inter-pair inter pair skew at source connector ?0.2 tc h a r acter duty cycle clock duty cycle 10 60% % table 8-18. sdvo interface timings symbol parameter min max unit figures notes transmitter and receiver timings ui unit interval 369.89 1000 ps 5 t tx-eye minimum transmission eye width 0.7 ? ui 8-28 1,2 t tx-rise/fall d+/d- tx out put rise/ fall time ? 0.125 ui 1,2 t rx-eye minimum receiver eye width 0.40 ? ui 8-29 3,4
electrical characteristics 332 datasheet 3. specified at the measurement point and measured over any 250 consecutive uis. the test load documented in the pci express* specification 2.0 should be used as the rx device when taking measurements (als o refer to the receiver compliance eye diagram). if the clocks to the rx and tx are not derived fr om the same referenc e clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 4. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the t rx- eye-median-to--max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less th an half of the total 0.6 ui jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is appr oximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived fr om the same referenc e clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 5. nominal unit interval for highest sdvo sp eed is 370 ps. howeve r, depending on the resolution on the interface, the ui may be more than 370 ps. table 8-19. displayport interf ace timings (ddp[d:b][3:0]) symbol p arameter min nom max unit ui_high_rate unit interval for high bit rate (2.7 gbps/lane) 370 ? ps ui_low_rate unit interval for reduced bit rate (1.62 gbps/lane) 617 ? ps down_spread_ amplitude link clock down spreading 0 ? 0.5 % down_spread_ frequency link clock down-spreading frequency 30 ? 33 khz ltx-skew- intrapair lane intra-pair output skew at tx package pins ?20ps ttx-rise/ fall_mismatch_ chipdiff lane intra-pair rise/fall time mismatch at tx package pin 5%? v tx-diffp-p-level1 differential peak-to-peak output voltage level 1 0.34 0.4 0.46 v v tx-diffp-p-level2 differential peak-to-peak output voltage level 2 0.51 0.6 0.68 v v tx-diffp-p-level3 differential peak-to-peak output voltage level 3 0.69 0.8 0.92 v v tx-preemp_ratio no pre-emphasis 0 0 0 db v tx-preemp_ratio 3.5 db pre-emphasis level 2.8 3.5 4.2 db v tx-preemp_ratio 6.0 db pre-emphasis level 4.8 6 7.2 db l tx-skew- inter_pair lane-to-lane output skew at tx package pins ??2ui
datasheet 333 electrical characteristics note: 1. measurement point for rise and fall time: v il (min)? v il (max) 2. cb = total capacitance of one bus line in pf. if mixed with high-speed mode devices, faster fall times according to high-speed mode t r /t f are allowed. table 8-20. displayport aux interface symbol p arameter min nom max unit ui aux unit interval 0.4 0.5 0.6 s t- aux_bus_park aux ch bus park time 10 ? ? ns tcycle-to-cycle jitter maximum allowable ui variation within a single transaction at the connector pins of a transmitting device 0.04 ui ? maximum allowable ui variation within a single transaction at the connector pins of a receiving device 0.05 ui ? table 8-21. ddc characteristics ddc signals: crt_ddc_clk, crt_ddc_data, l_ddc_ clk, l_ddc_data, sdvo_ctrlclk, sdvo_ctrldata, ddp[d:c]_ctrlclk, ddp[d:c]_ctrldata symbol parameter standard mode fast mode 1 mhz units max min max min max f scl operating frequency 100 ? 400 ? 1000 khz t r rise time 1 ???? n s t f fall time 1 250 20+0.1cb 2 250 ? 120 ns
electrical characteristics 334 datasheet table 8-22. lvds interface ac characterist ics at various frequencies (sheet 1 of 2) symbol parameter min nom max unit figures notes llht lvds low-to-high tran sit ion tim e 0.25 0.5 0.75 ns 8-26 1, across receiver termination lhlt lvds high-to-low tran sit ion tim e 0.25 0.5 0.75 ns 1, across receiver termination frequency = 40-mhz tppos0 transmitter output pulse for bit 0 -0.25 0 0.25 ns 8-27 tppos1 transmitter output pulse for bit 1 3.32 3.57 3.82 ns tppos2 transmitter output pulse for bit 2 6.89 7.14 7.39 ns tppos3 transmitter output pulse for bit 3 10.46 10.71 10.96 ns tppos4 transmitter output pulse for bit 4 14.04 14.29 14.54 ns tppos5 transmitter output pulse for bit 5 17.61 17.86 18.11 ns tppos6 transmitter output pulse for bit 6 21.18 21.43 21.68 ns tjcc transmitter jitter cycle-to-cycle ? 350 370 ps frequency = 65-mhz tppos0 transmitter output pulse for bit 0 -0.20 0 0.20 ns 8-27 tppos1 transmitter output pulse for bit 1 2.00 2.20 2.40 ns tppos2 transmitter output pulse for bit 2 4.20 4.40 4.60 ns tppos3 transmitter output pulse for bit 3 6.39 6.59 6.79 ns tppos4 transmitter output pulse for bit 4 8.59 8.79 8.99 ns tppos5 transmitter output pulse for bit 5 10.79 10.99 11.19 ns tppos6 transmitter output pulse for bit 6 12.99 13.19 13.39 ns tjcc transmitter jitter cycle-to-cycle ? ? 250 ps
datasheet 335 electrical characteristics frequency = 85Cmhz tppos0 transmitter output pulse for bit 0 -0.20 0 0.20 ns 8-27 tppos1 transmitter output pulse for bit 1 1.48 1.68 1.88 ns tppos2 transmitter output pulse for bit 2 3.16 3.36 3.56 ns tppos3 transmitter output pulse for bit 3 4.84 5.04 5.24 ns tppos4 transmitter output pulse for bit 4 6.52 6.72 6.92 ns tppos5 transmitter output pulse for bit 5 8.20 8.40 8.60 ns tppos6 transmitter output pulse for bit 6 9.88 10.08 10.28 ns tjcc transmitter jitter cycle-to-cycle ??250ps frequency = 108Cmhz tppos0 transmitter output pulse for bit 0 -0.20 0 0.20 ns 8-27 tppos1 transmitter output pulse for bit 1 1.12 1.32 1.52 ns tppos2 transmitter output pulse for bit 2 2.46 2.66 2.86 ns tppos3 transmitter output pulse for bit 3 3.76 3.96 4.16 ns tppos4 transmitter output pulse for bit 4 5.09 5.29 5.49 ns tppos5 transmitter output pulse for bit 5 6.41 6.61 6.81 ns tppos6 transmitter output pulse for bit 6 7.74 7.94 8.14 ns tjcc transmitter jitter cycle-to-cycle ??250ps table 8-22. lvds interface ac characteristics at various frequencies (sheet 2 of 2) symbol parameter min nom max unit figures notes
electrical characteristics 336 datasheet notes: 1. measured at each r, g, b termination accordin g to the vesa test procedure ? evaluation of analog display graphics subsystems proposal (version 1, draft 4, december 1, 2000). 2. r, g, b max video rise/fall time: 50% of minimum pixel clock period. 3. r, g, b min video rise/fall time: 10% of minimum pixel clock period. 4. max settling time: 30% of minimum pixel clock period. 5. video channel-channel output skew: 25% of minimum pixel clock period. 6. overshoot/undershoot: 12% of black-white video level (full-scale) step function. 7. noise injection ratio: 2.5% of maximum luminance voltage (dc to max. pixel frequency). 8. r, g, b ac parameters are strongly dependent on the board implementation table 8-23. crt dac ac characteristics parameter min nom max units notes pixel clock frequency 400 mhz r, g, b video rise time 0.25 ? 1.25 ns 1, 2, 8 (10-90% of black-to- white transition, @ 400-mhz pixel clock) r, g, b video fall time 0.25 ? 1.25 ns 1, 3, 8 (90-10% of white-to- black transition, @ 400-mhz pixel clock) settling time 0.75 ns 1, 4, 8 @ 400-mhz pixel clock video channel-to- channel output skew 0.625 ns 1, 5, 8 @ 400-mhz pixel clock overshoot/ undershoot -0.084 ? +0.084 v 1, 6, 8 full-scale voltage step of 0.7 v noise injection ratio 2.5 % 1, 7, 8 table 8-24. clock timings (sheet 1 of 4) sym parameter min max unit notes figure pci clock (clkout_pci[4:0]) t1 period 29.566 30.584 ns 8-11 t2 high time 10.826 17.850 ns 8-11 t3 low time 10.426 17.651 ns 8-11 duty cycle 40 60 % t4 rising edge rate 1.0 4 v/ns 8-11 t5 falling edge rate 1.0 4 v/ns 8-11 jitter ? 500 ps 8 , 9 14.318 mhz flex clock t6 period 68.83 70.84 ns 8-11 t7 high time 29.55 39.00 ns 8-11 t8 low time 29.16 38.80 ns 8-11 duty cycle 40 60 % - rising edge rate 1.0 4 v/ns 5 - falling edge rate 1.0 4 v/ns 5 jitter (14.318 mhz configured on clkoutflex1 or clkoutflex3) ? 800 ps 8 , 9
datasheet 337 electrical characteristics jitter(14.318 mhz configured on clkoutflex0 or clkoutflex2) ? 1000 ps 8 , 9 48 mhz flex clock t9 period 20.32 21.34 ns 8-11 t10 high time 7.02 12.51 ns 8-11 t11 low time 6.63 12.30 ns 8-11 duty cycle 40 60 % - rising edge rate 1.0 4 v/ns 5 -falling edge rate 1.0 4 v/ns 5 jitter (48mhz configured on clkoutflex1 or clkoutflex3) ?410ps 8 , 9 jitter(48mhz configured on clkoutflex0 or clkoutflex2) ?510ps 8 , 9 24 mhz flex clock t12 period 41.16 42.18 ns 8-11 t13 high time 22.64 23.19 ns 8-11 t14 low time 18.52 18.98 ns 8-11 duty cycle 45 55 % - rising edge rate 1.0 4 v/ns 5 -falling edge rate 1.0 4 v/ns 5 jitter (24mhz configured on clkoutflex1 or clkoutflex3) ?330ps 8 , 9 jitter(24mhz configured on clkoutflex0 or clkoutflex2) ?510ps 8 , 9 27 mhz flex clock t15 period 36.4 37.67 ns 8-11 t16 high time 20.02 20.72 ns 8-11 t17 low time 16.38 16.95 ns 8-11 duty cycle 45 55 % - rising edge rate 1.0 4 v/ns 5 -falling edge rate 1.0 4 v/ns 5 jitter (27mhz configured on clkoutflex1 or clkoutflex3) ?450ps 8 , 9 jitter (27mhz configured on clkoutflex0 or clkoutflex2) ?630ps 8 , 9 clkout_dp_[p,n] period period ssc on 7.983 8.726 ns 8-30 period period ssc off 7.983 8.684 ns 8-30 dtycyc duty cycle 40 60 % 8-30 v _swing differential output swing 300 ? mv 8-30 slew_rise rising edge rate 1.5 4 v/ns 8-30 slew_fall falling edge rate 1.5 4 v/ns 8-30 table 8-24. clock timings (sheet 2 of 4) sym parameter min max unit notes figure
electrical characteristics 338 datasheet jitter 350 ps 8 , 9 clkout_pcie[7:0]_[p,n], clkout_dmi_[p,n], clkout_peg_[b:a]_[p,n], clkout_itpxdp_[p,n] period period ssc on 9.849 10.201 ns 8-30 period period ssc off 9.849 10.151 ns 8-30 dtycyc duty cycle 40 60 % 8-30 v_swing differential output swing 300 ? mv 8-30 slew_rise rising edge rate 1.5 4 v/ns 8-30 slew_fall falling edge rate 1.5 4 v/ns 8-30 jitter ? 150 ps 8 , 9 , 10 ssc spread spectrum 0 0.5 % 13 , 14 smbus/smlink clock (smbclk, sml[1:0]clk) f smb operating frequency 10 100 khz t22 high time 4.0 50 ? s 28-20 t23 low time 4.7 ? ? s 8-20 t24 rise time ? 1000 ns 8-20 t25 fall time ? 300 ns 8-20 smlink0 clock (sml0c lk) (see note 15) f smb operating frequency 0 400 khz t22_sml high time 0.6 50 ? s 28-20 t23_sml low time 1.3 ? ? s 8-20 t24_sml rise time ? 300 ns 8-20 t25_sml fall time ? 300 ns 8-20 hda_bclk (intel ? high definition audio) f hda operating frequency 24.0 mhz frequency tolerance ? 100 ppm t26a input jitter (refer to clock chip specification) ? 300 ppm t27a high time (measured at 0.75 vcc) 18.75 22.91 ns 8-11 t28a low time (measured at 0.35 vcc) 18.75 22.91 ns 8-11 suspend clock (susclk) f susclk operating frequency 32 khz 4 t39 high time 10 ? ? s 4 t39a low time 10 ? ? s 4 xtal25_in/xtal25_out ppm 12 crystaltolerance cut accuracy max 35ppm(@ 25 c +/- 3c) ppm 12 tempstability max 30ppm(10 c to 70c) ppm 12 aging max 5ppm table 8-24. clock timings (sheet 3 of 4) sym parameter min max unit notes figure
datasheet 339 electrical characteristics notes: 1. the clk48 expects a 40/60% duty cycle. 2. the maximum high time (t18 max) provide a simple ensured method for devices to detect bus idle conditions. 3. bclk rise and fall times are measured from 10%vdd and 90%vdd. 4. susclk duty cycle can range from 30% minimum to 70% maximum. 5. edge rates in a system as measured from 0.8 v to 2.0 v. 6. the active frequency can be 5 mhz, 50 mh z, or 62.5 mhz depend ing on the interface speed. dynamic changes of the normal operating frequency are not allowed. 7. testing condition: 1 kohm pull up to vcc, 1 kohm pull down and 10 pf pull down and 1/2 inch trace (see figure 8-31 for more detail). 8. jitter is specified as cycle to cycle as meas ured between two rising edges of the clock being characterized. period min and max includes cycle to cycle jitter and is also measured between two rising edges of the clock being characterized. 9. on all jitter measurements care should be taken to set the zero crossing voltage (for rising edge) of the clock to be the point where the edge rate is the fastest. using a math function = average(derivavitive(ch1)) and set the averages to 64, place the cursors where the slope is the highest on the rising edge ? usua lly this lower half of the rising edge. the reason this is defined is for users trying to measure in a system it is impossible to get the probe exactly at the end of the transmission line with large flip chip components, this results in a reflection induced ledge in the mi ddle of the rising edge and will si gnificantly increase measured jitter. 10. phase jitter requirement: the designated gen2 outputs will meet the reference clock jitter requirements from the pci express gen2 base specification . the test is to be performed on a component test board under quiet conditions with all clock output s on. jitter analysis is performed using a standardized tool provided by the pci sig. measurement methodology is defined in intel document ?pci expres s reference clock jitter measurements?. note that this is not for clkout_pcie[7:0]. 11. testing condition: 1-k ? pull-up to vcc, 1 k ? pull down and 10 pf pull-down and 1/2 inch trace (see figure 8-31 for more detail). 12. total of crystal cut accuracy, frequency vari ations due to temperature, parasitics, load capacitance variations and aging is recommended to be less than 90 ppm. 13. spread spectrum (ssc) is referenc ed to rising edge of the clock. 14. spread spectrum (ssc) of 0.25% on clkout _pcie[7:0] and clkout_peg_[b:a] is used for wimax friendly clocking purposes. 15. when smlink0 is configured to run in fast mode using a soft strap, the operating frequency is in the range of 300 khz?400 khz. spi_clk slew_rise output rise slew rate (0.2vcc - 0.6vcc) 14v/ns 11 8-31 slew_fall output fall slew rate (0.6vcc - 0.2vcc) 14v/ns 11 8-31 table 8-24. clock timings (sheet 4 of 4) sym parameter min max unit notes figure
electrical characteristics 340 datasheet note: 1. refer to note 3 of table 4-4 in section 4.2.2.2 and note 2 of table 4-6 in section 4.2.3.2 of the pci local bus specification, revision 2.3 for measurement details. table 8-25. pci interface timing sym parameter min max units notes figure t40 ad[31:0] valid delay 2 11 ns 1 8-12 t41 ad[31:0] setup time to pciclk rising 7 ? ns 8-13 t42 ad[31:0] hold time from pciclk rising 0 ? ns 8-13 t43 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, perr#, plock#, devsel# valid delay from pciclk rising 211ns 1 8-12 t44 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, perr#, plock#, idsel, devsel# output enable delay from pciclk rising 2n s 8-16 t45 c/be[3:0]#, frame#, trdy#, irdy#, stop#, perr#, plock#, devsel#, gnt[a:b]# float delay from pciclk rising 228ns 8-14 t46 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, perr#, devsel#, setup time to pciclk rising 7n s 8-13 t47 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, perr#, devsel#, req[a:b]# hold time from pclkin rising 0?ns 8-13 t48 pcirst# low pulse width 1 ms 8-15 t49 gnt[3:0]# valid delay from pciclk rising 212ns t50 req[3:0]# setup time to pciclk rising 12 ? ns
datasheet 341 electrical characteristics notes: 1. driver output resistance under st eady state drive is specified at 28 ? at minimum and 43 ? at maximum. 2. timing difference between th e differential data signals. 3. measured at crossover point of differential data signals. 4. measured at 50% swing point of data signals. 5. measured from last crossover point to 50% swin g point of data line at leading edge of eop. 6. measured from 10% to 90% of the data signal. 7. full-speed data rate has minimum of 11.97 mb/s and maximum of 12.03 mb/s. 8. low-speed data rate has a minimum of 1.48 mb/s and a maximum of 1.52 mb/s. table 8-26. universal serial bus timing sym parameter min max units notes fig full-speed source (note 7) t100 usbpx+, usbpx- driver rise time 4 20 ns 1, c l = 50 pf 8-17 t101 usbpx+, usbpx- driver fall time 4 20 ns 1, c l = 50 pf 8-17 t102 source differential driver jitter - to next transition - for paired transitions ?3.5 ?4 3.5 4 ns ns 2, 3 8-18 t103 source se0 interval of eop 160 175 ns 4 8-19 t104 source jitter for differential transition to se0 transition ?2 5 ns 5 t105 receiver data jitter tolerance - t o next transition - for paired transitions ?18.5 ?9 18.5 9 ns ns 3 8-18 t106 eop width: must accept as eop 82 ? ns 4 8-19 t107 width of se0 interval during differential transition ?14 ns low-speed source (note 8) t108 usbpx+, usbpx ? driver rise time 75 300 ns 1, 6 c l = 50 pf c l = 350 pf 8-17 t109 usbpx+, usbpx ? driver fall time 75 300 ns 1,6 c l = 50 pf c l = 350 pf 8-17 t110 source differential driver jitter to n e x t tra n s i t i o n for paired transitions ?25 ?14 25 14 ns ns 2, 3 8-18 t111 source se0 interval of eop 1.25 1.50 s 4 8-19 t112 source jitter for differential transition to se0 transition ?40 100 ns 5 t113 receiver data jitter tolerance - to next transition - for paired transitions ?152 ?200 152 200 ns ns 3 8-18 t114 eop width: must accept as eop 670 ? ns 4 8-19 t115 width of se0 in ter val during differential transition ? 210 ns
electrical characteristics 342 datasheet notes: 1. 20% ? 80% at transmitter 2. 80% ? 20% at transmitter 3. as measured from 100 mv differential cros spoints of last and first edges of burst. 4. operating data period during out-of-band burst transmissions. table 8-27. sata interface timings sym parameter min max units notes figure ui gen i operating data period 666.43 670.23 ps ui-2 gen ii operating data period (3gb/s) 333.21 335.11 ps ui-3 gen iii operating data period (6gb/s) 166.6083 166.6667 ps t120gen1 rise time 0.15 0.41 ui 1 t120gen2 rise time 0.2 0.41 ui 1 t120gen3 rise time 0.2 0.41 ui 1 t121gen1 fall time 0.15 0.41 ui 2 t121gen2 fall time 0.2 0.41 ui 2 t121gen3 fall time 0.2 0.41 ui 2 t122 tx differential skew ? 20 ps t123 comreset 310.4 329.6 ns 3 t124 comwake transmit spacing 103.5 109.9 ns 3 t125 oob operating data period 646.67 686.67 ns 4
datasheet 343 electrical characteristics notes: 1. a device will timeout when an y clock low exceeds this value. 2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. if a slave device exceeds this time, it is expected to release both its clock and da ta lines and reset itself. 3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop. 4. t134 has a minimum timing for i 2 c of 0 ns, while the minimum timing for smbus/smlink is 300 ns. 5. timings with the smlfm designator apply on ly to smlink0 and only when smlink0 is operating in fast mode. table 8-28. smbus and smlink timing sym parameter min max units notes fig t130 bus free time between stop and start condition 4.7 ? s 8-20 t130smlfm bus free time between stop and start condition 1.3 ? s 58-20 t131 hold time after (repeated) start condition. after this period, the first clock is generated. 4.0 ? s 8-20 t131smlfm hold time after (repeated) start condition. after this period, the first clock is generated. 0.6 ? s 58-20 t132 repeated start cond ition setup time 4.7 ? s 8-20 t132smlfm repeated start co ndition setup time 0.6 ? s 58-20 t133 stop condition setup time 4.0 ? s 8-20 t133smlfm stop condition setup time 0.6 ? s 58-20 t134 data hold time 0 ? ns 48-20 t134smlfm data hold time 0 ? ns 4, 5 8-20 t135 data setup time 250 ? ns 8-20 t135smlfm data setup time 100 ? ns 58-20 t136 device time out 25 35 ms 1 t137 cumulative clock low extend time (slave device) ?25 ms 28-21 t138 cumulative clock low extend time (master device) ?10 ms 38-21
electrical characteristics 344 datasheet table 8-29. intel ? high definition audio timing sym parameter min max units notes fig t143 time duration for which hda_sd is valid before hda_bclk edge. 7? ns 8-23 t144 time duration for which hda_sdo is valid after hda_bclk edge. 7? ns 8-23 t145 setup time for hda_sdin[3:0] at rising edge of hda_bclk 15 ? ns 8-23 t146 hold time for hda_sdin[3:0] at rising edge of hda_bclk 0? ns 8-23 table 8-30. lpc timing sym parameter min max units notes fig t150 lad[3:0] valid delay from pciclk rising 211 ns 8-12 t151 lad[3:0] output enable delay from pciclk rising 2? ns 8-16 t152 lad[3:0] float delay from pciclk rising ?28 ns 8-14 t153 lad[3:0] setup time to pciclk rising 7 ? ns 8-13 t154 lad[3:0] hold time from pciclk rising 0 ? ns 8-13 t155 ldrq[1:0]# setup time to pciclk rising 12 ? ns 8-13 t156 ldrq[1:0]# hold time from pciclk rising 0? ns 8-13 t157 ee# valid delay from pciclk rising 2 12 ns 8-12 table 8-31. miscellaneous timings sym parameter min max units notes fig t160 serirq setup time to pciclk rising 7 ? ns 8-13 t161 serirq hold time from pciclk rising 0 ? ns 8-13 t162 ri#, gpio, usb resu me pulse width 2 ? rtcclk 8-15 t163 spkr valid delay from osc rising ? 200 ns 8-12 t164 serr# active to nmi active ? 200 ns
datasheet 345 electrical characteristics notes: 1. the typical clock frequency dr iven by the pch is 17.86 mhz. 2. measurement point for low time and high time is taken at 0.5(vccspi) note: 1. the typical clock frequency dr iven by the pch is 31.25 mhz. 2. measurement point for low time and high time is taken at 0.5(vccspi). table 8-32. spi timings (20 mhz) sym parameter min max units notes fig t180a serial clock frequency - 20m hz operation 17.06 18.73 mhz 1 t183a tco of spi_mosi with respect to serial clock falling edge at the host -5 13 ns 8-22 t184a setup of spi_miso with respect to serial clock falling edge at the host 16 ? ns 8-22 t185a hold of spi_miso with respect to serial clock falling edge at the host 0? ns 8-22 t186a setup of spi_cs[1:0]# assertion with respect to serial clock rising at the host 30 ? ns 8-22 t187a hold of spi_cs[1:0]# deassertion with respect to serial clock falling at the host 30 ? ns 8-22 t188a spi_clk high time 26.37 ? ns 8-22 t189a spi_clk low time 26.82 ? ns 8-22 table 8-33. spi timings (33 mhz) sym parameter min max units notes fig t180b serial clock frequency - 33 mhz operation 29.83 32.81 mhz 1 t183b tco of spi_mosi with respect to serial clock falling edge at the host -5 5 ns 8-22 t184b setup of spi_miso with respect to serial clock falling edge at the host 8?ns 8-22 t185b hold of spi_miso with respect to serial clock falling edge at the host 0?ns 8-22 t186b setup of spi_cs[1:0]# assertion with respect to serial clock rising at the host 30 ? ns 8-22 t187b hold of spi_cs[1:0]# deassertion with respect to serial clock falling at the host 30 ? ns 8-22 t188b spi_clk high time 14.88 - ns 8-22 t189b spi_clk low time 15.18 - ns 8-22
electrical characteristics 346 datasheet note: 1. typical clock frequency driven by the pch is 50 mhz. 2. when using 50 mhz mode ensure target flash component can meet t188c and t189c specifications. measurement should be taken at a point as close as po ssible to the package pin. 3. measurement point for low time and high time is taken at 0.5(vccspi). notes: 1. the originator must drive a mo re restrictive time to allow fo r quantized sampling errors by a client yet still attain the minimum time less than 500 s. t bit limits apply equally to t bit - a and t bit -m. pch is targeted on 1 mbps which is 1 s bit time. 2. the minimum and maximum bit times are relative to t bit defined in the timing negotiation pulse. 3. t bit -a is the negotiated address bit time and t bit -m is the negotiated message bit time. table 8-34. spi timings (50 mhz) sym parameter min max units notes fig t180c serial clock frequency - 50-mhz operation 46.99 53.40 mhz 1 t183c tco of spi_mosi with respect to serial clock falling edge at the host -3 3 ns 8-22 t184c setup of spi_miso with respect to serial clock falling edge at the host 8?ns 8-22 t185c hold of spi_miso with respect to serial clock falling edge at the host 0?ns 8-22 t186c setup of spi_cs[1:0]# assertion with respect to serial clock rising edge at the host 30 ? ns 8-22 t187c hold of spi_cs[1:0]# assertion with respect to serial clock rising edge at the host 30 ? ns 8-22 t188c spi_clk high time 7.1 ? ns 2, 3 8-22 t189c spi_clk low time 11.17 ? ns 2, 3 8-22 table 8-35. sst timings (s erver/workstation only) sym parameter min max units notes fig t bit bit time (overall time evident on sst) bit time driven by an originator 0.495 0.495 500 250 s s 1- t bit, jitter bit time jitter between adjacent bits in an sst message header or data bytes after timing has been negotiated ??% t bit ,drift change in bit time across a sst address or sst message bits as driven by the originator. this limit only applies across t bit-a bit drift and t bit-m drift. ??% t h1 high level time for logic '1' 0.6 0.8 x t bit 2 t h0 high level time for logic '0' 0.2 0.4 x t bit t sstr rise time (measured from v ol = 0.3v to v ih,min ) ?25 + 5 ns/ node t sstf fall time (measured from v oh = 1.1v to v il,max ) ?33 ns/ node
datasheet 347 electrical characteristics notes: 1. measured from (cl_vref ? 50 mv to cl_vref + 50 mv) at the receiving device side. no test load is required for this measurement as the receiving device fulfills this purpose. 2. cl_vref = 0.12*(vccsus3_3). 8.7 power sequencing and reset signal timings table 8-36. controller link receive timings sym parameter min max units notes fig t190 single bit time 13 ? ns 8-32 t191 single clock period 15 ? ns 8-32 t192 rise time/fall time 0.11 3.5 v/ns 1 8-33 t193 setup time before cl_clk1 0.9 ? ns 8-32 t194 hold time after cl_clk1 0.9 ? ns 8-32 v il_ac input low voltage (ac) cl_vref - 0.08 v2 v ih_ac input high voltage (ac) cl_vref +0.08 v2 table 8-37. power sequencing and re set signal timings (sheet 1 of 2) sym parameter min max units notes fig t200 vccrtc active to rtcrst# deassertion 9 ? ms 8-1 , 8-2 t200a rtcrst# deassertion to dpwrok high 0 ? ms 8-1 , 8-2 t200b vccdsw3_3 active to dpwrok high 10 ? ms 8-1 , 8-2 t200c vccdsw3_3 active to vccsus3_3 active 0 ? ms 8-1 , 8-2 t201 vccsus active to rsmrst# deassertion 10 ? ms 1 8-1 , 8-2 t202 dpwrok high to slp_su s# deassertion 95 ? ms 2, 3 8-1 , 8-2 t202a rsmrst# and slp_sus# deassertion to susclk toggling 5?ms 3, 4 8-1 , 8-2 t203 slp_s5# high to slp_s4# high 30 s 5 8-3 t204 slp_s4# high to slp_s3# high 30 s 6 8-3 t205 vcc active to pwrok high 10 ? ms 7, 13 t206 pwrok deglitch time 1 ? ms 8 t207 vccasw active to apwrok high 1 ? ms t208 pwrok high to pch clock outputs stable 1 ? ms 9 t209 pch clock output stable to procpwrgd high 1 ? ms t210 procpwrgd and sys_pwrok high to sus_stat# deassertion 1?ms t211 sus_stat# deassertion to pltrst# deassertion 60 ? s t212 apwrok high to spi soft-strap reads 500 ? s 21 t213 apwrok high to cl_r st1# deasserted 500 ? s 10 t214 dmi message and all pci express ports and dmi in l2/l3 state to sus_stat# active 60 ? s 8-6
electrical characteristics 348 datasheet t215 sus_stat# active to pltrst# active 210 ? s 8-6 t217 pltrst# active to procpwrgd inactive 30 ? s 8-6 t218 procpwrgd inactive to clocks invalid 10 ? s 8-6 t219 clocks invalid to slp_s3# assertion 1 ? s 8-6 t220 slp_s3# low to slp_s4# low 30 ? s 8-6 t221 slp_s4# low to slp_s5# low 30 ? s 8-6 t222 slp_s3# active to pwrok deasserted 0 ? 8-6 t223 pwrok rising to drampwrok rising 0 ? s 8-8 t224 drampwrok falling to slp_s4# falling -100 ? ns 11 8-8 t225 vccrtc active to vccdsw3_3 active 0 ? ms 1, 12 8-2 t226 rtcrst# deassertion to rsmrst# deassertion 20 ? ns 8-2 t227 vccsus active to vccasw active 0 ? ms 1 t229 vccasw active to vcc active 0 ? ms t230 apwrok high to pwrok high 0 ? ms t231 pwrok low to vcc falling 40 ? ns 13, 14, 15 t232 apwrok falling to vccasw falling 40 ? ns 15 t233 slp_s3# assertion to vcccore rail falling 5 ? s 13, 14 t234 dpwrok falling to vccdsw rail falling 40 ns 8-7 t235 rsmrst# assertion to vccsus rail falling 40 ? ns 1, 14, 15 8-7 t236 rtcrst# deassertion to vccrtc rail falling 0 ? ms 8-7 t237 slp_lan# (or lanphypc) rising to intel lan phy power high and stable ?20ms t238 dpwrok falling to any of vccdsw, vccsus, vccasw, vccasw3_3, or vcc falling 40 ? ns 1, 13, 14, 15 t239 v5ref_sus active to vccsus3_3 active 0 ? ms 16 t240 v5ref active to vcc3_3 active see note 15 ?ms 16 t241 vccsus supplies active to vcc supplies active 0 ? ms 1, 13 t242 hda_rst# active low pulse width 1 ? ? s t244 vccsus active to slp_s5 #, slp_s4#, slp_s3#, sus_stat#, pltrst# and pcirst# valid ?50ns 20 t246 s4 wake event to slp_s4# inactive (s4 wake) see note below 5 t247 s3 wake event to slp_s3# inactive (s3 wake) see note below 6 t251 rsmrst# deassertion to apwrok assertion 0 ? ms t252 thrmtrip# active to slp_s3#, slp_s4#, slp_s5# active ? 175 ns t253 rsmrst# rising edge transition from 20% to 80% ?50 ? s t254 rsmrst# falling edge transition ? 50 s 18, 19 table 8-37. power sequencing and reset signal timings (sheet 2 of 2) sym parameter min max units notes fig
datasheet 349 electrical characteristics notes: 1. vccsus supplies include vccsus 3_3, v5ref_sus, and vccsushda. also includes dcpsus for mobile platforms that power dcpsus externally. 2. this timing is a nominal value counted using rt c clock. if rtc clock is n?t already stable at the rising edge of rsmrst#, this timing could be shorter or longer than the specified value. 3. platforms not supporting deep s4/s5 will typi cally have slp_sus# le ft as no connect. hence dpwrok high and rsmrst# deasse rtion to susclk toggling would be t202+t202a=100 ms minimum. 4. platforms supporting deep s4/s5 will have slp_sus# deassert prior to rsmrst#. platforms not supporting deep s4/s5 will ha ve rsmrst# deassert prior to slp_sus#. 5. dependency on slp_s4# and slp_a# stretching 6. dependency on slp_s3# and slp_a# stretching 7. it is required that the power rails associated with pci/pcie (typically the 3.3 v, 5 v, and 12 v core well rails) have been valid for 99 ms prior to pwrok assertion in order to comply with the 100 ms pci/pcie 2.0 specification on pltrst# deassertion. system designers must ensure the requiremen t is met on the platforms. 8. ensure pwrok is a solid logic '1' befo re proceeding with the boot sequence. note: if pwrok drops after t206 it will be considered a power failure. 9. timing is dependant on whether 25 mhz crys tal is stable by the time pwrok is high. 10. requires spi messaging to be completed. 11. the negative min timing implies that dram pwrok must either fall before slp_s4# or within 100 ns after it. 12. the vccdsw3_3 supplies must never be active while the vccrtc supply is inactive. 13. vcc includes vccio, vcccore, vcc3_3, vccadplla, vccadpllb, vccadac, v5ref, v_proc_io, vccclkdmi, vccdiffclkn, vccv rm, vccdfterm, vccssc , vccalvds (mobile only), vcctxlvds (mobile on ly) and vccasw (if intel ? me only powered in s0). 14. a power rail is considered to be inactive when the rail is at its nominal voltage minus 5% or less. 15. board design may meet (t231 and t232 and t235) or (t238). 16. v5ref must be powered up before vcc3_3, or after vcc3_3 within 0.7 v. also, v5ref must power down after vcc3_3, or before vcc3_3 wi thin 0.7 v. v5ref_sus must be powered up before vccsus3_3, or after vccsus3_3 within 0.7 v. also, v5ref_sus must power down after vccsus3_3, or before vccsus3_3 within 0.7 v. 17. if rtc clock is not already stable at rsmr st# rising edge, this time may be longer. 18. rsmrst# falling edge must transition to 0.8 v or less before vccsus3_3 drops to 2.9 v 19. the 50 s should be measured from vih to vil (2 v to 0.78 v). 20. this is an internal timing showing when the signals (slp_s5#, slp_s4#, slp_s3#, sus_stat#, pltrst# and pcirst#) are valid after vccsus rail is active. 21. apwrok high to spi soft-strap read is an internal pch timing. the timing cannot be measured externally and in cluded here for general po wer sequencing reference.
electrical characteristics 350 datasheet 8.8 power management timing diagrams figure 8-1. g3 w/rtc loss to s4/s5 (with deep s4/s5 support) timing diagram signal name destination source susclk rsmrst# board pch board vccrtc board pch rtcrst# board pch t200 vccsus board pch t201 slp_s5# pch board o nly for s 4 after g 3 or d eepsx vccdsw3_3 board pch dpwrok board pch g3 t200 b t200c deep s4/s5 t202 valid s5/s4 pch t200 a t202a t225 t226 slp_sus# pch board figure 8-2. g3 w/rtc loss to s4/s5 (without deep s4/s5 support) timing diagram signal name d estination source susclk rsmrst# board pch pch board vccrtc board pch rtcrst# board pch t200 vccsus board pch t202 slp_s5# pch board vccdsw3_3 board pch dpwrok board pch g3 t200b t201 valid s5/s4 only for s4 after g3 t200a t200c t202a t226 t225 slp_sus# pch board
datasheet 351 electrical characteristics figure 8-3. s5 to s0 timing diagram apwrok may come up earlier than pwrok, but no later slp_s3# slp_a# signal name dest source slp_s4# slp_s5# pch board pch board pch board pch board board pch vcccore_cpu board cpu procpwrgd sus_stat# pwrok drampwrok sys_pwrok cpu vrm pch board pch pch cpu apwrok board pch vcc board pch 25 mhz crystal osc board pch stable t209 pltrst# dmi pch cpu pch board pch cpu/board pch cpu t203 t204 t205 t207 t r a i n i n g s t r a p _ s e t c p u _ r e s e t _ d o n e f l e x s k u v d m w r it e s c p u _ r e s e t _ d o n e _ a c k t211 t206 v_vid t210 slp_lan# pch board could already be high before this sequence begins (to support wol), but will never go high later than slp_s3# or slp_a# vccasw could already be high before this sequence begins (to support m3), but will never go high later than slp_s3# thrmtrip# cpu pch ignored honored assumes soft strap programmed to start at procpwrgd - expected setting for snb cpu svid cpu cpu vrm serial vid load procpwrgd t208 stable pch output clocks pch board t229 t230
electrical characteristics 352 datasheet figure 8-4. s3/m3 to s0 timing diagram slp_s3# slp_a# cpu svid signal name dest source slp_s4# slp_s5# pch board pch board pch board pch board board pch vcccore_cpu cpu cpu vrm board cpu procpwrgd sus_stat# pwrok drampwrok sys_pwrok cpu vrm pch board pch pch cpu apwrok board pch vcc board pch 25 mhz crystal osc board pch stable pltrst# dmi pch cpu pch board pch cpu/board pch cpu t205 t r a i n i n g s t r a p _ s e t c p u _ r e s e t _ d o n e f l ex s k u v d m w ri t e s c p u _ r e s e t _d o n e _ a c k t211 t206 serial vid load note: v_proc_io may go to vboot at this time, but can also stay at 0v (default) v_vid procpwrgd t210 slp_lan# pch board vccasw thrmtrip# cpu pch ignored honored assumes soft strap programmed to start at cpupwrgd - expected setting for snb stable pch output clocks pch board t209 t208 figure 8-5. s5/moff - s5/m3 timing diagram slp_s3# slp_a# signal name dest source slp_s4# slp_s5# pch board pch board pch board pch board board pch apwrok board pch t207 slp_lan# pch board could already be high before this sequence begins (to support wol), but will never go high later than slp_a# vccasw spi cl_rst1# (m obile o nly) spi flash controller link t212 t213 pch pch
datasheet 353 electrical characteristics figure 8-6. s0 to s5 timing diagram signal name dest source thrmtrip# cpu pch honored valid pltrst# pch board procpwrgd pch board pch output clocks pch board slp_s3# pch board pwrok board pch t218 t219 ignored t222 slp_a# slp_s4# slp_s5# pch board pch board pch board drampwrok pch cpu me-related signals going to m3: stay high going to moff: go low sys_pwrok board pch apwrok board pch t220 t221 may drop before or after slp_s4/5# and drampwrgd cl_rst# pch source of lanphypc value pch gbe phy value from mac latched in sus well live value from gbe mac only switch if going to moff if appropriate, save mac pmcsr context here controller link slp_lan# pch board slp_lan# could stay high for m3 or wol dmi pcie ports pch pcie* devices normal operation l2/l3 dmi message l2/l3 sus_stat# pch board t214 t215 t217
electrical characteristics 354 datasheet figure 8-7. s4/s5 to deep s4/s5 to g3 w/ rtc loss timing diagram signal name destination source dpwrok board pch vccdsw board pch slp_sus# pch board suswarn# p c h b oard (e c ) susack# board (ec) pch rsmrst# board pch vccsus board pch slp_s3# / slp_s4# / slp_a# pch board slp_s5# pch board slp_s5# drops here if not already asserted undriven undriven undriven undriven t235 rtcrst# board pch vccrtc board pch g3 deep s4/s5 t234 t236 s4/s5 figure 8-8. drampwrok timing diagram signal name destination source slp_s4# pch board pwrok board pch t223 drampwrok pch cpu t224
datasheet 355 electrical characteristics 8.9 ac timing diagrams figure 8-9. clock cycle time figure 8-10. transmitting position (data to strobe) clka/ clkb ya/yb tppos1 tppos2 tppos3 tppos4 tppos5 tppos6 tppos0 figure 8-11. clock timing 2.0v 0.8v period high time low time fall time rise time
electrical characteristics 356 datasheet figure 8-12. valid delay from rising clock edge figure 8-13. setup and hold times figure 8-14. float delay figure 8-15. pulse width clock 1.5v valid delay vt output clock vt input hold time setup time vt 1.5v input vt output float delay vt pulse width vt
datasheet 357 electrical characteristics figure 8-16. output enable delay figure 8-17. usb rise and fall times figure 8-18. usb jitter clock output output enable delay vt 1.5v differential data lines 90% 10% 10% 90% t r t f rise time fall time c l c l low-speed: 75 ns at c l = 50 pf, 300 ns at c l = 350 pf full-speed: 4 to 20 ns at c l = 50 pf high-speed: 0.8 to 1.2 ns at c l = 10 pf paired transitions consecutive transitions crossover points t period differential data lines jitter
electrical characteristics 358 datasheet figure 8-19. usb eop width figure 8-20. smbus transaction figure 8-21. smbus timeout differential data lines eop width data crossover level tperiod t130 smbclk smbdata t131 t19 t134 t20 t21 t135 t132 t18 t133 start stop t137 clk ack clk ack t138 t138 smbclk smbdata
datasheet 359 electrical characteristics figure 8-22. spi timings figure 8-23. intel ? high definition audio input and output timings spi_clk spi_mosi spi_miso spi_cs# t186 t187 t184 t185 t183 t189 t188 hda_sdout hda_sdin[3:0] hda_bit_clk t143 t143 t144 t144 t145 t146
electrical characteristics 360 datasheet figure 8-24. dual chan nel interface timings figure 8-25. dual chan nel interface timings figure 8-26. lvds load and transition times dqs dq[7:0] td qsl tdh td s tdqs tdh tds dq dq[7:0] tdvw tdqsq tdqsq tqh
datasheet 361 electrical characteristics figure 8-27. transmitting position (data to strobe) clka/ clkb ya/yb tppos1 tppos2 tppos3 tppos4 tppos5 tppos6 tppos0 figure 8-28. pci express transmitter eye
electrical characteristics 362 datasheet figure 8-29. pci ex press receiver eye v rs-diffp-p-min>175mv .4 ui =t rx-eye min v ts-diff = 0mv d+/d- crossing point
datasheet 363 electrical characteristics figure 8-30. measurement poin ts for differential waveforms. v min = -0 .30 v v max = 1 .15 v vcross max = 550 mv vcross min = 300 mv vcr oss delta = 140 mv v min = -0. 30 v v m ax = 1.15 v vcross max = 550 mv vcross min = 300 mv vcross delta = 140 mv clock# clock clock clock# vcross median clock clock# vcross median clock clock# vcross median +75 m v vcross median -75 mv t r i s e tf a ll clock-clock# vih_ min = +150 mv vil_max = -150 mv positive duty cycle (differential ) 0.0v clock-clock# .0 v negative duty cycle (differential ) clock period (differential ) fall edge rate rise edge rate differential clock ? differential measurements differential clock ? single ended measurements
electrical characteristics 364 datasheet figure 8-31. pch test load vccasw3_3 figure 8-32. controller link receive timings figure 8-33. controller link receive slew rate t190 cl_clk1 cl_data1 t191 t193 t194 t192 cl_vref ? 50mv cl_vref + 50mv t192 cl_vref cl_clk1 / cl_data1
datasheet 365 register and memory mapping 9 register and memory mapping the pch contains registers that are located in the processor?s i/o space and memory space and sets of pci configuration registers that are located in pci configuration space. this chapter describes the pch i/o and memory maps at the register-set level. register access is also described. register-level address maps and individual register bit descriptions are provided in the followi ng chapters. the following notations and definitions are used in the register /instruction description chapters. ro read only. in some cases, if a register is read only, writes to this register location have no effect. however, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. see the i/o and memory map tables for details. wo write only. in some cases, if a register is write only, reads to this register location have no effect. however, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. see the i/o and memory map tables for details. r/w read/write. a register with this attribute can be read and written. r/wc read/write clear. a register bit with this attribute can be read and written. however, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. r/wo read/write-once. a register bit with this attribute can be written only once after power up. after the first write, the bit becomes read only. r/wl read/write lockable. a register bit with the attribute can be read at any time but writes may only occur if the associated lock bit is set to unlock. if the associated lock bit is set to lock, this register bit becomes ro unless otherwise indicated. r/wlo read/write, lock-once. a register bit with this attribute can be written to the non-locked value multiple times, but to the locked value only once. after the locked value has been written, the bit becomes read only. reserved the value of reserved bits must never be changed. for details see section 9.2 . default when the pch is reset, it sets its registers to predetermined default states. it is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the pch registers accordingly. bold register bits that are highlighted in bold text indicate that the bit is implemented in the pch. register bits that are not implemented or are hardwired will remain in plain text.
register and memory mapping 366 datasheet 9.1 pci devices and functions the pch incorporates a variety of pci devices and functions, as shown in ta b l e 9 - 1 . if for some reason, the particular system platform does not want to support any one of the device functions, with the exception of d30:f0, can individually be disabled. the integrated gigabit ethernet controller will be disabled if no platform lan connect component is detected (see section 5.3 ). when a function is disabled, it does not appear at all to the software. a disabled function will not respond to any register reads or writes, insuring that these devices appear hidden to software. notes: 1. the pci-to-lpc bridge contai ns registers that control lp c, power manage ment, system management, gpio, proces sor interface, rtc, inte rrupts, timers, and dma. 2. sata controller 2 (d31:f5) is only visible when d31:f2 cc.scc=01h. 3. prior to bios initialization of the pch usb su bsystem, the ehci contro llers will appear as function 7. after bios initialization, th e ehci controllers will be function 0. 4. this table shows the default pci express function number-to- root port mapping. function numbers for a given root port are assignable through the ?root port function number and hide for pci express root po rts? register (rcba+0404h). table 9-1. pci devi ces and functions bus:device:function function description bus 0:device 30:function 0 pci-to-pci bridge bus 0:device 31:function 0 lpc controller 1 bus 0:device 31:function 2 sata controller #1 bus 0:device 31:function 3 smbus controller bus 0:device 31:function 5 sata controller #2 2 bus 0:device 31:function 6 thermal subsystem bus 0:device 29:function 0 3 usb ehci controller #1 bus 0:device 26:function 0 3 usb ehci controller #2 bus 0:device 28:function 0 pci express* port 1 bus 0:device 28:function 1 pci express port 2 bus 0:device 28:function 2 pci express port 3 bus 0:device 28:function 3 pci express port 4 bus 0:device 28:function 4 pci express port 5 bus 0:device 28:function 5 pci express port 6 bus 0:device 28:function 6 pci express port 7 bus 0:device 28:function 7 pci express port 8 bus 0:device 27:function 0 intel ? high definition audio controller bus 0:device 25:function 0 gigabit ethernet controller bus 0:device 22:function 0 intel ? management engi ne interface #1 bus 0:device 22:function 1 intel management engine interface #2 bus 0:device 22:function 2 ide-r bus 0:device 22:function 3 kt
datasheet 367 register and memory mapping 9.2 pci configuration map each pci function on the pch has a set of pci configuration registers. the register address map tables for these register sets are included at the beginning of the chapter for the particular function. configuration space registers are accessed th rough configuration cycles on the pci bus by the host bridge using configur ation mechanism #1 detailed in the pci local bus specification, revision 2.3 . some of the pci registers contain reserved bits. software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of re served bit positions are preserved. that is, the values of reserved bit positions must fi rst be read, merged with the new values for other bit positions and then written back. no te the software does not need to perform read, merge, write operation for the configuration address register. in addition to reserved bits within a register, the configuration space contains reserved locations. software should not write to re served pci configuration locations in the device-specific region (above address offset 3fh). 9.3 i/o map the i/o map is divided into fixed and variable address ranges. fixed ranges cannot be moved, but in some cases can be disabled. variable ranges can be moved and can also be disabled. 9.3.1 fixed i/o address ranges ta b l e 9 - 2 shows the fixed i/o decode ranges from the processor perspective. note that for each i/o range, there may be separate behavior for reads and writes. dmi (direct media interface) cycles that go to target ranges that are marked as ?reserved? will not be decoded by the pch, and will be passed to pci unless the subtractive decode policy bit is set (d31:f0:offset 42h, bit 0). if a pci master targets one of the fixed i/o target ranges, it will be positively deco ded by the pch in medium speed. address ranges that are not listed or marked ?reserved? are not decoded by the pch (unless assigned to one of the variable ranges).
register and memory mapping 368 datasheet table 9-2. fixed i/o ranges de coded by pch (sheet 1 of 2) i/o address read target write target internal unit 00h?08h dma controller dma controller dma 09h?0eh reserved dma controller dma 0fh dma controller dma controller dma 10h?18h dma controller dma controller dma 19h?1eh reserved dma controller dma 1fh dma controller dma controller dma 20h?21h interrupt controller interrupt controller interrupt 24h?25h interrupt controller interrupt controller interrupt 28h?29h interrupt controller interrupt controller interrupt 2ch?2dh interrupt controller interrupt controller interrupt 2eh?2fh lpc sio lpc sio forwarded to lpc 30h?31h interrupt controller interrupt controller interrupt 34h?35h interrupt controller interrupt controller interrupt 38h?39h interrupt controller interrupt controller interrupt 3ch?3dh interrupt controller interrupt controller interrupt 40h?42h timer/counter timer/counter pit (8254) 43h reserved timer/counter pit 4eh?4fh lpc sio lpc sio forwarded to lpc 50h?52h timer/counter timer/counter pit 53h reserved timer/counter pit 60h microcontroller microcontroller forwarded to lpc 61h nmi controller nmi controller processor i/f 62h microcontroller microcontroller forwarded to lpc 64h microcontroller microcontroller forwarded to lpc 66h microcontroller microcontroller forwarded to lpc 70h reserved 1 nmi and rtc controller rtc 71h rtc controller rtc controller rtc 72h rtc controller nmi and rtc controller rtc 73h rtc controller rtc controller rtc 74h rtc controller nmi and rtc controller rtc 75h rtc controller rtc controller rtc 76h rtc controller nmi and rtc controller rtc 77h rtc controller rtc controller rtc 80h dma controller, lpc, pci, or pcie dma controller and lpc, pci, or pcie dma 81h?83h dma controller dma controller dma 84h?86h dma controller dma controller and lpc, pci, or pcie dma 87h dma controller dma controller dma 88h dma controller dma controller and lpc, pci, or pcie dma 89h?8bh dma controller dma controller dma 8ch?8eh dma controller dma controll er and lpc, pci, or pcie dma
datasheet 369 register and memory mapping note: 1. see section 13.7.2 8fh dma controller dma controller dma 90h?91h dma controller dma controller dma 92h reset generator reset generator processor i/f 93h?9fh dma controller dma controller dma a0h?a1h interrupt controller interrupt controller interrupt a4h?a5h interrupt controller interrupt controller interrupt a8h?a9h interrupt controller interrupt controller interrupt ach?adh interrupt controller interrupt controller interrupt b0h?b1h interrupt controller interrupt controller interrupt b2h?b3h power management power management power management b4h?b5h interrupt controller interrupt controller interrupt b8h?b9h interrupt controller interrupt controller interrupt bch?bdh interrupt controller interrupt controller interrupt c0h?d1h dma controller dma controller dma d2h?ddh reserved dma controller dma deh?dfh dma controller dma controller dma f0h ferr# / interrupt controller ferr# / interrupt contro ller processor i/f 170h?177h sata controller, pci, or pcie sata controller, pci, or pcie sata 1f0h?1f7h sata controller, pci, or pcie sata controller, pci, or pcie sata 200h?207h gameport low gameport low forwarded to lpc 208h?20fh gameport high gamepo rt high forwarded to lpc 376h sata controller, pci, or pcie sata controller, pci, or pcie sata 3f6h sata controller, pci, or pcie sata controller, pci, or pcie sata 4d0h?4d1h interrupt controller interrupt controller interrupt cf9h reset generator reset generator processor i/f table 9-2. fixed i/o ranges de coded by pch (sheet 2 of 2) i/o address read target write target internal unit
register and memory mapping 370 datasheet 9.3.2 variable i/o decode ranges ta b l e 9 - 3 shows the variable i/o decode ranges. they are set using base address registers (bars) or other configuration bits in the various pci configuration spaces. the pnp software (pci or acpi) can use their configuration mechanisms to set and adjust these values. warning: the variable i/o ranges should not be set to conflict with the fixed i/o ranges. unpredictable results if the configuration so ftware allows conflicts to occur. the pch does not perform any checks for conflicts. note: 1. all ranges are decoded directly from dmi. the i/o cycles will not be seen on pci, except the range associated with pci bridge. table 9-3. variable i/o decode ranges range name mappable size (bytes) target acpi anywhere in 64 kb i/o space 64 power management ide bus master anywhere in 64 kb i/o space 1. 16 or 32 2. 16 1. sata host controller #1, #2 2. ide-r native ide command anywhere in 64 kb i/o space 1 8 1. sata host controller #1, #2 2. ide-r native ide control anywhere in 64 kb i/o space 1 4 1. sata host controller #1, #2 2. ide-r sata index/data pair anywhere in 64 kb i/o space 16 sata host controller #1, #2 smbus anywhere in 64 kb i/o space 32 smb unit tco 96 bytes above acpi base 32 tco unit gpio anywhere in 64 kb i/o space 128 gpio unit parallel port 3 ranges in 64 kb i/o space 8 3 lpc peripheral serial port 1 8 ranges in 64 kb i/o space 8 lpc peripheral serial port 2 8 ranges in 64 kb i/o space 8 lpc peripheral floppy disk controller 2 ranges in 64 kb i/o space 8 lpc peripheral lan anywhere in 64 kb i/o space 32 2 lan unit lpc generic 1 anywhere in 64 kb i/o space 4 to 256 lpc peripheral lpc generic 2 anywhere in 64 kb i/o space 4 to 256 lpc peripheral lpc generic 3 anywhere in 64 kb i/o space 4 to 256 lpc peripheral lpc generic 4 anywhere in 64 kb i/o space 4 to 256 lpc peripheral i/o trapping ranges anywhere in 64 kb i/o space 1 to 256 trap on backbone pci bridge anywhere in 64 kb i/o space i/o base/ limit pci bridge pci express root ports anywhere in 64 kb i/o space i/o base/ limit pci express root ports 1?8 kt anywhere in 64 kb i/o space 8 kt
datasheet 371 register and memory mapping 2. the lan range is typically not used, as the registers can also be accessed via a memory space. 3. there is also an alias 400h above the parallel port range that is used for ecp parallel ports. 9.4 memory map ta b l e 9 - 4 shows (from the processor perspective) the memory ranges that the pch decodes. cycles that arrive from dmi that are not directed to any of the internal memory targets that decode directly from dmi will be driven out on pci unless the subtractive decode policy bit is set (d31:f0:offset 42h, bit 0). pci cycles generated by external pci masters will be positively decoded unless they fall in the pci-to-pci bridge memory forwarding ranges (those addresses are reserved for pci peer-to-peer traffic). if the cycle is not in the internal lan controller?s range, it will be forwarded up to dmi. software must not attempt locks to the pch memory-mapped i/o ranges for ehci and hpet. if attempte d, the lock is not honored which means potential deadlock conditions may occur. table 9-4. memory decode ranges from processor perspective (sheet 1 of 3) memory range target dependency/comments 0000 0000h?000d ffffh 0010 0000h?tom (top of memory) main memory tom register s in host controller 000e 0000h?000e ffffh lpc or spi bit 6 in bios decode enable register is set 000f 0000h?000f ffffh lpc or spi bit 7 in bios decode enable register is set fec_ _000h?fec_ _040h io(x) apic inside pch _ _is controlled using apic range select (asel) field and apic enable (aen) bit fec1 0000h?fec1 7fff pci express* port 1 pci expr ess* root port 1 i/oxapic enable (pae) set fec1 8000h?fec1 8fffh pci express* port 2 pci ex press* root port 2 i/oxapic enable (pae) set fec2 0000h?fec2 7fffh pci express* port 3 pci ex press* root port 3 i/oxapic enable (pae) set fec2 8000h?fec2 8fffh pci express* port 4 pci ex press* root port 4 i/oxapic enable (pae) set fec3 0000h?fec3 7fffh pci express* port 5 pci ex press* root port 5 i/oxapic enable (pae) set fec3 8000h?fec3 8fffh pci express* port 6 pci ex press* root port 6 i/oxapic enable (pae) set fec4 0000h?fec4 7fff pci express* port 7 pci expr ess* root port 7 i/oxapic enable (pae) set fec4 8000h?fec4 ffff pci express* port 8 pci expr ess* root port 8 i/oxapic enable (pae) set ffc0 0000h?ffc7 ffffh ff80 0000h?ff87 ffffh lpc or spi (or pci) 2 bit 8 in bios decode enable register is set ffc8 0000h?ffcf ffffh ff88 0000h?ff8f ffffh lpc or spi (or pci) 2 bit 9 in bios decode enable register is set ffd0 0000h?ffd7 ffffh ff90 0000h?ff97 ffffh lpc or spi (or pci) 2 bit 10 in bios decode en able register is set ffd8 0000h?ffdf ffffh ff98 0000h?ff9f ffffh lpc or spi (or pci) 2 bit 11 in bios decode en able register is set ffe0 000h?ffe7 ffffh ffa0 0000h?ffa7 ffffh lpc or spi (or pci) 2 bit 12 in bios decode en able register is set ffe8 0000h?ffef ffffh ffa8 0000h?ffaf ffffh lpc or spi (or pci) 3 bit 13 in bios decode en able register is set
register and memory mapping 372 datasheet fff0 0000h?fff7 ffffh ffb0 0000h?ffb7 ffffh lpc or spi (or pci)2 bit 14 in bios decode enable register is set fff8 0000h?ffff ffffh ffb8 0000h?ffbf ffffh lpc or spi (or pci)2 always enabled. the top two 64 kb blocks of this range can be swapped, as described in section 9.4.1 . ff70 0000h?ff7f ffffh ff30 0000h?ff3f ffffh lpc or spi (or pci)2 bit 3 in bios decode enable register is set ff60 0000h?ff6f ffffh ff20 0000h?ff2f ffffh lpc or spi (or pci)2 bit 2 in bios decode enable register is set ff50 0000h?ff5f ffffh ff10 0000h?ff1f ffffh lpc or spi (or pci)2 bit 1 in bios decode enable register is set ff40 0000h?ff4f ffffh ff00 0000h?ff0f ffffh lpc or spi (or pci)2 bit 0 in bios decode enable register is set 128 kb anywhere in 4 gb range integrated lan controller enable using bar in device 25:function 0 (integrated lan controller mbara) 4 kb anywhere in 4 gb range integrated lan controller enable using bar in device 25:function 0 (integrated lan controller mbarb) 1 kb anywhere in 4 gb range usb ehci controller #11 enable using standard pc i mechanism (device 29, function 0) 1 kb anywhere in 4 gb range usb ehci controller #21 enable using standard pc i mechanism (device 26, function 0) 16 kb anywhere in 64-bit addressing space intel ? high definition audio host controller enable using standard pc i mechanism (device 27, function 0) fed0 x000h?fed0 x3ffh high precision event timers 1 bios determines the ?fixed? location which is one of four, 1-kb ranges where x (in the first column) is 0h, 1h, 2h, or 3h. fed4 0000h?fed4 ffffh tpm on lpc none memory base/limit anywhere in 4 gb range pci bridge enable via standard pc i mechanism (device 30: function 0) prefetchable memory base/ limit anywhere in 64-bit address range pci bridge enable via standard pc i mechanism (device 30: function 0) 64 kb anywhere in 4 gb range lpc lpc generic memory rang e. enable via setting bit[0] of the lpc generi c memory range register (d31:f0:offset 98h). 32 bytes anywhere in 64-bit address range smbus enable via standard pc i mechanism (device 31: function 3) 2 kb anywhere above 64 kb to 4 gb range sata host controller #1 ahci memory-mapped re gisters. enable via standard pci mechanism (device 31: function 2) memory base/limit anywhere in 4 gb range pci express root ports 1-8 enable via standard pc i mechanism (device 28: function 0-7) prefetchable memory base/ limit anywhere in 64-bit address range pci express root ports 1-8 enable via standard pc i mechanism (device 28: function 0-7) table 9-4. memory decode ranges from processor perspect ive (sheet 2 of 3) memory range target dependency/comments
datasheet 373 register and memory mapping notes: 1. software must not attempt locks to memory mapped i/o ranges for usb ehci or high precision event timers. if attempted, the lock is not honored, which means potential deadlock conditions may occur. 2. pci is the target when the boot bios destination selection bits are set to 10b (chipset config registers:offset 3401 bits 11:10). when pci selected, the firmware hub decode enable bits have no effect. 9.4.1 boot-block update scheme the pch supports a ?top-block swap? mode that has the pch swap the top block in the fwh or spi flash (the boot block) with anothe r location. this allows for safe update of the boot block (even if a power failure occurs ). when the ?top swap? enable bit is set, the pch will invert a16 for cycles going to the upper two 64 kb blocks in the fwh or appropriate address lines as selected in boot block size (boot_block_size) soft strap for spi. specifically for fhw, in this mode accesses to ffff_0000h?ffff_ffffh are directed to fffe_0000h?fffe_ffffh and vice versa. when the top swap enable bit is 0, the pch will not invert a16. specifically for spi, in this mode the ?top-b lock swap? behavior is as described below. when the top swap enable bit is 0, the pch will not invert any address bit. 4 kb anywhere in 64-bit address range thermal reporting enable via standard pc i mechanism (device 31: function 6 tbar/tbarh) 4 kb anywhere in 64-bit address range thermal reporting enable via standard pc i mechanism (device 31: function 6 tbarb/tbarbh) 16 bytes anywhere in 64-bit address range intel ? mei #1, #2 enable via standard pc i mechanism (device 22: function 1:0) 4 kb anywhere in 4 gb range kt enable via standard pc i mechanism (device 22: function 3) 16 kb anywhere in 4 gb range root complex register block (rcrb) enable via setting bit[0] of the root complex base address register (d31:f0:offset f0h). table 9-4. memory decode ranges from processor perspective (sheet 3 of 3) memory range target dependency/comments table 9-5. spi mode address swapping boot_block_size value accesses to being directed to 000 (64 kb) ffff_0000h?ffff_ffffh fffe_0000h?fffe_ffffh and vice versa 001 (128 kb) fffe_0000h?ffff_ffffh fffc_0000h?fffd_ffffh and vice versa 010 (256 kb) fffc_0000h?ffff_ffffh fff8_0000h?fffb_ffffh and vice versa 011 (512 kb) fff8_0000h?ffff_ffffh fff0_0000h?fff7_ffffh and vice versa 100 (1 mb) fff0_0000h?ffff_ffffh ffe0_0000h?ffef_ffffh and vice versa 101?111 reserved reserved
register and memory mapping 374 datasheet this bit is automatically set to 0 by rtcrst#, but not by pltrst#. the scheme is based on the concept that the top block is reserved as the ?boot? block, and the block immediately below the top bl ock is reserved for doing boot-block updates. the algorithm is: 1. software copies the top block to the block immediately below the top 2. software checks that the copied block is correct. this could be done by performing a checksum calculation. 3. software sets the top swap bit. this will invert the appropriate address bits for the cycles going to the fwh or spi. 4. software erases the top block 5. software writes the new top block 6. software checks the new top block 7. software clears the top swap bit if a power failure occurs at any point after st ep 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. this is because the top swap bit is backed in the rtc well. note: the top-block swap mode may be forced by an external strapping option (see section 2.27 ). when top-block swap mode is forced in this manner, the top swap bit cannot be cleared by software. a re-boot with the strap removed will be required to exit a forced top-block swap mode. note: top-block swap mode only affects accesses to the firmware hub space, not feature space for fwh. note: the top-block swap mode has no effect on accesses below fffe_0000h for fwh.
datasheet 375 chipset configuration registers 10 chipset configuration registers this section describes all registers and base functionality that is related to chipset configuration and not a specific interface (s uch as lpc, usb, or pci express*). it contains the root complex register block that describes the behavior of the upstream internal link. this block is mapped into memory space, using the root complex base address (rcba) register of the pci-to-lpc bridge. accesses in this space must be limited to 32 bit (dw) quantities. burst accesses are not allowed. all chipset configuration registers are located in the core well unless otherwise indicated. 10.1 chipset configuration registers (memory space) note: address locations that are not shown should be treated as reserved (see section 9.2 for details). table 10-1. chipset configurat ion register memory map (mem ory space) (sheet 1 of 2) offset mnemonic register name default attribute 0050h?0053h cir0 chipset initialization register 0 00000000h r/wl 0400h?0403 rpc root port configuration 0000000yh r/w, ro 0404h?0407h rpfn root port function number and hide for pci express root ports 76543210h r/wo, ro 0408h?040b flrstat function level reset pending status summary 00000000h ro 1e00h?1e03h trsr trap status register 00000000h r/wc, ro 1e10h?1e17h trcr trapped cycle register 0000000000000000h ro 1e18h?1e1fh twdr trapped write data register 0000000000000000h ro 1e80h?1e87h iotr0 i/o trap register 0 0000000000000000h r/w 1e88h?1e8fh iotr1 i/o trap register 1 0000000000000000h r/w 1e90h?1e97h iotr2 i/o trap register 2 0000000000000000h r/w 1e98h?1e9fh iotr3 i/o trap register 3 0000000000000000h r/w 2014h?2017h v0ctl virtual channel 0 resource control 80000011h r/wl, ro 201ah?201bh v0sts virtual channel 0 resource status 0000h ro 2020h?2023h v1ctl virtual channel 1 resource control 00000000h r/w, ro, r/wl 2026h?2027h v1sts virtual channel 1 resource status 0000h ro 20ach?20afh rec root error command 0000h r/w 21a4h?21a7h lcap link capabilities 00012c42h ro, r/wo 21a8h?21a9h lctl link control 0000h r/w 21aah?21abh lsts link status 0042h ro 21b0h?21b1h dlctl2 dmi link control 2 register 0001h r/w, ro
chipset configuration registers 376 datasheet 2234h?2327h dmic dmi control 00000000h r/w, ro 3000h?3000h tctl tco configuration 00h r/w 3100h?3103h d31ip device 31 interrupt pin 03243200h r/w, ro 3104h?3107h d30ip device 30 interrupt pin 00000000h ro 3108h?310bh d29ip device 29 interrupt pin 10004321h r/w 310ch?310fh d28ip device 28 interrupt pin 00214321h r/w 3110h?3113h d27ip device 27 interrupt pin 00000001h r/w 3114h?3117h d26ip device 26 interrupt pin 30000321h r/w 3118h?311bh d25ip device 25 interrupt pin 00000001h r/w 3124h?3127h d22ip device 22 interrupt pin 00000001h r/w 3140h?3141h d31ir device 31 interrupt route 3210h r/w 3144h?3145h d29ir device 29 interrupt route 3210h r/w 3146h?3147h d28ir device 28 interrupt route 3210h r/w 3148h?3149h d27ir device 27 interrupt route 3210h r/w 314ch?314dh d26ir device 26 interrupt route 3210h r/w 3150h?3151h d25ir device 25 interrupt route 3210h r/w 315ch?315dh d22ir device 22 interrupt route 3210h r/w 31feh?31ffh oic other interrupt control 0000h r/w 3310h?3313h prsts power and reset status 03000000h ro, r/wc 3318h?331bh pm_cfg power management configuration 00000000h r/w 332ch?332fh deep_s4_pol deep s4/s5 from s4 power policies 00000000h r/w 3330h?3333h deep_s5_pol deep s4/s5 from s5 power policies 00000000h r/w 33c8h?33cbh pmsync_cfg pmsync configuration 00000000h r/w 3400h?3403h rc rtc configuration 00000000h r/w, r/wlo 3404h?3407h hptc high precision timer configuration 00000000h r/w 3410h?3413h gcs general control and status 000000yy0h r/w, r/wlo 3414h?3414h buc backed up control 00h r/w 3418h?341bh fd function disable 00000000h r/w 341ch?341fh cg clock gating 00000000h r/w 3420h?3420h fdsw function disable sus well 00h r/w 3424h?3425h dispbdf display bus, device and function initialization 0010h r/w 3428h?342bh fd2 function disable 2 00000000h r/w 3590h?3594h miscctl miscellaneous control register 00000000h r/w 35a0h?35a3h usbocm1 usb overcurrent map register 1 00000000h r/wo 35a4h?35a7h usbocm2 usb overcurrent map register 2 00000000h r/wo 35b0h?35b3h rmhwkctl usb rate matching hub wake control 00000000h r/wo table 10-1. chipset configuration register memory map (memory sp ace) (sheet 2 of 2) offset mnemonic register name default attribute
datasheet 377 chipset configuration registers 10.1.1 cir0chipset init ialization register 0 offset address: 0050?0053h attribute: r/wl default value: 00000000h size: 32-bit 10.1.2 rpcroot port configuration register offset address: 0400?0403h attribute: r/w, ro default value: 0000000yh (y = 00xxb) size: 32-bit bit description 31 tc lock-down (tclockdn) ? r/wl. when set to 1, certain dmi configuration registers are locked down by this and cannot be written. once set to 1, this bit can only be cleared by a pltrst#. 30:0 cir0 field 0 ? r/wl. bios must set this fiel d. bits locked by tclockdn. bit description 31:12 reserved 11 gbe over pcie root port enable (gbepcierpen) ? r/w. 0 = gbe mac/phy communication is not enabled over pci express. 1 = the pci express port selected by the gbepcieportsel register will be used for gbe mac/phy over pci express communication the default value for this register is set by the gbe_pcie_en soft strap. note: gbe and pcie will use the output of this register and not the soft strap 10:8 gbe over pcie root port select (gbepcierpsel) ? r/w . if the gbepcierpen is a ?1?, then this regi ster determines which port is used for gbe mac/phy communication over pci express. this register is set by soft strap and is writable to support separate phy on motherboard and docking station. 111 = port 8 (lane 7) 110 = port 7 (lane 6) 101 = port 6 (lane 5) 100 = port 5 (lane 4) 101 = port 4 (lane 3) 010 = port 3 (lane 2) 001 = port 2 (lane 1) 000 = port 1 (lane 0) the default value for this re gister is set by the gbe_pcieportsel[2:0] soft strap. note: gbe and pcie will use the output of this register and not the soft strap 7:4 reserved 3:2 port configuration2 (pc2) ? ro. this controls how th e pci bridges are organized in various modes of operation for ports 5?8. for the following mappings, if a port is not shown, it is considered a x1 port with no connection. this bit is set by the pciepcs2[1:0] soft strap. 11 = 1 x4, port 5 (x4) 10 = 2 x2, port 5 (x2), port 7 (x2) 01 = 1x2 and 2x1s, port 5 (x2), port 7 (x1) and port 8(x1) 00 = 4 x1s, port 5 (x1), port 6 (x1), port 7 (x1) and port 8 (x1)
chipset configuration registers 378 datasheet 10.1.3 rpfnroot port function number and hide for pci express* root ports register offset address: 0404?0407h attribute: r/wo, ro default value: 76543210h size: 32-bit for the pci express root ports, the assignment of a function number to a root port is not fixed. bios may re-assign the function numbers on a port by port basis. this capability will allow bios to disable/hide any root port and still have functions 0 thru n- 1 where n is the total number of enabled root ports. port numbers will remain fixed to a physical root port. the existing root port function disable registers operate on physical ports (not functions). port configuration (1x4, 4x1, etc.) is not affected by the logical function number assignment and is associated with physical ports. 1:0 port configuration (pc) ? ro. this controls how the pci bridges are organized in various modes of operation for ports 1?4. for the following mappings, if a port is not shown, it is considered a x1 port with no connection. these bits are set by the pciepcs1[1:0] soft strap. 11 = 1 x4, port 1 (x4) 10 = 2 x2, port 1 (x2), port 3 (x2) 01 = 1x2 and 2x1s, port 1 (x2), port 3 (x1) and port 4 (x1) 00 = 4 x1s, port 1 (x1), port 2 (x1), port 3 (x1) and port 4 (x1) bit description bit description 31 root port 8 config hide (rp8ch) ? r/w. this bit is used to hide the root port and any devices behind it fro m being discovered by the os. when set to 1, the root port will not claim any downstre am configuration transactions. 30:28 root port 8 function number (rp8fn) ? r/wo. these bits set the function number for pci express root port 8. this root port function number must be a unique value from the other r oot port function numbers 27 root port 7 config hide (rp7ch) ? r/w. this bit is used to hide the root port and any devices behind it fro m being discovered by the os. when set to 1, the root port will not claim any downstre am configuration transactions. 26:24 root port 7 function number (rp7fn) ? r/wo. these bits set the function number for pci express root port 7. this root port function number must be a unique value from the other r oot port function numbers 23 root port 6 config hide (rp6ch) ? r/w. this bit is used to hide the root port and any devices behind it fro m being discovered by the os. when set to 1, the root port will not claim any downstre am configuration transactions. 22:20 root port 6 function number (rp6fn) ? r/wo. these bits set the function number for pci express root port 6. this root port function number must be a unique value from the other r oot port function numbers 19 root port 5 config hide (rp5ch) ? r/w. this bit is used to hide the root port and any devices behind it fro m being discovered by the os. when set to 1, the root port will not claim any downstre am configuration transactions.
datasheet 379 chipset configuration registers 10.1.4 flrstatfunction level re set pending status register offset address: 0408?040bh attribute: ro default value: 00000000h size: 32-bit 18:16 root port 5 function number (rp5fn) ? r/wo. these bits set the function number for pci express root port 5. this root port function number must be a unique value from the other r oot port function numbers 15 root port 4 config hide (rp4ch) ? r/w. this bit is used to hide the root port and any devices behind it from being discove red by the os. when set to 1, the root port will not claim any downstre am configuration transactions. 14:12 root port 4 function number (rp4fn) ? r/wo. these bits set the function number for pci express root port 4. this root port function number must be a unique value from the other r oot port function numbers 11 root port 3 config hide (rp3ch) ? r/w. this bit is used to hide the root port and any devices behind it from being discove red by the os. when set to 1, the root port will not claim any downstre am configuration transactions. 10:8 root port 3 function number (rp3fn) ? r/wo. these bits set the function number for pci express root port 3. this root port function number must be a unique value from the other r oot port function numbers 7 root port 2 config hide (rp2ch) ? r/w. this bit is used to hide the root port and any devices behind it from being discove red by the os. when set to 1, the root port will not claim any downstre am configuration transactions. 6:4 root port 2 function number (rp2fn) ? r/wo. these bits set the function number for pci express root port 2. this root port function number must be a unique value from the other r oot port function numbers 3 root port 1 config hide (rp1ch) ? r/w. this bit is used to hide the root port and any devices behind it from being discove red by the os. when set to 1, the root port will not claim any downstre am configuration transactions. 2:0 root port 1 function number (rp1fn) ? r/wo. these bits set the function number for pci express root port 1. this root port function number must be a unique value from the other r oot port function numbers bit description bit description 31:17 reserved 16 flr pending status for d29:f0, ehci #1 ? ro. 0 = function level reset is not pending. 1 = function level reset is pending. 15 flr pending status for d26:f0, ehci #2 ? ro. 0 = function level reset is not pending. 1 = function level reset is pending. 10:9 reserved 8 flr pending status for d26:f0, ehci#2 ? ro. 0 = function level reset is not pending. 1 = function level reset is pending. 7:0 reserved
chipset configuration registers 380 datasheet 10.1.5 trsrtrap status register offset address: 1e00?1e03h attribute: r/wc, ro default value: 00000000h size: 32-bit 10.1.6 trcrtrapped cycle register offset address: 1e10?1e17h attribute: ro default value: 0000000000000000h size: 64-bit this register saves information about the i/o cycle that was trapped and generated the smi# for software to read. bit description 31:4 reserved 3:0 cycle trap smi# status (ctss) ? r/wc. these bits are set by hardware when the corresponding cycle trap register is enable d and a matching cycle is received (and trapped). these bits are or?ed together to create a single status bit in the power management register space. note that the smi# and trapping must be enabled in order to set these bits. these bits are set before the completion is generated for the trapped cycle, thereby ensuring that the processor can enter the smi# handler wh en the instruction completes. each status bit is cleared by writing a 1 to th e corresponding bit location in this register. bit description 63:25 reserved 24 read/write# (rwi) ? ro. 0 = trapped cycle was a write cycle. 1 = trapped cycle was a read cycle. 23:20 reserved 19:16 active-high byte enables (ahbe) ? ro. this is the dword-aligned byte enables associated with the trapped cycle. a 1 in any bit location indicates that the corresponding byte is enabled in the cycle. 15:2 trapped i/o address (tioa) ? ro. this is the dword-aligned address of the trapped cycle. 1:0 reserved
datasheet 381 chipset configuration registers 10.1.7 twdrtrapped write data register offset address: 1e18?1e1fh attribute: ro default value: 0000000000000000h size: 64-bit this register saves the data from i/o write cycles that are trapped for software to read. 10.1.8 iotrni/o tr ap register (0C3) offset address: 1e80?1e87h register 0 attribute: r/w 1e88?1e8fh register 1 1e90?1e97h register 2 1e98?1e9fh register 3 default value: 0000000000000000h size: 64-bit these registers are used to specify the set of i/o cycles to be trapped and to enable this functionality. bit description 63:32 reserved 31:0 trapped i/o data (tiod) ? ro. dword of i/o write data. this field is undefined after trapping a read cycle. bit description 63:50 reserved 49 read/write mask (rwm) ? r/w. 0 = the cycle must match the type specified in bit 48. 1 = trapping logic will operate on both read and write cycles. 48 read/write# (rwio) ? r/w. 0 = write 1 = read note: the value in this field does not matter if bit 49 is set. 47:40 reserved 39:36 byte enable mask (bem) ? r/w. a 1 in any bit position indicates that any value in the corresponding byte enable bit in a received cycle will be treated as a match. the corresponding bit in the byte en ables field, below, is ignored. 35:32 byte enables (tbe) ? r/w. active-high dword-aligned byte enables. 31:24 reserved 23:18 address[7:2] mask (adma) ? r/w. a 1 in any bit position indicates that any value in the corresponding address bit in a receiv ed cycle will be treated as a match. the corresponding bit in the addres s field, below, is ignored. the mask is only provided for the lower 6 bits of the dword address, al lowing for traps on address ranges up to 256 bytes in size. 17:16 reserved 15:2 i/o address[15:2] (ioad) ? r/w. dword-aligned address 1 reserved 0 trap and smi# enable (trse) ? r/w. 0 = trapping and smi# logic disabled. 1 = the trapping logic specified in this register is enabled.
chipset configuration registers 382 datasheet 10.1.9 v0ctlvirtual channel 0 resource control register offset address: 2014?2017h attribute: r/wl, ro default value: 80000011h size: 32-bit 10.1.10 v0stsvirtual channel 0 resource status register offset address: 201a?201bh attribute: ro default value: 0000h size: 16-bit bit description 31 virtual channel enable (en) ? ro. always set to 1. vc 0 is always enabled and cannot be disabled. 30:27 reserved 26:24 virtual channel identifier (id) ? ro. indicates the id to use for this virtual channel. 23:16 reserved 15:10 extended tc/vc map (etvm) ? r/wl. defines the upper 8-bits of the vc0 16-bit tc/vc mapping registers. these registers us e the pci express reserved tc[3] traffic class bit. these bits are locked if the tclockdn bit (rcba+0050h:bit 31) is set. 9:7 reserved 6:1 transaction class / virtual channel map (tvm) ? r/wl. indicates which transaction classes are mapped to this virt ual channel. when a bit is set, this transaction class is mapped to the virtual channel. these bits are locked if the tclockdn bit (rcba+0050h:bit 31) is set. 0 reserved bit description 15:2 reserved 1 vc negotiation pending (np) ? ro. when set, this bit indicates the virtual channel is still being nego tiated with ingress ports. 0 reserved
datasheet 383 chipset configuration registers 10.1.11 v1ctlvirtual channel 1 resource control register offset address: 2020?2023h attribute: r/w, ro, r/wl default value: 00000000h size: 32-bit 10.1.12 v1stsvirtual channel 1 resource status register offset address: 2026?2027h attribute: ro default value: 0000h size: 16-bit bit description 31 virtual channel enable (en) ? r/w. enables the vc when set. disables the vc when cleared. 30:28 reserved 27:24 virtual channel identifier (id) ? r/w. indicates the id to use for this virtual channel. 23:16 reserved 15:10 extended tc/vc map (etvm) ? r/wl. defines the upper 8-bits of the vc0 16-bit tc/vc mapping registers. these registers use the pci express reserved tc[3] traffic class bit. these bits are locked if the tclockdn bit (rcba+0050h:bit 31) is set. 9:8 reserved 7:1 transaction class / virtual channel map (tvm) ? r/wl. indicates which transaction classes are mapped to this virtual channel. when a bit is set, this transaction class is mapped to the virtual channel. these bits are locked if the tclockdn bit (rcba+0050h:bit 31) is set. 0 reserved bit description 15:2 reserved 1 vc negotiation pending (np) ? ro. when set, this bit indicates the virtual channel is still being nego tiated with ingress ports. 0 reserved
chipset configuration registers 384 datasheet 10.1.13 recroot error command register offset address: 20ac?20afh attribute: r/w default value: 0000h size: 32-bit 10.1.14 lcaplink capa bilities register offset address: 21a4?21a7h attribute: r/wo, ro default value: 00012c42h size: 32-bit bit description 31 drop poisoned downstream packets (dpdp) ? r/w. determines how downstream packets on dmi are handled that are received with the ep field set, indicating poisoned data: 0 = packets are forwarded downstream without forcing the ut field set. 1 = this packet and all subseque nt packets with data received on dmi for any vc will have their unsupported transaction (ut) field set causing them to master abort downstream. packets without data such as memory, i/o and config read requests are allowed to proceed. 30:0 reserved bit description 31:18 reserved 17:15 l1 exit latency (el1) ? r/wo. indicates that the exit latency is 2 s to 4 s. 14:12 l0s exit latency (el0) ? r/w. this field indicates th at exit latency is 128 ns to less than 256 ns. 11:10 active state link pm support (apms) ?r/w. indicates the level of aspm support on dmi. 00 = disabled 01 = l0s entry supported 10 = reserved 11 = l0s and l1 entry supported 9:4 maximum link width (mlw) ? ro. indicates the maximum link width is 4 ports. 3:0 maximum link speed (mls) ? ro. indicates the link speed is 5.0 gb/s.
datasheet 385 chipset configuration registers 10.1.15 lctllink control register offset address: 21a8?21a9h attribute: r/w default value: 0000h size: 16-bit 10.1.16 lstslink status register offset address: 21aa?21abh attribute: ro default value: 0042h size: 16-bit 10.1.17 dlctl2dmi link control 2 register offset address: 21b0?21b1h attribute: r/w, ro default value: 0001h size: 16-bit bit description 15:8 reserved 7 extended synch (es) ? r/w. when set, forces ex tended transmission of fts ordered sets when exiting l0s prior to entering l0 and extra ts1 sequences at exit from l1 prior to entering l0. 6:2 reserved 1:0 active state link pm control (aspm) ? r/w. indicates whether dmi should enter l0s, l1, or both. 00 = disabled 01 = l0s entry enabled 10 = l1 entry enabled 11 = l0s and l1 entry enabled bit description 15:10 reserved 9:4 negotiated link width (nlw) ? ro. negotiated link width is x4 (000100b). 3:0 current link speed (ls) ? ro. 0001b = 2.5 gb/s 0010b = 5.0 gb/s bit description 31:4 reserved 3:0 dlctl2 field 1 ? r/w. bios must set these bits.
chipset configuration registers 386 datasheet 10.1.18 dmicdmi control register offset address: 2234?2237h attribute: r/w default value: 00000000h size: 32-bit 10.1.19 tctltco configuration register offset address: 3000?3000h attribute: r/w default value: 00h size: 8-bit bit description 31:2 reserved 1:0 dmi clock gate enable (dmicgen) ? r/w. bios must program this field to 11b. bit description 7 tco irq enable (ie) ? r/w. 0 = tco irq is disabled. 1 = tco irq is enabled, as sele cted by the tco_irq_sel field. 6:3 reserved 2:0 tco irq select (is) ? r/w. specifies on which irq the tco will internally appear. if not using the apic, the tco interrupt must be routed to irq9?11, and that interrupt is not sharable with the serirq stream, but is shar eable with other pci interrupts. if using the apic, the tco interrupt can also be mapped to irq20?23, and can be shared with other interrupt. 000 = irq 9 001 = irq 10 010 = irq 11 011 = reserved 100 = irq 20 (only if apic enabled) 101 = irq 21 (only if apic enabled) 110 = irq 22 (only if apic enabled) 111 = irq 23 (only if apic enabled) when setting the these bits, the ie bit should be cleared to prevent glitching. when the interrupt is mapped to apic interrupts 9, 10, or 11, the apic should be programmed for active-high reception. when the interrupt is mapped to apic interrupts 20 through 23, the apic should be programmed for active-low reception.
datasheet 387 chipset configuration registers 10.1.20 d31ipdevice 31 in terrupt pi n register offset address: 3100?3103h attribute: r/w, ro default value: 03243200h size: 32-bit bit description 31:28 reserved 27:24 thermal throttle pin (ttip) ? r/w. indicates which pin the thermal throttle controller drives as its interrupt 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?fh = reserved 23:20 sata pin 2 (sip2) ? r/w. indicates which pin the sa ta controller 2 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?fh = reserved 19:16 reserved 15:12 smbus pin (smip) ? r/w. indicates which pin the smbus controller drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?fh = reserved 11:8 sata pin (sip) ? r/w. indicates which pin the sata controller drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?fh = reserved 7:4 reserved 3:0 lpc bridge pin (lip) ? ro. currently, the lp c bridge does not generate an interrupt, so this field is read-only and 0.
chipset configuration registers 388 datasheet 10.1.21 d30ipdevice 30 in terrupt pin register offset address: 3104?3107h attribute: ro default value: 00000000h size: 32-bit 10.1.22 d29ipdevice 29 in terrupt pin register offset address: 3108?310bh attribute: r/w default value: 10004321h size: 32-bit 10.1.23 d28ipdevice 28 in terrupt pin register offset address: 310c?310fh attribute: r/w default value: 00214321h size: 32-bit bit description 31:4 reserved 3:0 pci bridge pin (pip) ? ro. currently, the pc i bridge does not generate an interrupt, so this field is read-only and 0. bit description 31:4 reserved 3:0 ehci #1 pin (e1p) ? r/w. indicates which pin the eh ci controller #1 drives as its interrupt, if controller exists. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved note: ehci controller #1 is mappe d to device 29 function 0. bit description 31:28 pci express* #8 pin (p8ip) ? r/w. indicates which pin the pci express* port #8 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 27:24 pci express #7 pin (p7ip) ? r/w. indicates which pi n the pci express port #7 drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved
datasheet 389 chipset configuration registers 23:20 pci express* #6 pin (p6ip) ? r/w. indicates which pin the pci express* port #6 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 19:16 pci express #5 pin (p5ip) ? r/w. indicates which pin the pci express port #5 drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved 15:12 pci express #4 pin (p4ip) ? r/w. indicates which pin the pci express* port #4 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# 4h = intd# (default) 5h?7h = reserved 11:8 pci express #3 pin (p3ip) ? r/w. indicates which pin the pci express port #3 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# (default) 4h = intd# 5h?7h = reserved 7:4 pci express #2 pin (p2ip) ? r/w. indicates which pin the pci express port #2 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 3:0 pci express #1 pin (p1ip) ? r/w. indicates which pin the pci express port #1 drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved bit description
chipset configuration registers 390 datasheet 10.1.24 d27ipdevice 27 in terrupt pin register offset address: 3110?3113h attribute: r/w default value: 00000001h size: 32-bit 10.1.25 d26ipdevice 26 in terrupt pin register offset address: 3114?3117h attribute: r/w default value: 30000321h size: 32-bit 10.1.26 d25ipdevice 25 in terrupt pin register offset address: 3118?311bh attribute: r/w default value: 00000001h size: 32-bit bit description 31:4 reserved 3:0 intel ? high definition audio pin (zip) ? r/w. indicates which pin the intel ? high definition audio controller drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserved bit description 31:4 reserved 3:0 ehci #2 pin (e2p) ? r/w. indicates which pin ehci controller #2 drives as its interrupt, if controller exists. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserve note: ehci controller #2 is mappe d to device 26 function 0. bit description 31:4 reserved 3:0 gbe lan pin (lip) ? r/w. indicates which pin the internal gbe lan controller drives as its interrupt 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserved
datasheet 391 chipset configuration registers 10.1.27 d22ipdevice 22 in terrupt pi n register offset address: 3124?3127h attribute: r/w default value: 00000001h size: 32-bit bit description 31:16 reserved 15:12 kt pin (ktip) ? r/w. indicates which pin the keyboard text pci functionality drives as its interrupt 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserved 11:8 ide-r pin (iderip) ? r/w. indicates which pin the ide redirect pci functionality drives as its interrupt 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserved 7:4 intel ? mei #2 pin (mei2ip) ? r/w. indicates which pin the management engine interface #2 drives as its interrupt 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserved 3:0 intel ? mei #1 pin (mei1ip) ? r/w. indicates which pin the management engine interface controller #1 drives as its interrupt 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# 4h = intd# 5h?fh = reserved
chipset configuration registers 392 datasheet 10.1.28 d31irdevice 31 in terrupt route register offset address: 3140?3141h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. indicates which ph ysical pin on the pch is connected to the intd# pin repo rted for device 31 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. indicates which ph ysical pin on the pch is connected to the intc# pin repo rted for device 31 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. indicates which ph ysical pin on the pch is connected to the intb# pin repo rted for device 31 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. indicates which ph ysical pin on the pch is connected to the inta# pin repo rted for device 31 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
datasheet 393 chipset configuration registers 10.1.29 d29irdevice 29 in terrupt route register offset address: 3144?3145h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. indicates which physical pin on the pch is connected to the intd# pin repo rted for device 29 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. indicates which ph ysical pin on the pch is connected to the intc# pin repo rted for device 29 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. indicates which ph ysical pin on the pch is connected to the intb# pin repo rted for device 29 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. indicates which ph ysical pin on the pch is connected to the inta# pin repo rted for device 29 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
chipset configuration registers 394 datasheet 10.1.30 d28irdevice 28 in terrupt route register offset address: 3146?3147h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. indicates which ph ysical pin on the pch is connected to the intd# pin repo rted for device 28 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. indicates which ph ysical pin on the pch is connected to the intc# pin repo rted for device 28 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. indicates which ph ysical pin on the pch is connected to the intb# pin repo rted for device 28 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. indicates which ph ysical pin on the pch is connected to the inta# pin repo rted for device 28 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
datasheet 395 chipset configuration registers 10.1.31 d27irdevice 27 in terrupt route register offset address: 3148?3149h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. indicates which physical pin on the pch is connected to the intd# pin repo rted for device 27 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. indicates which ph ysical pin on the pch is connected to the intc# pin repo rted for device 27 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. indicates which ph ysical pin on the pch is connected to the intb# pin repo rted for device 27 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. indicates which ph ysical pin on the pch is connected to the inta# pin repo rted for device 27 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
chipset configuration registers 396 datasheet 10.1.32 d26irdevice 26 in terrupt route register offset address: 314c?314dh attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) r/w. indicates which physical pin on the pch is connected to the intd# pin repo rted for device 26 functions: 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. indicates which ph ysical pin on the pch is connected to the intc# pin repo rted for device 26 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. indicates which ph ysical pin on the pch is connected to the intb# pin repo rted for device 26 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. indicates which ph ysical pin on the pch is connected to the inta# pin repo rted for device 26 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
datasheet 397 chipset configuration registers 10.1.33 d25irdevice 25 in terrupt route register offset address: 3150?3151h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr): ? r/w. indicates which ph ysical pin on the pch is connected to the intd# pin repo rted for device 25 functions: 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. indicates which ph ysical pin on the pch is connected to the intc# pin repo rted for device 25 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. indicates which ph ysical pin on the pch is connected to the intb# pin repo rted for device 25 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. indicates which ph ysical pin on the pch is connected to the inta# pin repo rted for device 25 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
chipset configuration registers 398 datasheet 10.1.34 d22irdevice 22 in terrupt route register offset address: 315c?315dh attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr): ? r/w. indicates which ph ysical pin on the pch is connected to the intd# pin repo rted for device 22 functions: 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. indicates which ph ysical pin on the pch is connected to the intc# pin repo rted for device 22 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. indicates which ph ysical pin on the pch is connected to the intb# pin repo rted for device 22 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. indicates which ph ysical pin on the pch is connected to the inta# pin repo rted for device 22 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
datasheet 399 chipset configuration registers 10.1.35 oicother interr upt control register offset address: 31fe?31ffh attribute: r/w default value: 0000h size: 16-bit note: fec10000h?fec3ffffh is allocated to pcie when i/oxapic enable (pae) bit is set. bit description 15:10 reserved 9 coprocessor error enable (cen) ? r/w. 0 = ferr# will not generate irq13 nor ignne#. 1 = if ferr# is low, the pch generates irq13 internally and holds it until an i/o port f0h write. it will also drive ignne# active. 8 apic enable (aen) ? r/w. 0 = the internal ioxapic is disabled. 1 = enables the internal ioxa pic and its address decode. note: software should read this register af ter modifying apic enable bit prior to access to the ioxapic address range. 7:0 apic range select (asel) ? r/w. these bits define address bits 19:12 for the ioxapic range. the default value of 00h enab les compatibility with prior pch products as an initial value. this value must not be changed unless the ioxapic enable bit is cleared.
chipset configuration registers 400 datasheet 10.1.36 prstspower and reset status register offset address: 3310?3313h attribute: ro, r/wc default value: 03000000h size: 32-bit bit description 31:16 reserved 15 power management watchdog timer ? r/wc. this bit is set when the power management watchdog time r causes a global reset. 14:7 reserved 6 intel ? management engine watchdog timer status ? r/wc. this bit is set when the intel management engine watchdog timer causes a global reset. 5 wake on lan override wake status (wol_ovr_wk_sts) ? r/wc. this bit gets set when all of the following conditions are met: ? integrated lan signals a power management event ? the system is not in s0 ? the ?wol enable override? bit is set in configuration space. bios can read this status bit to determine this wake source. software clears this bit by writing a 1 to it. 4 reserved 3 intel me host power down (me_host_pwrdn) ? r/wc. this bit is set when the intel management engine generates a host reset with power down. 2 intel me host reset warm status (me_hrst_warm_sts) ? r/wc. this bit is set when the intel management engine gene rates a host reset without power cycling. software clears this bit by wr iting a 1 to this bit position. 1 intel me host reset cold status (me_hrst_cold_sts) ? r/wc. this bit is set when the intel management engine genera tes a host reset with power cycling. software clears this bit by wr iting a 1 to this bit position. 0 intel me wake status (me_wake_sts) ? r/wc. this bit is set when the intel management engine generates a non-maskable wake event, and is not affected by any other enable bit. when this bit is set, the host power management logic wakes to s0.
datasheet 401 chipset configuration registers 10.1.37 pm_cfgpower manageme nt configuration register offset address: 3318?331bh attribute: r/w default value: 00000000h size: 32-bit bit description 31:27 reserved 26:24 pm_cfg field 1 r/w. bios must program this field to 101b. 23:22 reserved 21 rtc wake from deep s4/s5 disable (rtc_ds_wake_dis) ? r/w. when set, this bit disables rtc wakes from waking the system from deep s4/s5. this bit is reset by rtcrst#. 20 reserved 19:18 slp_sus# minimum assertion width (slp_sus_min_asst_wdth) ? r/w. this field indicates the minimum assert ion width of the slp_sus# signal to guarantee that the sus power supplies have been fully po wer cycled. this value may be modified per platform depending on power supply capacitance, board capacitance, power circuits, etc. valid values are: 11 = 4 seconds 10 = 1 second 01 = 500 ms 00 = 0 ms (that is, stretching disabled - default) these bits are cleared by rtcrst# assertion. notes: 1. this field is ro when the slp stre tching policy lock-down bit is set. 2. this field is ignored when exiting g3 or deep s4/s5 states if the ?disable slp stretching after sus well po wer up? bit is set. note th at unlike with all other slp_* pin stretching, this disable bi t only impacts slp_sus# stretching during g3 exit rather than both g3 and deep s4/s5 exit. slp_sus# stretching always applies to deep s4/s5 regardless of the disable bit. 3. for platforms that enable deep s4/s5, bios must program slp_sus# stretching to be greater than or equal to the largest stretching value on any other slp_* pin (slp_s3#, slp_s4#, or slp_a#). 17:16 slp_a# minimum assertion wi dth (slp_a_min_asst_wdth) ? r/w. this field indicates the minimum assertion width of the slp_a# signal to guarantee that the asw power supplies have been fully po wer cycled. this value may be modified per platform depending on power supply capacitance, board capacitance, power circuits, etc. valid values are: 11 = 2 seconds 10 = 98 ms 01 = 4 seconds 00 = 0 ms (that is, stretching disabled ? default) these bits are cleared by rtcrst# assertion. notes: 1. this field is ro when the slp stre tching policy lock-down bit is set. 2. this field is ignored when exiting g3 or deep s4/s5 states if the ?disable slp stretching after sus well power up? bit is set. 15:0 reserved
chipset configuration registers 402 datasheet 10.1.38 deep_s4_poldeep s4/s 5 from s4 power policies register offset address: 332c?332fh attribute: r/w default value: 00000000h size: 32-bit this register is in the rtc power well and is reset by rtcrst# assertion. 10.1.39 deep_s5_poldeep s4/s5 from s5 power policies register offset address: 3330?3333h attribute: r/w default value: 00000000h size: 32-bit this register is in the rtc power well and is reset by rtcrst# assertion. bit description 31:2 reserved 1 deep s4/s5 from s4 enable in dc mode (dps4_en_dc) ? r/w. a '1' in this bit enables the platform to ente r deep s4/s5 while operating in s4 on dc power (based on the ac_present pin value). 0 deep s4/s5 from s4 enable in ac mode (dps4_en_ac) ? r/w. a '1' in this bit enables the platform to enter deep s4/s5 while operating in s4 on ac power (based on the ac_present pin value). required to be programmed to 0 on mobile. bit description 31:16 reserved 15 deep s4/s5 from s5 enable in dc mode (dps5_en_dc) ? r/w. a '1' in this bit enables the platform to ente r deep s4/s5 while operating in s5 on dc power (based on the ac_present pin value). 14 deep s4/s5 from s5 enable in ac mode (dps5_en_ac) ? r/w. a '1' in this bit enables the platform to enter deep s4/s5 while operating in s5 on ac power (based on the ac_present pin value). required to be programmed to 0 on mobile. 13:0 reserved
datasheet 403 chipset configuration registers 10.1.40 pmsync_cfgpmsync configuration register offset address: 33c8?33cbh attribute: r/w default value: 00000000h size: 32-bit bit description 31:12 reserved 11 gpio_d pin selection (gpio_d_sel) ? r/w. there are two possible gpios that can be routed to the gpio_d pmsync state. this bit selects between them: 0 = gpio5 (default) 1 = gpio0 10 gpio_c pin selection (gpio_c_sel) ? r/w. there are two possible gpios that can be routed to the gpio_c pmsync state. this bit selects between them: 0 = gpio37 (default) 1 = gpio4 9 gpio_b pin selection (gpio_b_sel) ? r/w. there are two possible gpios that can be routed to the gpio_b pmsync state. this bit selects between them: 0 = gpio0 (default) 1 = gpio37 8 gpio_a pin selection (gpio_a_sel) ? r/w. there are two possible gpios that can be routed to the gpio_a pmsync state. this bit selects between them: 0 = gpio4 (default) 1 = gpio5 7:0 reserved
chipset configuration registers 404 datasheet 10.1.41 rcrtc configuration register offset address: 3400?3403h attribute: r/w, r/wlo default value: 00000000h size: 32-bit 10.1.42 hptchigh precision timer configuration register offset address: 3404?3407h attribute: r/w default value: 00000000h size: 32-bit bit description 31:5 reserved 4 upper 128 byte lock (ul) ? r/wlo. 0 = bytes not locked. 1 = bytes 38h?3fh in the upper 128-byte bank of rtc ram are locked and cannot be accessed. writes will be dr opped and reads will not re turn any ensured data. bit reset on system reset. 3 lower 128 byte lock (ll) ? r/wlo. 0 = bytes not locked. 1 = bytes 38h?3fh in the lower 128-byte bank of rtc ram are locked and cannot be accessed. writes will be dr opped and reads will not re turn any ensured data. bit reset on system reset. 2 upper 128 byte enable (ue) ? r/w. 0 = bytes locked. 1 = the upper 128-byte bank of rtc ram can be accessed. 1:0 reserved bit description 31:8 reserved 7 address enable (ae) ? r/w. 0 = address disabled. 1 = the pch will decode the high precisio n timer memory address range selected by bits 1:0 below. 6:2 reserved 1:0 address select (as) ? r/w. this 2-bit field selects 1 of 4 possible memory address ranges for the high precision time r functionality. the encodings are: 00 = fed0_0000h ? fed0_03ffh 01 = fed0_1000h ? fed0_13ffh 10 = fed0_2000h ? fed0_23ffh 11 = fed0_3000h ? fed0_33ffh
datasheet 405 chipset configuration registers 10.1.43 gcsgeneral contro l and status register offset address: 3410?3413h attribute: r/w, r/wlo default value: 00000yy0h (yy = xx0000x0b)size: 32-bit bit description 31:13 reserved 12 function level reset capability structure select (flrcssel) ? r/w. 0 = function level reset (flr) will utilize the standard capability structure with unique capability id assigned by pcisig. 1 = vendor specific capability structure is selected for flr. 11:10 boot bios straps (bbs) ? r/w. this field determines the destination of accesses to the bios memory range. the default values for these bits represent the strap values of gnt1#/gpio51 (bit 11) at the rising edge of pwrok and sata1gp/gpio19 (bit 10) at the rising edge of pwrok. when pci is selected, the top 16 mb of memory below 4 gb (ff00_0000h to ffff_ffffh) is accepted by the primary side of the pci p2p bridge and forwarded to the pci bus. this allows systems with co rrupted or unprogrammed flash to boot from a pci device. the pci-to-pci bridge memory space enable bit does not need to be set (nor any other bits) in order for these cycles to go to pc i. note that bios decode range bits and the other bios protection bits have no e ffect when pci is selected. this functionality is intend ed for debug/testing only. when spi or lpc is selected, the range that is decoded is further qualified by other configuration bits described in the respective sections. the value in this field can be overwritten by software as long as the bios interface lock-down (bit 0) is not set. note: booting to pci is intended for debug/ testing only. boot bios destination select to lpc/pci by functional strap or using boot bios destination bit will not affect spi accesses initiated by intel ? management engine or integrated gbe lan. 9 server error reporting mode (serm) ? r/w. 0 = the pch is the final target of all errors. the proces sor sends a messages to the pch for the purpose of generating nmi. 1 = the processor is the final target of all errors from pci express* and dmi. in this mode, if the pch detects a fatal, non-fata l, or correctable error on dmi or its downstream ports, it sends a message to the processor. if the pch receives an err_* message from the downstream po rt, it sends that message to the processor. 8:6 reserved 5 no reboot (nr) ? r/w. this bit is set when the ?no reboot? strap (spkr pin on the pch) is sampled high on pwrok. this bit may be set or cleared by software if the strap is sampled low but may not override the strap when it in dicates ?no reboot?. 0 = system will reboot upon the second timeout of the tco timer. 1 = the tco timer will count down and gene rate the smi# on th e first timeout, but will not reboot on the second timeout. bits 11:10 description 00b lpc 01b reserved 10b pci 11b spi
chipset configuration registers 406 datasheet 4 alternate access mode enable (ame) ? r/w. 0 = disabled. 1 = alternate access read only registers ca n be written, and writ e only registers can be read. before entering a low power st ate, several register s from powered down parts may need to be saved. in the majori ty of cases, this is not an issue, as registers have read and write paths. ho wever, several of the isa compatible registers are either read only or write only. to get data out of write-only registers, and to restore data into read-only registers, the pch implements an alternate access mode. for a list of these registers see section 5.13.9 . 3 shutdown policy select (sps) ? r/w. 0 = pch will drive init# in response to the shutdown vendor defined message (vdm). (default) 1 = pch will treat the shutdown vdm similar to receiving a cf9h i/o write with data value 06h, and will drive pltrst# active. 2 reserved page route (rpr) ? r/w. determines where to send the reserved page registers. these addresses are sent to pci or lpc for the purpose of generating post codes. the i/o addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8ch, 8dh, and 8eh. 0 = writes will be forwarded to lpc, shad owed within the pch, and reads will be returned from the internal shadow 1 = writes will be forwarded to pci, shad owed within the pch, and reads will be returned from the internal shadow. note: if some writes are done to lpc/pci to these i/o ranges, and then this bit is flipped, such that writes will now go to the other interface , the reads will not return what was last written. shadow ing is performed on each interface. the aliases for these register s, at 90h, 94h, 95h, 96h, 98h, 9ch, 9dh, and 9eh, are always decoded to lpc. 1 reserved 0 bios interface lock-down (bild) ? r/wlo. 0 = disabled. 1 = prevents buc.ts (offset 3414, bit 0) and gcs.bbs (offset 3410h, bits 11:10) from being changed. this bit can on ly be written from 0 to 1 once. bit description
datasheet 407 chipset configuration registers 10.1.44 bucbacked up control register offset address: 3414?3414h attribute: r/w default value: 0000000xb size: 8-bit all bits in this register are in the rtc well and only cleared by rtcrst#. 10.1.45 fdfunction disable register offset address: 3418?341bh attribute: r/w default value: see bit description size: 32-bit when disabling a function, only the config uration space is disabled. software must ensure that all functionality within a controller that is not desired (such as memory spaces, i/o spaces, and dma engines) is di sabled prior to disabling the function. when a function is disabled, software must not attempt to re-enable it. a disabled function can only be re-enabled by a platform reset. bit description 7:6 reserved 5 lan disable ? r/w. 0 = lan is enabled 1 = lan is disabled. this bit is locked by the function disabl e sus well lockdown register. once locked, this bit can not be changed by software. 4 daylight savings override (sdo) ? r/w. 0 = daylight savings is enabled. 1 = the dse bit in rtc register b is set to read-only with a value of 0 to disable daylight savings. 3:1 reserved 0 top swap (ts) ? r/w. 0 = pch will not invert a16. 1 = pch will invert a16 for cycles going to the bios space (but not the feature space) in the fwh. if pch is strapped for top-swap (gnt3# is low at rising edge of pwrok), then this bit cannot be cleared by software. the strap jumper should be removed and the system rebooted. bit description 31:26 reserved 25 serial ata disable 2 (sad2) ? r/w. default is 0. 0 = the sata controller #2 (d31:f5) is enabled. 1 = the sata controller #2 (d31:f5) is disabled. 24 thermal throttle disable (ttd) ? r/w. default is 0. 0 = thermal thrott le is enabled. 1 = thermal throttle is disabled. 23 pci express* 8 disable (pe8d) ? r/w. default is 0. when disabled, the link for this port is put into the ?link down? state. 0 = pci express* port #8 is enabled. 1 = pci express port #8 is disabled.
chipset configuration registers 408 datasheet 22 pci express 7 disable (pe7d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #7 is enabled. 1 = pci express port #7 is disabled. 21 pci express* 6 disable (pe6d) ? r/w. default is 0. when disabled, the link for this port is put into the ?link down? state. 0 = pci express* port #6 is enabled. 1 = pci express port #6 is disabled. 20 pci express 5 disable (pe5d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #5 is enabled. 1 = pci express port #5 is disabled. 19 pci express 4 disable (pe4d) ? r/w. default is 0. when disabled, the link for this port is put into th e ?link down? state. 0 = pci express port #4 is enabled. 1 = pci express port #4 is disabled. note: this bit must be set when po rt 1 is configured as a x4. 18 pci express 3 disable (pe3d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #3 is enabled. 1 = pci express port #3 is disabled. note: this bit must be set when po rt 1 is configured as a x4. 17 pci express 2 disable (pe2d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #2 is enabled. 1 = pci express port #2 is disabled. note: this bit must be set wh en port 1 is configured as a x4 or a x2. 16 pci express 1 disable (pe1d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #1 is enabled. 1 = pci express port #1 is disabled. 15 ehci #1 disable (ehci1d) ? r/w. default is 0. 0 = the ehci #1 is enabled. 1 = the ehci #1 is disabled. 14 lpc bridge disable (lbd) ? r/w. default is 0. 0 = the lpc bridge is enabled. 1 = the lpc bridge is disabled. unlike the ot her disables in this register, the following additional spaces will no longer be decoded by the lpc bridge: ? memory cycles below 16 mb (1000000h) ? i/o cycles below 64 kb (10000h) ? the internal i/oxapic at fec0_0000 to fecf_ffff memory cycle in the lpc bios range below 4 gb will still be decode d when this bit is set; however, the aliases at the top of 1 mb (the e and f segment) no longer will be decoded. 13 ehci #2 disable (ehci2d) ? r/w. default is 0. 0 = the ehci #2 is enabled. 1 = the ehci #2 is disabled. 12:5 reserved bit description
datasheet 409 chipset configuration registers 10.1.46 cgclock gating register offset address: 341c?341fh attribute: r/w default value: 00000000h size: 32-bit 4 intel ? high definition audio disable (hdad) ? r/w. default is 0. 0 = the intel ? high definition audio controller is enabled. 1 = the intel ? high definition audio controller is disabled and its pci configuration space is not accessible. 3 smbus disable (sd) ? r/w. default is 0. 0 = the smbus controller is enabled. 1 = the smbus controller is disabled. se tting this bit only disables the pci configuration space. 2 serial ata disable 1 (sad1) ? r/w. default is 0. 0 = the sata controller #1 (d31:f2) is enabled. 1 = the sata controller #1 (d31:f2) is disabled. 1 pci bridge disable ? r/w. default is 0. 0 = the pci-to-pci bridge (d30:f0) is enabled. 1 = the pci-to-pci bridge (d30:f0) is disabled. 0 bios must set this bit to 1b. bit description bit description 31 legacy (lpc) dynamic clock gate enable ? r/w. 0 = legacy dynamic clock gating is disabled 1 = legacy dynamic clock gating is enabled 30 reserved 29:28 cg field 1 ? r/w. bios must program this field to 11b. 27 sata port 3 dynamic clock gate enable ? r/w. 0 = sata port 3 dynamic clock gating is disabled 1 = sata port 3 dynamic clock gating is enabled 26 sata port 2 dynamic clock gate enable ? r/w. 0 = sata port 2 dynamic clock gating is disabled 1 = sata port 2 dynamic clock gating is enabled 25 sata port 1 dynamic clock gate enable ? r/w. 0 = sata port 1 dynamic clock gating is disabled 1 = sata port 1 dynamic clock gating is enabled 24 sata port 0 dynamic clock gate enable ? r/w. 0 = sata port 0 dynamic clock gating is disabled 1 = sata port 0 dynamic clock gating is enabled 23 lan static clock gating enable (lanscge) ? r/w. 0 = lan static clock gating is disabled 1 = lan static clock gating is enabled when the lan disable bit is set in the backed up control rtc register. 22 high definition audio dynamic clock gate enable ? r/w. 0 = high definition audio dynamic clock gating is disabled 1 = high definition audio dynamic clock gating is enabled
chipset configuration registers 410 datasheet 10.1.47 fdswfunction disa ble sus well register offset address: 3420h attribute: r/w default value: 00h size: 8-bit 21 high definition audio static clock gate enable ? r/w. 0 = high definition audio static clock gating is disabled 1 = high definition audio static clock gating is enabled 20 usb ehci static clock gate enable ? r/w. 0 = usb ehci static cl ock gating is disabled 1 = usb ehci static clock gating is enabled 19 usb ehci dynamic clock gate enable ? r/w. 0 = usb ehci dynamic cl ock gating is disabled 1 = usb ehci dynamic clock gating is enabled 18 sata port 5 dynamic clock gate enable ? r/w. 0 = sata port 5 dynamic clock gating is disabled 1 = sata port 5 dynamic clock gating is enabled 17 sata port 4 dynamic clock gate enable ? r/w. 0 = sata port 4 dynamic clock gating is disabled 1 = sata port 4 dynamic clock gating is enabled 16 pci dynamic gate enable ? r/w. 0 = pci dynamic gating is disabled 1 = pci dynamic gating is enabled 15:6 reserved 5 smbus clock gating enable (smbcgen) ? r/w. 0 = smbus clock gating is disabled. 1 = smbus clock gating is enabled. 4:1 reserved 0 pci express root port static clock gate enable ? r/w. 0 = pci express root port stat ic clock gating is disabled 1 = pci express root port stat ic clock gating is enabled bit description bit description 7 function disable sus well lockdown (fdswl) ? r/w03 0 = fdsw registers are not locked down 1 = fdsw registers are locked down note: this bit must be set when intel ? active management technology is enabled. 6:0 reserved
datasheet 411 chipset configuration registers 10.1.48 dispbdfdisplay bus, device and function initialization register offset address: 3424?3425h attribute: r/w default value: 0010h size: 16-bit 10.1.49 fd2function disable 2 register offset address: 3428?342bh attribute: r/w default value: 00000000h size: 32-bit bit description 15:8 display bus number (dbn) ? r/w. the bus number of the display in the processor. bios should alwa ys program these bits as 0. 7:3 display device number (ddn) ? r/w. the device numbe r of the display in the processor. bios should alwa ys program these bits as 2. 2:0 display function number (dfn) ? r/w. the function number of the display in the processor. bios should alwa ys program these bits as 0. bit description 31:5 reserved 4 kt disable (ktd) ?r/w. default is 0. 0 = keyboard text controll er (d22:f3) is enabled. 1 = keyboard text controll er (d22:f3) is disabled 3 ide-r disable (irerd) ?r/w. default is 0. 0 = ide redirect controll er (d22:f2) is enabled. 1 = ide redirect controller (d22:f2) is disabled. 2 intel ? mei #2 disable (mei2d) ?r/w. default is 0. 0 = intel mei controller #2 (d22:f1) is enabled. 1 = intel mei controller #2 (d22:f1) is disabled. 1 intel mei #1 disable (mei1d) ?r/w. default is 0. 0 = intel mei controller #1 (d22:f0) is enabled. 1 = intel mei controller #1 (d22:f0) is disabled. 0 display bdf enable (dbdfen) ?r/w.
chipset configuration registers 412 datasheet 10.1.50 miscctlmiscella neous control register offset address: 3590?3593h attribute: r/w default value: 00000000h size: 32-bit this register is in the suspend well. this register is not reset on d3-to-d0, hcreset nor core well reset. bit description 31:2 reserved 1 ehci 2 usbr enable ? r/w. when set, this bit enables support for the usb-r redirect device on the ehci controller in device 26. sw must complete programming the following registers be fore this bit is set: 1. enable rmh 2. hcsparams (n_cc, n_ports) 0 ehci 1 usbr enable ? r/w. when set, this bit enables support for the usb-r redirect device on the ehci controller in device 29. sw must complete programming the following registers be fore this bit is set: 1. enable rmh 2. hcsparams (n_cc, n_ports)
datasheet 413 chipset configuration registers 10.1.51 usbocm1overcurr ent map register 1 offset address: 35a0?35a3h attribute: r/w0 default value: c0300c03h size: 32-bit all bits in this register are in the resume well and is only cleared by rsmrst#. bit description 31:24 oc3 mapping each bit position maps oc3# to a set of ports as follows: the oc3# pin is ganged to the overcurrent signal of ea ch port that has its corresponding bit set. it is software responsibility to ensure that a given port?s bit map is set only for one oc pin. 23:16 oc2 mapping each bit position maps oc2# to a set of ports as follows: the oc2# pin is ganged to the overcurrent signal of ea ch port that has its corresponding bit set. it is software responsibility to ensure that a given port?s bit map is set only for one oc pin. 15:8 oc1 mapping each bit position maps oc1# to a set of ports as follows: the oc1# pin is ganged to the overcurrent signal of ea ch port that has its corresponding bit set. it is software responsibility to ensure that a given port?s bit map is set only for one oc pin. 7:0 oc0 mapping each bit position maps oc0# to a set of ports as follows: the oc0# pin is ganged to the overcurrent signal of ea ch port that has its corresponding bit set. it is software responsibility to ensure that a given port?s bit map is set only for one oc pin. bit 31 30 29 28 27 26 25 24 port 76543210 bit 23 22 21 20 19 18 17 16 port 76543210 bit 15 14 13 12 11 10 9 8 port 76543210 bit 76543210 port 76543210
chipset configuration registers 414 datasheet 10.1.52 usbocm2overcurre nt map register 2 offset address: 35a4?35a7h attribute: r/w0 default value: 00000000h size: 32-bit all bits in this register are in the resume well and is only cleared by rsmrst# bit description 31:30 reserved 29:24 oc7 mapping each bit position maps oc7# to a set of ports as follows: the oc7# pin is ganged to the overcurrent signal of ea ch port that has its corresponding bit set. it is software responsibility to ensure that a given port?s bit map is set only for one oc pin. 23:22 reserved 21:16 oc6 mapping each bit position maps oc6# to a set of ports as follows: the oc6# pin is ganged to the overcurrent signal of ea ch port that has its corresponding bit set. it is software responsibility to ensure that a given port?s bit map is set only for one oc pin. 15:14 reserved 13:8 oc5 mapping each bit position maps oc5# to a set of ports as follows: the oc5# pin is ganged to the overcurrent signal of ea ch port that has its corresponding bit set. it is software responsibility to ensure that a given port?s bit map is set only for one oc pin. 7:6 reserved 5:0 oc4 mapping each bit position maps oc4# to a set of ports as follows: the oc4# pin is ganged to the overcurrent signal of ea ch port that has its corresponding bit set. it is software responsibility to ensure that a given port?s bit map is set only for one oc pin. bit 29 28 27 26 25 24 port 13 12 11 10 9 8 bit 21 20 19 18 17 16 port 13 12 11 10 9 8 bit 13 12 11 10 9 8 port 13 12 11 10 9 8 bit 543210 port 13 12 11 10 9 8
datasheet 415 chipset configuration registers 10.1.53 rmhwkctlrate matching hub wake control register offset address: 35b0?35b3h attribute: r/w default value: 00000000h size: 32-bit all bits in this register are in the resume well and is only cleared by rsmrst#. bit description 31:10 reserved 9 rmh 2 inherit ehci2 wake control settings: when this bit is set, the rmh behaves as if bits 6:4 of this register re flect the appropriate bits of ehci portsc0 bits 22:20. 8 rmh 1 inherit ehci1 wake control settings: when this bit is set, the rmh behaves as if bits 2:0 of this register re flect the appropriate bits of ehci portsc0 bits 22:20. 7 rmh 2 upstream wake on device resume this bit governs the hub behavior when globally suspended an d the system is in sx. 0 = enables the port to be sensitive to de vice initiated resume events as system wake-up events; that is, the hub will init iate a resume on it s upstream port and cause a wake from sx when a device re sume occurs on an enabled ds port 1 = device resume event is seen on a down stream port, the hub does not initiate a wake upstream and does not cause a wake from sx 6 rmh 2 upstream wake on oc disable this bit governs the hub behavior when globally suspended and the system is in sx. 0 = enables the port to be sensitive to ov er-current conditions as system wake-up events; that is, the hub will initiate a resume on its upstre am port and cause a wake from sx when an oc conditio n occurs on an enabled ds port 1 = over-current event does not initiate a wake upstream and does not cause a wake from sx 5 rmh 2 upstream wake on disconnect disable this bit governs the hub behavior when globally suspended an d the system is in sx 0 = enables disconnect events on downstream port to be treated as resume events to be propagated upstream. in this case, it is allowed to initiate a wake on its upstream port and cause a system wake from sx in response to a disconnect event on a downstream port 1 = downstream disconnect events do not init iate a resume on its upstream port or cause a resume from sx. 4 rmh 2 upstream wake on connect enable this bit governs the hub behavior when globally suspended an d the system is in sx. 0 = enables connect events on a downstream port to be treated as resume events to be propagated upstream. as well as waking up the system from sx. 1 = downstream connect events do not wake the system from sx nor does it initiate a resume on its upstream port. 3 rmh 1 upstream wake on device resume this bit governs the hub behavior when globally suspended an d the system is in sx. 0 = enables the port to be sensitive to de vice initiated resume events as system wake-up events; that is, the hub will init iate a resume on it s upstream port and cause a wake from sx when a device re sume occurs on an enabled ds port 1 = device resume event is seen on a down stream port, the hub does not initiate a wake upstream and does not cause a wake from sx
chipset configuration registers 416 datasheet 2 rmh 1 upstream wake on oc disable this bit governs the hub behavior when globally suspended and the system is in sx. 0 = enables the port to be sensitive to over-current conditions as system wake-up events. that is, the hub will initiate a resume on its upstre am port and cause a wake from sx when an oc conditio n occurs on an enabled ds port 1 = over-current event does not initiate a wake upstream and does not cause a wake from sx 1 rmh 1 upstream wake on disconnect disable this bit governs the hub behavior when globally suspended and the system is in sx 0 = enables disconnect events on downstream port to be treate d as resume events to be propagated upstream. in this case, it is allowed to initiate a wake on its upstream port and cause a system wake from sx in response to a disconnect event on a downstream port 1 = downstream disconnect events do not initiate a resu me on its upstream port or cause a resume from sx. 0 rmh 1 upstream wake on connect enable this bit governs the hub behavior when globally suspended and the system is in sx. 0 = enables connect events on a downstream port to be treated as resume events to be propagated upstream. as well as waking up the system from sx. 1 = downstream connect events do not wake the system from sx nor does it initiate a resume on its upstream port. bit description
datasheet 417 pci-to-pci bridge registers (d30:f0) 11 pci-to-pci bridge registers (d30:f0) the pch pci bridge resides in pci device 30, function 0 on bus #0. this implements the buffering and control logic between pci and the backbone. the arbitration for the pci bus is handled by this pci device. 11.1 pci configuration registers (d30:f0) note: address locations that are not shown should be treated as reserved (see section 9.2 for details). table 11-1. pci bridge register address map (pci-pcid30:f0) offset mnemonic register name default attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h psts pci status 0010h r/wc, ro 08h rid revision identification see register description ro 09h?0bh cc class code 060401h ro 0dh pmlt primary master latency timer 00h ro 0eh headtyp header type 01h ro 18h?1ah bnum bus number 000000h ro 1bh smlt secondary master latency timer 00h r/w 1ch?1dh iobase_limit i/o base and limit 0000h r/w, ro 1eh?1fh secsts secondary status 0280h r/wc, ro 20h?23h membase_ limit memory base and limit 00000000h r/w 24h?27h pref_mem_ base_limit prefetchable memory base and limit 00010001h r/w, ro 28h?2bh pmbu32 prefetchable memory upper 32 bits 00000000h r/w 2ch?2fh pmlu32 prefetchable memory limit upper 32 bits 00000000h r/w 34h capp capability list pointer 50h ro 3ch?3dh intr interrupt information 0000h r/w, ro 3eh?3fh bctrl bridge control 0000h r/wc, ro, r/w 40h?41h spdh secondary pci device hiding 0000h r/w, ro 44h?47h dtc delayed transaction control 00000000h r/w 48h?4bh bps bridge proprietary status 00000000h r/wc, ro 4ch?4fh bpc bridge policy configuration 10001200h r/w, ro 50h?51h svcap subsystem vendor capability pointer 000dh ro 54h?57h svid subsystem vendor ids 00000000h r/wo
pci-to-pci bridge registers (d30:f0) 418 datasheet 11.1.1 vid vendor identificati on register (pci-pcid30:f0) offset address: 00h?01h attribute: ro default value: 8086h size: 16 bits 11.1.2 did device identificati on register (pci-pcid30:f0) offset address: 02h?03h attribute: ro default value: see bit description size: 16 bits 11.1.3 pcicmdpci command (pci-pcid30:f0) offset address: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:0 vendor id ? ro. this is a 16-bit value assi gned to intel. intel vid = 8086h. bit description 15:0 device id ? ro. this is a 16-bit value assigned to the pci bridge. bit description 15:11 reserved 10 interrupt disable (id) ? ro. hardwired to 0. the pci bridge has no interrupts to disable. 9 fast back to back enable (fbe) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a . 8 serr# enable (serr_en) ? r/w. 0 = disable. 1 = enable the pch to generate an nmi (or smi# if nmi routed to smi#) when the d30:f0 sse bit (offset 06h, bit 14) is set. 7 wait cycle control (wcc) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a . 6 parity error response (per) ? r/w. 0 = the pch ignores parity errors on the pci bridge. 1 = the pch will set the sse bit (d30:f0, of fset 06h, bit 14) when parity errors are detected on the pci bridge. 5 vga palette snoop (vps) ? ro . hardwired to 0, per the pci express* base specification, revision 1.0a . 4 memory write and invalidate enable (mwe) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a 3 special cycle enable (sce) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a and the pci- to-pci bridge specification.
datasheet 419 pci-to-pci bridge registers (d30:f0) 11.1.4 pstspci status register (pci-pcid30:f0) offset address: 06h ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 2 bus master enable (bme) ? r/w. 0 = disable 1 = enable. allows the pci-to-pci br idge to accept cycles from pci. 1 memory space enable (mse) ? r/w. controls the respon se as a target for memory cycles targeting pci. 0 = disable 1 = enable 0 i/o space enable (iose) ? r/w. controls the response as a target for i/o cycles targeting pci. 0 = disable 1 = enable bit description bit description 15 detected parity error (dpe) ? r/wc. 0 = parity error not detected. 1 = indicates that the pch detect ed a parity error on the inte rnal backbone. this bit gets set even if the parity error response bit (d30:f0:04 bit 6) is not set.
pci-to-pci bridge registers (d30:f0) 420 datasheet 14 signaled system error (sse) ? r/wc. several internal an d external sources of the bridge can cause serr#. the first class of errors is parity e rrors related to the backbone. the pci bridge captures generic da ta parity errors (errors it finds on the backbone) as well as errors returned on backbone cycles wher e the bridge was the master. if either of these two conditions is met, and the primary side of the bridge is enabled for parity error response, serr# will be captured as shown below. as with the backbone, the pci bus captures the same sets of e rrors. the pci bridge captures generic data parity erro rs (errors it finds on pci) as well as errors returned on pci cycles where the bridge was the master. if either of these two conditions is met, and the secondary side of the bridge is enable d for parity error response, serr# will be captured as shown below. the final class of errors is system bus errors. there are three status bits associated with system bus errors, each with a corresponding enable. the diagram capturing this is shown below. after checking for the three above classes of errors, an serr# is generated, and psts.sse logs the generation of serr#, if cm d.see (d30:f0:04, bit 8) is set, as shown below. 13 received master abort (rma) ? r/wc. 0 = no master abort received. 1 = set when the bridge receives a ma ster abort status from the backbone. 12 received target abort (rta) ? r/wc. 0 = no target abort received. 1 = set when the bridge receives a ta rget abort status from the backbone. bit description
datasheet 421 pci-to-pci bridge registers (d30:f0) 11.1.5 ridrevision identificati on register (pci-pcid30:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 11.1.6 ccclass code register (pci-pcid30:f0) offset address: 09h?0bh attribute: ro default value: 060401h size: 24 bits 11 signaled target abort (sta) ? r/wc. 0 = no signaled target abort 1 = set when the bridge generates a completion packet with target abort status on the backbone. 10:9 reserved 8 data parity error detected (dpd) ? r/wc. 0 = data parity error not detected. 1 = set when the bridge receives a comp letion packet from the backbone from a previous request, and detects a parity error, and cmd. pere is set (d30:f0:04 bit 6). 7:5 reserved 4 capabilities list (clist) ? ro. hardwired to 1. capabili ty list exist on the pci bridge. 3 interrupt status (is) ? ro. hardwired to 0. the pci bridge does not generate interrupts. 2:0 reserved bit description bit description 7:0 revision id ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit description 23:16 base class code (bcc) ? ro. hardwired to 06h. indicates this is a bridge device. 15:8 sub class code (scc) ? ro. hardwired to 04h. indicates th is device is a pci-to-pci bridge. 7:0 programming interface (pi) ? ro. hardwired to 01h. indicates the bridge is subtractive decode
pci-to-pci bridge registers (d30:f0) 422 datasheet 11.1.7 pmltprimary master latency timer register (pci-pcid30:f0) offset address: 0dh attribute: ro default value: 00h size: 8 bits 11.1.8 headtypheader type register (pci-pcid30:f0) offset address: 0eh attribute: ro default value: 01h size: 8 bits 11.1.9 bnumbus number re gister (pci-pcid30:f0) offset address: 18h?1ah attribute: r/w default value: 000000h size: 24 bits bit description 7:3 master latency timer count (mltc) ? ro. reserved per the pci express* base specification, revision 1.0a . 2:0 reserved bit description 7 multi-function device (mfd) ? ro. a 0 indicates a single function device 6:0 header type (htype) ? ro. this 7-bit field identifi es the header layout of the configuration space, which is a pci-to-pci bridge in this case. bit description 23:16 subordinate bus number (sbbn) ? r/w. indicates the highest pci bus number below the bridge. 15:8 secondary bus number (scbn) ? r/w. indicates the bus number of pci. 7:0 primary bus number (pbn) ? r/w. this field is default to 00h. in a multiple-pch system, programmable pbn allows an pch to be located on any bus. system configuration software is responsible for in itializing these registers to appropriate values. pbn is not used by hardwa re in determinin g its bus number.
datasheet 423 pci-to-pci bridge registers (d30:f0) 11.1.10 smltsecondary master latency timer register (pci-pcid30:f0) offset address: 1bh attribute: r/w default value: 00h size: 8 bits this timer controls the amount of time the pch pci-to-pci bridge will burst data on its secondary interface. the counter starts co unting down from the assertion of frame#. if the grant is removed, then the expiration of this counter will result in the deassertion of frame#. if the grant has not been remo ved, then the pch pci-to-pci bridge may continue ownership of the bus. 11.1.11 iobase_limiti/o ba se and limit register (pci-pcid30:f0) offset address: 1ch?1dh attribute: r/w, ro default value: 0000h size: 16 bits bit description 7:3 master latency timer count (mltc) ? r/w. this 5-bit field indi cates the number of pci clocks, in 8-clock increments, that the pch remains as master of the bus. 2:0 reserved bit description 15:12 i/o limit address limit bits [15:12] ? r/w. i/o base bits corresponding to address lines 15:12 for 4-kb alignment. bits 11: 0 are assumed to be padded to fffh. 11:8 i/o limit address capability (iolc) ? ro. indicates that the bridge does not support 32-bit i/o addressing. 7:4 i/o base address (ioba) ? r/w. i/o base bits corresponding to address lines 15:12 for 4-kb alignment. bi ts 11:0 are assumed to be padded to 000h. 3:0 i/o base address capability (iobc) ? ro. indicates that the bridge does not support 32-bit i/o addressing.
pci-to-pci bridge registers (d30:f0) 424 datasheet 11.1.12 secstssecondary status register (pci-pcid30:f0) offset address: 1eh ? 1fh attribute: r/wc, ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = parity error not detected. 1 = pch pci bridge detected an address or data parity error on the pci bus 14 received system error ( rse) ? r/wc. 0 = serr# assertion not received 1 = serr# assertion is received on pci. 13 received master abort (rma) ? r/wc. 0 = no master abort. 1 = this bit is set whenever th e bridge is acting as an in itiator on the pci bus and the cycle is master-aborted. for processor/pch interface packets that have completion required, this must also ca use a target abort to be re turned and sets psts.sta. (d30:f0:06 bit 11) 12 received target abort (rta) ? r/wc. 0 = no target abort. 1 = this bit is set whenever the bridge is acting as an initiator on pci and a cycle is target-aborted on pci. for processor/pch interface packets that have completion required, this event must also cause a target abort to be returned, and sets psts.sta. (d30:f0:06 bit 11). 11 signaled target abort (sta) ? r/wc. 0 = no target abort. 1 = this bit is set when the br idge is acting as a target on the pci bus and signals a target abort. 10:9 devsel# timing (devt) ? ro. 01h = medium decode timing. 8 data parity error detected (dpd) ? r/wc. 0 = conditions de scribed below not met. 1 = the pch sets this bit when all of the following three conditions are met: ? the bridge is the initiator on pci. ? perr# is detected asserted or a parity error is detected internally ? bctrl.pere (d30:f0:3e bit 0) is set. 7 fast back to back capable (fbc) ? ro. hardwi red to 1 to indicate that the pci to pci target logic is capable of rece iving fast back-to-back cycles. 6 reserved 5 66 mhz capable (66mhz_cap) ? ro. hardwire d to 0. this bridge is 33 mhz capable only. 4:0 reserved
datasheet 425 pci-to-pci bridge registers (d30:f0) 11.1.13 membase_limitmemory base and limit register (pci-pcid30:f0) offset address: 20h?23h attribute: r/w default value: 00000000h size: 32 bits this register defines the base and limit, aligned to a 1-mb boundary, of the non- prefetchable memory area of the bridge. a ccesses that are within the ranges specified in this register will be sent to pci if cmd. mse is set. accesses from pci that are outside the ranges specified will be accepted by the bridge if cmd.bme is set. 11.1.14 pref_mem_base_limitprefetchable memory base and limit register (pci-pcid30:f0) offset address: 24h?27h attribute: r/w, ro default value: 00010001h size: 32-bit defines the base and limit, aligned to a 1- mb boundary, of the prefetchable memory area of the bridge. accesses that are within th e ranges specified in this register will be sent to pci if cmd.mse is set. accesses from pci that are outside the ranges specified will be accepted by the bridge if cmd.bme is set. bit description 31:20 memory limit (ml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the upper 1-mb alig ned value (exclusive) of the range. the incoming address must be less than this value. 19:16 reserved 15:4 memory base (mb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lower 1-mb alig ned value (inclusive) of the range. the incoming address must be greate r than or equal to this value. 3:0 reserved bit description 31:20 prefetchable memory limit (pml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the u pper 1-mb aligned value (exclusive) of the range. the incoming address mu st be less than this value. 19:16 64-bit indicator (i64l) ? ro. indicates support for 64-bit addressing. 15:4 prefetchable memory base (pmb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lo wer 1-mb aligned value (inclusive) of the range. the incoming address must be greater than or equal to this value. 3:0 64-bit indicator (i64b) ? ro. indicates support fo r 64-bit addressing.
pci-to-pci bridge registers (d30:f0) 426 datasheet 11.1.15 pmbu32prefetchable memory base upper 32 bits register (pci-pcid30:f0) offset address: 28h?2bh attribute: r/w default value: 00000000h size: 32 bits 11.1.16 pmlu32prefetchable memory limit upper 32 bits register (pci-pcid30:f0) offset address: 2c?2fh attribute: r/w default value: 00000000h size: 32 bits 11.1.17 cappcapability list poin ter register (pci-pcid30:f0) offset address: 34h attribute: ro default value: 50h size: 8 bits 11.1.18 intrinterrupt informat ion register (pci-pcid30:f0) offset address: 3ch ? 3dh attribute: r/w, ro default value: 0000h size: 16 bits bit description 31:0 prefetchable memory base upper portion (pmbu) ? r/w. upper 32-bits of the prefetchable address base. bit description 31:0 prefetchable memory limit upper portion (pmlu) ? r/w. upper 32-bits of the prefetchable address limit. bit description 7:0 capabilities pointer (ptr) ? ro. indicates that the pointer for the first entry in the capabilities list is at 50h in configuration space. bit description 15:8 interrupt pin (ipin) ? ro. the pci bridge does not assert an interrupt. 7:0 interrupt line (iline) ? r/w. software written value to indicate which interrupt line (vector) the interrupt is conn ected to. no hardware action is taken on this register. since the bridge does not gene rate an interrupt, bios should program this value to ffh as per the pci bri dge specification.
datasheet 427 pci-to-pci bridge registers (d30:f0) 11.1.19 bctrlbridge control register (pci-pcid30:f0) offset address: 3eh ? 3fh attribute: r/wc, ro, r/w default value: 0000h size: 16 bits bit description 15:12 reserved 11 discard timer serr# enable (dte ) ? r/w. controls the generation of serr# on the primary interface in respon se to the dts bit being set: 0 = do not generate serr# on a secondary timer discard 1 = generate serr# in response to a secondary timer discard 10 discard timer status (dts) ? r/wc. this bit is set to 1 when the secondary discard timer (see the sdt bit below) expires for a delayed transaction in the hard state. 9 secondary discard timer (sdt) ? r/w. this bit sets the maximum number of pci clock cycles that the pch waits for an initia tor on pci to repeat a delayed transaction request. the counter starts once the delayed transaction data is has been returned by the system and is in a buffer in the pch pci bridge. if the master has not repeated the transaction at least once before the counter expires, the pch pci bridge discards the transaction from its queue. 0 = the pci master timeout value is between 2 15 and 2 16 pci clocks 1 = the pci master timeout value is between 2 10 and 2 11 pci clocks 8 primary discard timer (pdt ) ? r/w. this bit is r/w for software compatibility only. 7 fast back to back enable (fbe) ? ro. hardwi red to 0. the pci logi c will not generate fast back-to-back cycles on the pci bus. 6 secondary bus reset (sbr) ? r/w. controls pcirst# assertion on pci. 0 = bridge deasserts pcirst# 1 = bridge asserts pcirst#. when pcirst # is asserted, the delayed transaction buffers, posting buffers, and the pci bus ar e initialized back to reset conditions. the rest of the part and the config uration registers are not affected. 5 master abort mode (mam ) ? r/w. controls the pch pc i bridge?s behavior when a master abort occurs: master abort on processor /pch interconnect (dmi): 0 = bridge asserts trdy# on pci. it drives all 1s for read s, and discards data on writes. 1 = bridge returns a target abort on pci. master abort pci (non-locked cycles): 0 = normal completion status will be retu rned on the processo r/pch interconnect. 1 = target abort completion st atus will be returned on th e processor/pch interconnect. note: all locked reads will return a comple ter abort completion status on the processor/pch interconnect. 4 vga 16-bit decode (v16d) ? r/w. enables the pch pci bridge to provide 16-bits decoding of vga i/o address precluding the decode of vga alias addresses every 1 kb. this bit requires the vgae bi t in this register be set.
pci-to-pci bridge registers (d30:f0) 428 datasheet 11.1.20 spdhsecondary pci device hiding register (pci-pcid30:f0) offset address: 40h?41h attribute: r/w, ro default value: 0000h size: 16 bits this register allows software to hide the pci devices, either plugged into slots or on the motherboard. 3 vga enable (vgae) ? r/w. when set to a 1, the pch pci bridge forwards the following transactions to pci regardless of th e value of the i/o base and limit registers. the transactions are qualified by cm d.mse (d30:f0:04 bit 1) and cmd.iose (d30:f0:04 bit 0) being set. ? memory addresses: 000a0000h?000bffffh ? i/o addresses: 3b0h?3bbh and 3c0h?3dfh. for th e i/o addresses, bits [63:16] of the address must be 0, and bits [15:10] of the address are ignored (that is, aliased). the same holds true from secondary accesses to the primary interface in reverse. that is, when the bit is 0, memory and i/o a ddresses on the second ary interface between the above ranges will be claimed. 2 isa enable (ie) ? r/w. this bit only applies to i/ o addresses that are enabled by the i/o base and i/o limit registers and are in the fi rst 64 kb of pci i/o space. if this bit is set, the pch pci bridge will block any forwarding from primary to secondary of i/o transactions addressing the last 768 bytes in each 1-kb block (o ffsets 100h to 3ffh). 1 serr# enable (see) ? r/w. controls the forwarding of secondary interface serr# assertions on the primary interface. when se t, the pci bridge will forward serr# pin. ? serr# is asserted on the secondary interface. ? this bit is set. ? cmd.see (d30:f0:04 bit 8) is set. 0 parity error response enable (pere) ? r/w. 0 = disable 1 = the pch pci bridge is enabled for parity error reporting based on parity errors on the pci bus. bit description bit description 15:4 reserved 3 hide device 3 (hd3) ? r/w, ro. same as bit 0 of th is register, except for device 3 (ad[19]) 2 hide device 2 (hd2) ? r/w, ro. same as bit 0 of this register, except for device 2 (ad[18]) 1 hide device 1 (hd1) ? r/w, ro. same as bit 0 of this regi ster, except for device 1 (ad[17]) 0 hide device 0 (hd0) ? r/w, ro. 0 = the pci configuration cycles for this slot are not affected. 1 = the pch hides device 0 on the pci bus. this is done by masking the idsel (keeping it low) for configuration cycles to that device. since the device will not see its idsel go active, it will not respond to pci configuration cycles and the processor will think the device is not presen t. ad[16] is used as idsel for device 0.
datasheet 429 pci-to-pci bridge registers (d30:f0) 11.1.21 dtcdelayed transa ction control register (pci-pcid30:f0) offset address: 44h ? 47h attribute: r/w default value: 00000000h size: 32 bits bit description 31 discard delayed transactions (ddt) ? r/w. 0 = logged delayed transactions are kept. 1 = the pch pci bridge will discard any de layed transactions it has logged. this includes transactions in th e pending queue, and any transactions in the active queue, whether in the hard or soft dt st ate. the prefetchers will be disabled and return to an idle state. notes: if a transaction is running on pci at the time this bit is set, that transaction will continue until either the pci master disconnects (by deasserting frame#) or the pci bridge disconnects (by asserting stop#). this bit is cleared by the pci bridge when the delayed transaction queu es are empty and have returned to an idle state. software sets this bit and poll s for its completion. 30 block delayed transactions (bdt) ? r/w. 0 = delayed transactions accepted 1 = the pch pci bridge will not accept incoming transactions which will result in delayed transactions. it will blindly retr y these cycles by asserting stop#. all postable cycles (memory writes) will still be accepted. 29:8 reserved 7:6 maximum delayed transactions (mdt) ? r/w. controls the maximum number of delayed transactions that the pch pc i bridge will run. encodings are: 00 =) 2 active, 5 pending 01 =) 2 active, no pending 10 =) 1 active, no pending 11 =) reserved 5 reserved 4 auto flush after disco nnect enable (afade) ? r/w. 0 = the pci bridge will retain any fetched da ta until required to discard by producer/ consumer rules. 1 = the pci bridge will flush any prefetched data after either the pci master (by deasserting frame#) or the pci bridge (by assertin g stop#) disconnects the pci transfer. 3 never prefetch (np) ? r/w. 0 = prefetch enabled 1 = the pch will only fetch a single dw and will not enable prefetching, regardless of the command being an memory read (mr), memory read line (mrl), or memory read multiple (mrm).
pci-to-pci bridge registers (d30:f0) 430 datasheet 11.1.22 bpsbridge proprietary status register (pci-pcid30:f0) offset address: 48h ? 4bh attribute: r/wc, ro default value: 00000000h size: 32 bits 2 memory read multiple prefetch disable (mrmpd) ? r/w. 0 = mrm commands will fetch multiple ca che lines as defined by the prefetch algorithm. 1 = memory read multiple (mrm) commands wi ll fetch only up to a single, 64-byte aligned cache line. 1 memory read line prefetch disable (mrlpd) ? r/w. 0 = mrl commands will fetch multiple cache lines as defined by the prefetch algorithm. 1 = memory read line (mrl) commands will fe tch only up to a single, 64-byte aligned cache line. 0 memory read prefetch disable (mrpd) ? r/w. 0 = mr commands will fetch up to a 64-byte aligned cache line. 1 = memory read (mr) commands will fetch only a single dw. bit description bit description 31:17 reserved 16 perr# assertion detected (pad) ? r/wc. this bit is set by hardware whenever the perr# pin is asserted on the ri sing edge of pci clock. this includes cases in which the chipset is the agent driving perr#. it re mains asserted until cleared by software writing a 1 to this location. when enabled by the perr#-to-serr# enable bit (in the bridge policy configuration regi ster), a 1 in this bit can generate an internal serr# and be a source for the nmi logic. this bit can be used by software to de termine the source of a system problem. 15:7 reserved 6:4 number of pending transactions (npt) ? ro. this read-only indicator tells debug software how many transactions are in the pending queue. possible values are: 000 = no pending transaction 001 = 1 pending transaction 010 = 2 pending transactions 011 = 3 pending transactions 100 = 4 pending transactions 101 = 5 pending transactions 110?111 = reserved note: this field is not valid if dtc.mdt (offset 44h:bits 7:6) is any value other than ?00?. 3:2 reserved 1:0 number of active transactions (nat) ? ro. this read-only indicator tells debug software how many transactions are in the active queue. possible values are: 00 = no active transactions 01 = 1 active transaction 10 = 2 active transactions 11 = reserved
datasheet 431 pci-to-pci bridge registers (d30:f0) 11.1.23 bpcbridge policy configuration register (pci-pcid30:f0) offset address: 4ch?4fh attribute: r/w default value: 10001200h size: 32 bits bit description 31:30 reserved 29 subtractive decode compatibility device id (sdcdid) ? r/w: when '0', this function shall report a device id of 244eh for desktop. when set to '1', this function shall report the devi ce device id value assigned to the pci-to-pci bridge in section . if subtractive decode (sde) is enabled, havi ng this bit as '0' allows the function to present a device id that is recognized by the os. 28 subtractive decode enable (sde) ? r/w: 0 = subtractive decode is disabled this f unction and will only claim transactions positively. 1 = the subtractive decode policy as listed in sdp below applies. software must ensure that on ly one pch device is enabled for subtractive decode at a time. 27:14 reserved 13:8 upstream read latency threshold (urlt) ? r/w: this field specifies the number of pci clocks after internally enqueuing an upstream memory read request at which point the pci target logic should insert wait states in order to optimize lead-off latency. when the master returns after this thre shold has been reached and data has not arrived in the delayed transaction completion queue, then the pci target logic will insert wait states instead of immediately re trying the cycle. the pci target logic will insert up to 16 clocks of target initial latency (from frame# assertion to trdy# or stop# assertion) before retrying the pci re ad cycle (if the read data has not arrived yet). note that the starting event for this read latency timer is not explicitly visible externally. a value of 0h disables this policy completely such that wait states will never be inserted on the read lead-off data phase. the default value (12h) specifies 18 pci clocks (540 ns) and is a pproximately 4 clocks less than the typical idle lead-off latency expected for desktop pch systems. this value may need to be changed by bi os, depending on the platform.
pci-to-pci bridge registers (d30:f0) 432 datasheet 11.1.24 svcapsubsystem vend or capability register (pci-pcid30:f0) offset address: 50h ? 51h attribute: ro default value: 000dh size: 16 bits 7 subtractive decode policy (sdp) ? r/w. 0 = the pci bridge always forwards memory and i/o cycles that ar e not claimed by any other device on the backbone (primary interface) to the pci bus (secondary interface). 1 = the pci bridge will not cl aim and forward memory or i/ o cycles at all unless the corresponding space enable bit is set in the command register. note: the boot bios destination selection strap can force the bios accesses to pci. 6 perr#-to-serr# enable (pse) ? r/w. when this bit is set, a 1 in the perr# assertion status bit (in the bri dge proprietary status register) will result in an internal serr# assertion on the primary side of th e bridge (if also en abled by the serr# enable bit in the primary command re gister). serr# is a source of nmi. 5 secondary discard timer testmode (sdtt) ? r/w. 0 = the secondary discard timer expiration will be defined in bctrl.sdt (d30:f0:3e, bit 9) 1 = the secondary discard timer will expire after 128 pci clocks. 4:3 reserved 2 peer decode enable (pde) ? r/w. 0 = the pci bridge assumes th at all memory cycles target main memory, and all i/o cycles are not claimed. 1 = the pci bridge will perform peer decode on any memory or i/o cycle from pci that falls outside of the memory and i/o window registers 1reserved 0 received target abort serr# enable (rtae) ? r/w. when set, the pci bridge will report serr# when psts.rta (d30:f0:06 bit 12) or ssts.rta (d30:f0:1e bit 12) are set, and cmd.see (d30:f0:04 bit 8) is set. bit description cmd.mse bpc.sdp range forwarding policy 00d o n ? t c a r e forward unclaimed cycles 0 1 don?t care forwarding prohibited 1xw i t h i n r a n g e positive decode and forward 1xo u t s i d e subtractive decode & forward bit description 15:8 next capability (next) ? ro. value of 00h indicates this is the last item in the list. 7:0 capability identifier (cid) ? ro. value of 0dh indicates this is a pci bridge subsystem vendor capability.
datasheet 433 pci-to-pci bridge registers (d30:f0) 11.1.25 svidsubsystem vendor ids register (pci-pcid30:f0) offset address: 54h ? 57h attribute: r/wo default value: 00000000h size: 32 bits bit description 31:16 subsystem identifier (sid) ? r/wo. indicates the subsystem as identified by the vendor. this field is write once and is locked down until a bridge reset occurs (not the pci bus reset). 15:0 subsystem vendor identifier (svid) ? r/wo. indicates the manufacturer of the subsystem. this field is write once and is locked down unti l a bridge reset occurs (not the pci bus reset).
pci-to-pci bridge registers (d30:f0) 434 datasheet
datasheet 435 gigabit lan configuration registers 12 gigabit lan configuration registers 12.1 gigabit lan configuration registers (gigabit lan d25:f0) note: register address locations that are not shown in table 12-1 should be treated as reserved. table 12-1. gigabit lan configuration registers address map (gigabit lan d25:f0) (sheet 1 of 2) offset mnemonic register name default attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h r/wc, ro 08h rid revision identification see register description ro 09h?0bh cc class code 020000h ro 0ch cls cache line size 00h r/w 0dh plt primary latency timer 00h ro 0eh headtyp header type 00h ro 10h?13h mbara memory base address a 00000000h r/w, ro 14h?17h mbarb memory base address b 00000000h r/w, ro 18h?1bh mbarc memory base address c 00000001h r/w, ro 2ch?2dh sid subsystem id see register description ro 2eh?2fh svid subsystem vendor id see register description ro 30h?33h erba expansion rom base address see register description ro 34h capp capabilities list pointer c8h ro 3ch?3dh intr interrupt information see register description r/w, ro 3eh mlmg maximum latency/minimum grant 00h ro c8h?c9h clist1 capabilities list 1 d001h ro cah?cbh pmc pci power ma nagement capability see register description ro cch?cdh pmcs pci power management control and status see register description r/wc, r/w, ro
gigabit lan configuration registers 436 datasheet 12.1.1 vidvendor identi fication register (gigabit land25:f0) address offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 12.1.2 diddevice identi fication register (gigabit land25:f0) address offset: 02h?03h attribute: ro default value: see bit description size: 16 bits cfh dr data register see register description ro d0h?d1h clist2 capabilities list 2 e005h r/wo, ro d2h?d3h mctl message control 0080h r/w, ro d4h?d7h maddl message address low see register description r/w d8h?dbh maddh message address high see register description r/w dch?ddh mdat message data see register description r/w e0h?e1h flrcap function level reset capability 0009h ro e2h?e3h flrclv function level re set capability length and value see register description r/wo, ro e4h?e5h devctrl device control 0000h r/w, ro table 12-1. gigabit lan config uration registers address map (gigabit lan d25:f0) (sheet 2 of 2) offset mnemonic register name default attribute bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. the field may be auto-loaded from the nvm at address 0dh du ring init time depending on the ?load vendor/device id? bit field in nvm word 0ah with a default value of 8086h. bit description 15:0 device id ? ro. this is a 16-bit value assigned to the pch gigabit lan controller. the field may be auto-loaded from the nvm word 0dh during initialization time depending on the "load vendor/device id" bit field in nvm word 0ah.
datasheet 437 gigabit lan configuration registers 12.1.3 pcicmdpci command register (gigabit land25:f0) address offset: 04h?05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. this disables pin-based intx# interrupts on enabled hot- plug and power management events. this bit has no e ffect on msi operation. 0 = internal intx# messages are generated if there is an interrupt for hot-plug or power management and msi is not enabled. 1 = internal intx# messages will not be generated. this bit does not affect inte rrupt forwarding from devices connected to the root port. assert_intx and deassert_intx messages wi ll still be forwarded to the internal interrupt controllers if this bit is set. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (see) ? r/w. 0 = disable 1 = enables the gb lan controller to gene rate an serr# message when psts.sse is set. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? r/w. 0 = disable. 1 = indicates that the device is capable of reporting pa rity errors as a master on the backbone. 5 palette snoop enable (pse) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. 0 = disable. all cycles from the device are master aborted 1 = enable. allows the root port to forwar d cycles onto the backbone from a gigabit lan* device. 1 memory space enable (mse) ? r/w. 0 = disable. memory cycles within the rang e specified by the memory base and limit registers are master aborted on the backbone. 1 = enable. allows memory cycles within th e range specified by the memory base and limit registers can be forwarde d to the gigabi t lan device. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disable. i/o cycles within the range spec ified by the i/o base and limit registers are master aborted on the backbone. 1 = enable. allows i/o cycles within the range specified by the i/o base and limit registers can be forwarded to the gigabit lan device.
gigabit lan configuration registers 438 datasheet 12.1.4 pcistspci status register (gigabit land25:f0) address offset: 06h ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = set when the gb lan controller receiv es a command or data from the backbone with a parity error. this is set even if pcimd.per (d25:f0, bit 6) is not set. 14 signaled system error (sse) ? r/wc. 0 = no system error signaled. 1 = set when the gb lan controller signals a system error to the internal serr# logic. 13 received master abort (rma) ? r/wc. 0 = root port has not received a completion with unsupported re quest status from the backbone. 1 = set when the gbe lan controller receiv es a completion with unsupported request status from the backbone. 12 received target abort (rta) ? r/wc. 0 = root port has not received a completion with completer abort from the backbone. 1 = set when the gb lan controller receiv es a completion with completer abort from the backbone. 11 signaled target abort (sta) ? r/wc. 0 = no target abort received. 1 = set whenever the gb lan controller fo rwards a target abort received from the downstream device onto the backbone. 10:9 devsel# timing status (dev_sts) ? ro. hardwired to 0. 8 master data parity error detected (dped) ? r/wc. 0 = no data parity error received. 1 = set when the gb lan controller receives a completion with a data parity error on the backbone and pcimd.per (d25:f0, bit 6) is set. 7 fast back to back capable (fb2bc) ? ro. hardwired to 0. 6reserved 5 66 mhz capable ? ro. hardwired to 0. 4 capabilities list ? ro. hardwired to 1. indi cates the presence of a capabilities list. 3 interrupt status ? ro. indicates status of ho t-plug and power management interrupts on the root port that re sult in intx# message generation. 0 = interrupt is deasserted. 1 = interrupt is asserted. this bit is not set if msi is enabled. if msi is not enabled, this bit is set regardless of the state of pcicmd.interrupt disable bit (d25:f0:04h:bit 10). 2:0 reserved
datasheet 439 gigabit lan configuration registers 12.1.5 ridrevision identification register (gigabit land25:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 12.1.6 ccclass code register (gigabit land25:f0) address offset: 09h ? 0bh attribute: ro default value: 020000h size: 24 bits 12.1.7 clscache line size register (gigabit land25:f0) address offset: 0ch attribute: r/w default value: 00h size: 8 bits 12.1.8 pltprimary late ncy timer register (gigabit land25:f0) address offset: 0dh attribute: ro default value: 00h size: 8 bits 12.1.9 headtypheade r type register (gigabit land25:f0) address offset: 0eh attribute: ro default value: 00h size: 8 bits bit description 7:0 revision id ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit description 23:0 class code ? ro. identifies the device as an ethernet adapter. 020000h = ethernet adapter. bit description 7:0 cache line size ? r/w. this field is implemented by pci devices as a read write field for legacy compatibility purposes but has no impact on any de vice functionality. bit description 7:0 latency timer (lt) ? ro. hardwired to 0. bit description 7:0 header type (ht) ? ro. 00h = indicates this is a single function device.
gigabit lan configuration registers 440 datasheet 12.1.10 mbaramemory base address register a (gigabit land25:f0) address offset: 10h ? 13h attribute: r/w, ro default value: 00000000h size: 32 bits the internal csr registers and memories are accessed as direct memory mapped offsets from the base address register. sw may only access whole dword at a time. 12.1.11 mbarbmemory base address register b (gigabit land25:f0) address offset: 14h ? 17h attribute: r/w, ro default value: 00000000h size: 32 bits the internal registers that are used to access the lan space in the external flash device. access to these registers are direct memory mapped offsets from the base address register. software may only access a dword at a time. bit description 31:17 base address (ba) r/w . software programs this fiel d with the base address of this region. 16:4 memory size (msize) r/w . memory size is 128 kb. 3 prefetchable memory (pm) ? ro. the gbe lan controller does not implement prefetchable memory. 2:1 memory type (mt) ? ro. set to 00b indicating a 32 bit bar. 0 memory / io space (mios) ? ro. set to 0 indicating a memory space bar. bit description 31:12 base address (ba) r/w . software programs this fiel d with the base address of this region. 11:4 memory size (msize) r/w . memory size is 4 kb. 3 prefetchable memory (pm) ? ro. the gb lan controller does not implement prefetchable memory. 2:1 memory type (mt) ? ro. set to 00b indicating a 32 bit bar. 0 memory / io space (mios) ? ro. set to 0 indicating a memory space bar.
datasheet 441 gigabit lan configuration registers 12.1.12 mbarcmemory base address register c (gigabit land25:f0) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000001h size: 32 bits internal registers, and memories, can be accessed using i/o operations. there are two 4b registers in the i/o mapping window: a ddr reg and data reg. software may only access a dword at a time. 12.1.13 svidsubsystem vendor id register (gigabit land25:f0) address offset: 2ch ? 2dh attribute: ro default value: see bit description size: 16 bits 12.1.14 sidsubsys tem id register (gigabit land25:f0) address offset: 2eh ? 2fh attribute: ro default value: see bit description size: 16 bits 12.1.15 erbaexpansion ro m base address register (gigabit land25:f0) address offset: 30h ? 33h attribute: ro default value: see bit description size: 32 bits bit description 31:5 base address (ba) r/w . software programs this fiel d with the base address of this region. 4:1 i/o size (iosize) ? ro. i/o space size is 32 bytes. 0 memory / i/o space (mios) ? ro. set to 1 indicating an i/o space bar. bit description 15:0 subsystem vendor id (svid) ? ro. this value may be loaded automatically from the nvm word 0ch upon power up depending on the "load subsystem id" bit field in nvm word 0ah. a value of 8086h is default fo r this field upon power up if the nvm does not respond or is not programmed. all func tions are initialized to the same value. bit description 15:0 subsystem id (sid) ? ro. this value may be loaded automatically from the nvm word 0bh upon power up or reset dependin g on the ?load subsystem id? bit field in nvm word 0ah with a default value of 0000h. this value is loadable from nvm word location 0ah. bit description 31:0 expansion rom base address (erba) ? ro. this register is used to define the address and size information for boot-time ac cess to the optional flash memory. if no flash memory exists, this register reports 00000000h.
gigabit lan configuration registers 442 datasheet 12.1.16 cappcapabilities list pointer register (gigabit land25:f0) address offset: 34h attribute: ro default value: c8h size: 8 bits 12.1.17 intrinterrupt information register (gigabit land25:f0) address offset: 3ch?3dh attribute: r/w, ro default value: 0100h size: 16 bits function level reset: no 12.1.18 mlmgmaximum latenc y/minimum grant register (gigabit land25:f0) address offset: 3eh attribute: ro default value: 00h size: 8 bits 12.1.19 clist1capabilities list register 1 (gigabit land25:f0) address offset: c8h?c9h attribute: ro default value: d001h size: 16 bits bit description 7:0 capabilities pointer (ptr) ? ro. indicates that the pointe r for the first entry in the capabilities list is at c8h in configuration space. bit description 15:8 interrupt pin (ipin) ? ro. indicates the interrupt pin driven by the gbe lan controller. 01h = the gbe lan controller implem ents legacy interrupts on inta. 7:0 interrupt line (iline) ? r/w. default = 00h. software written value to indicate which interrupt line (vector) the interrupt is connected to. no hardware action is taken on this register. bit description 7:0 maximum latency/minimum grant (mlmg) ? ro. not used. hardwired to 00h. bit description 15:8 next capability (next) ? ro. value of d0h indicates the location of the next pointer. 7:0 capability id (cid) ? ro. indicates the linked list item is a pci power management register.
datasheet 443 gigabit lan configuration registers 12.1.20 pmcpci power manageme nt capabilities register (gigabit land25:f0) address offset: cah ? cbh attribute: ro default value: see bit descriptions size: 16 bits function level reset: no (bits 15:11 only) bit description 15:11 pme_support (pmes) ? ro. this five-bit field indicates the power states in which the function may assert pm e#. it depend on pm ena and au x-pwr bits in word 0ah in the nvm: these bits are not reset by function level reset. 10 d2_support (d2s) ? ro. the d2 state is not supported. 9 d1_support (d1s) ? ro. the d1 state is not supported. 8:6 aux_current (ac) ? ro. required current defined in the data register. 5 device specific initialization (dsi) ? ro. set to 1. the gbe lan controller requires its device driver to be executed following transition to the d0 un-initialized state. 4 reserved 3 pme clock (pmec) ? ro. hardwired to 0. 2:0 version (vs) ? ro. hardwired to 010b to indicate support for revision 1.1 of the pci power management specification . condition function value pm ena=0 no pme at all states 0000b pm ena & aux-pwr=0 pme at d0 and d3hot 01001b pm ena & aux-pwr=1 pme at d0, d3hot and d3cold 11001b
gigabit lan configuration registers 444 datasheet 12.1.21 pmcspci power mana gement control and status register (gigabit land25:f0) address offset: cch ? cdh attribute: r/wc, r/w, ro default value: see bit description size: 16 bits function level reset: no (bit 8 only) bit description 15 pme status (pmes) ? r/wc. this bit is set to 1 when the function detects a wake-up event independent of the state of the pmee bit. writing a 1 will clear this bit. 14:13 data scale (dsc) ? r/w. this field indicates the sc aling factor to be used when interpreting the value of the data register. for the gbe lan and common functions this fi eld equals 01b (indicating 0.1 watt units) if the pm is enabled in the nvm, and the data_select field is set to 0, 3, 4, 7, (or 8 for function 0). else it equals 00b. for the manageability functions this field eq uals 10b (indicating 0.01 watt units) if the pm is enabled in the nvm, and the data_select fi eld is set to 0, 3, 4, 7. else it equals 00b. 12:9 data select (dsl) ? r/w. this four-bit field is used to select which data is to be reported through the data register (offset cfh) and data_scale fi eld. these bits are writeable only when the power ma nagement is enabled using nvm. 0h = d0 power consumption 3h = d3 power consumption 4h = d0 power dissipation 7h = d3 power dissipation 8h = common power all other values are reserved. 8 pme enable (pmee) ? r/w. if power management is enabled in the nvm, writing a 1 to this register will enable wakeup. if power management is di sabled in the nvm, writing a 1 to this bit has no affect, and will not set the bit to 1. this bit is not reset by function level reset. 7:4 reserved ? returns a value of 0000. 3 no soft reset (nsr) ? ro. defines if the device ex ecuted internal reset on the transition to d0. the lan controller always reports 0 in this field. 2 reserved ? returns a value of 0b. 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the gbe lan controller and to se t a new power state. the values are: 00 = d0 state (default) 01 = ignored 10 = ignored 11 = d3 state (power management must be enables in the nvm or this cycle will be ignored).
datasheet 445 gigabit lan configuration registers 12.1.22 drdata register (gigabit land25:f0) address offset: cfh attribute: ro default value: see bit description size: 8 bits 12.1.23 clist2capabilities list register 2 (gigabit land25:f0) address offset: d0h?d1h attribute: r/wo, ro default value: e005h size: 16 bits function level reset: no (bits 15:8 only) 12.1.24 mctlmessage control register (gigabit land25:f0) address offset: d2h?d3h attribute: r/w, ro default value: 0080h size: 16 bits bit description 7:0 reported data (rd) ? ro. this register is used to report power consumption and heat dissipation. this register is controlled by the data_select field in the pmcs (offset cch, bits 12:9), and the power scale is repo rted in the data_scale field in the pmcs (offset cch, bits 14:13). the data of this field is loaded from the nvm if pm is enabled in the nvm or with a default value of 00h otherwise. bit description 15:8 next capability (next) ? r/wo. value of e0h points to the function level reset capability structure. these bits are not reset by function level reset. 7:0 capability id (cid) ? ro. indicates the linked list item is a message signaled interrupt register. bit description 15:8 reserved 7 64-bit capable (cid) ? ro. set to 1 to indicate th at the gbe lan controller is capable of generating 64-bit message addresses. 6:4 multiple message enable (mme) ? ro. returns 000b to indicate that the gbe lan controller only supports a single message. 3:1 multiple message capable (mmc) ? ro. the gbe lan controller does not support multiple messages. 0 msi enable (msie) ? r/w. 0 = msi generation is disabled. 1 = the gb lan controller will generate ms i for interrupt assertion instead of intx signaling.
gigabit lan configuration registers 446 datasheet 12.1.25 maddlmessage address low register (gigabit land25:f0) address offset: d4h?d7h attribute: r/w default value: see bit description size: 32 bits 12.1.26 maddhmessage address high register (gigabit land25:f0) address offset: d8h?dbh attribute: r/w default value: see bit description size: 32 bits 12.1.27 mdatmessage data register (gigabit land25:f0) address offset: dch?ddh attribute: r/w default value: see bit description size: 16 bits 12.1.28 flrcapfunction level reset capability (gigabit land25:f0) address offset: e0h?e1h attribute: ro default value: 0009h size: 16 bits bit description 31:0 message address low (maddl) ? r/w. written by the system to indicate the lower 32 bits of the address to use for the msi memory write transaction. the lower two bits will always return 0 regardless of the write operation. bit description 31:0 message address high (maddh) ? r/w. written by the system to indicate the upper 32 bits of the address to use for the msi memory write transaction. bit description 31:0 message data (mdat) ? r/w. written by the system to indicate the lower 16 bits of the data written in the msi memory write dw ord transaction. the upper 16 bits of the transaction are written as 0000h. bit description 15:8 next pointer ? ro. this field provides an offset to the next capability item in the capability list. the value of 00h in dicates the last item in the list. 7:0 capability id ? ro. the value of this field depends on the flrcssel bit. 13h = if flrcssel = 0 09h = if flrcssel = 1, indicating vendor specific capability.
datasheet 447 gigabit lan configuration registers 12.1.29 flrclvfunction level re set capability length and version register (gigabit land25:f0) address offset: e2h?e3h attribute: r/wo, ro default value: see description. size: 16 bits function level reset: no (bits 9:8 only when flrcssel = 0) when flrcssel = 0, this register is defined as follows: when flrcssel = 1, this register is defined as follows: 12.1.30 devctrldevice control re gister (gigabit land25:f0) address offset: e4?e5h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:10 reserved 9 function level reset capability ? r/wo. 1 = support for function level reset. this bit is not reset by function level reset. 8 txp capability ? r/wo. 1 = indicates support for the tr ansactions pending (txp) bit. txp must be supported if flr is supported. 7:0 capability length ? ro. the value of this field indi cates the number of bytes of the vendor specific capability as require by the pci specification. it has the value of 06h for the function level reset capability. bit description 15:12 vendor specific capability id ? ro. a value of 2h in th is field identifies this capability as function level reset. 11:8 capability version ? ro. the value of this field indicates the version of the function level reset capability. default is 0h. 7:0 capability length ? ro. the value of this field indi cates the number of bytes of the vendor specific capability as require by the pci specification. it has the value of 06h for the function level reset capability. bit description 15:9 reserved 8 transactions pending (txp) ? r/w. 1 = indicates the controller has issued non-posted requests which have not been completed. 0 = indicates that completions for all no n-posted requests have been received. 7:1 reserved 0 initiate function level reset ? ro. this bit is used to initiate an flt transition. a write of 1 initiates the transition. since hardware must not respond to any cycles until function level reset completion, the valu e read by software from this bit is 0.
gigabit lan configuration registers 448 datasheet
datasheet 449 lpc interface bridge registers (d31:f0) 13 lpc interface bridge registers (d31:f0) the lpc bridge function of the pch resides in pci device 31:function 0. this function contains many other functional units, such as dma and interrupt controllers, timers, power management, system management , gpio, rtc, and lpc configuration registers. registers and functions associated with other functional units are described in their respective sections. 13.1 pci configuration registers (lpc i/fd31:f0) note: address locations that are not shown should be treated as reserved. table 13-1. lpc interface pci register address map (lpc i/fd31:f0) (sheet 1 of 2) offset mnemonic register name default attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0007h r/w, ro 06h?07h pcists pci status 0210h r/wc, ro 08h rid revision identification see register description r/wo 09h pi programming interface 00h ro 0ah scc sub class code 01h ro 0bh bcc base class code 06h ro 0dh plt primary latency timer 00h ro 0eh headtyp header type 80h ro 2ch?2fh ss sub system identifiers 00000000h r/wo 40h?43h pmbase acpi base address 00000001h r/w, ro 44h acpi_cntl acpi control 00h r/w 48h?4bh gpiobase gpio base address 00000001h r/w, ro 4ch gc gpio control 00h r/w 60h?63h pirq[ n ]_rout pirq[a?d] routing control 80808080h r/w 64h sirq_cntl serial irq control 10h r/w, ro 68h?6bh pirq[ n ]_rout pirq[e?h] routing control 80808080h r/w 6ch?6dh lpc_ibdf ioxapic bus:device:function 00f8h r/w 70h?7fh lpc_hnbdf hpet configuration 00f8h r/w 80h lpc_i/o_dec i/o decode ranges 0000h r/w 82h?83h lpc_en lpc i/f enables 0000h r/w 84h?87h gen1_dec lpc i/f generic decode range 1 00000000h r/w
lpc interface bridge registers (d31:f0) 450 datasheet 13.1.1 vidvendor identification register (lpc i/fd31:f0) offset address: 00h ? 01h attribute: ro default value: 8086h size: 16-bit lockable: no power well: core 13.1.2 diddevice identification register (lpc i/fd31:f0) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16-bit lockable: no power well: core 88h?8bh gen2_dec lpc i/f generic decode range 2 00000000h r/w 8ch?8eh gen3_dec lpc i/f generic decode range 3 00000000h r/w 90h?93h gen4_dec lpc i/f generic decode range 4 00000000h r/w 94h?97h ulkmc usb legacy keyboard / mouse control 00002000h ro, r/wc, r/w 98h?9bh lgmr lpc i/f generic memory range 00000000h r/w a0h?cfh power management (see section 13.8.1 ) d0h?d3h bios_sel1 bios select 1 00112233h r/w, ro d4h?d5h bios_sel2 bios select 2 4567h r/w d8h?d9h bios_dec_en1 bios decode enable 1 ffcfh r/w, ro dch bios_cntl bios control 00h r/wlo, r/w, ro e0h?e1h fdcap feature detect ion capability id 0009h ro e2h fdlen feature detection capability length 0ch ro e3h fdver feature detection version 10h ro e4h?e7h fvecidx feature vector index 00000000h r/w e8h?ebh fvecd feature vector data see description ro f0h?f3h rcba root complex base address 00000000h r/w table 13-1. lpc interface pci register addr ess map (lpc i/fd31:f0) (sheet 2 of 2) offset mnemonic register name default attribute bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the pch lpc bridge. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the did register.
datasheet 451 lpc interface bridge registers (d31:f0) 13.1.3 pcicmdpci command re gister (lpc i/fd31:f0) offset address: 04h ? 05h attribute: r/w, ro default value: 0007h size: 16-bit lockable: no power well: core 13.1.4 pcistspci status re gister (lpc i/fd31:f0) offset address: 06h ? 07h attribute: ro, r/wc default value: 0210h size: 16-bit lockable: no power well: core note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15:10 reserved 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. the lpc bridge generate s serr# if this bit is set. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error respon se enable (pere) ? r/w. 0 = no action is taken when detecting a parity error. 1 = enables the pch lpc bridge to respond to parity errors detected on backbone interface. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 memory write and invalidate enable (mwie) ? ro. hardwired to 0. 3 special cycle en able (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? ro. bus masters cannot be disabled. 1 memory space enable (mse) ? ro. memo ry space cannot be disabled on lpc. 0 i/o space enable (iose) ? ro. i/o space cannot be disabled on lpc. bit description 15 detected parity error (dpe) ? r/wc. set when the lpc bridge detects a parity error on the internal backbone. set even if the pcicmd.pere bit (d31:f0:04, bit 6) is 0. 0 = parity error not detected. 1 = parity error detected. 14 signaled system error (sse) ? r/wc. set when the lpc bridge signals a system error to the internal serr# logic. 13 master abort status (rma) ? r/wc. 0 = unsupported request status not received. 1 = the bridge received a completion with unsupported requ est status from the backbone. 12 received target abort (rta) ? r/wc. 0 = completion abort not received. 1 = completion with completion abort received from the backbone.
lpc interface bridge registers (d31:f0) 452 datasheet 13.1.5 ridrevision identification register (lpc i/fd31:f0) offset address: 08h attribute: r/wo default value: see bit description size: 8 bits 13.1.6 piprogramming interface register (lpc i/fd31:f0) offset address: 09h attribute: ro default value: 00h size: 8 bits 11 signaled target abort (sta) ? r/wc. 0 = target abort not generated on the backbone. 1 = lpc bridge generated a completion pa cket with target abort status on the backbone. 10:9 devsel# timing status (dev_sts) ? ro. 01 = medium timing. 8 data parity error detected (dped) ? r/wc. 0 = all conditions listed below not met. 1 = set when all three of the following conditions are met: ? lpc bridge receives a co mpletion packet from the backbone from a previous request, ? parity error has been detected (d31:f0:06, bit 15) ? pcicmd.pere bit (d31:f0 :04, bit 6) is set. 7 fast back to back capable (fbc) ? ro. hardwired to 0. 6 reserved 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4 capabilities list (clist) ? ro. capabi lity list exists on the lpc bridge. 3 interrupt status (is) ? ro. the lpc bridge does not ge nerate interrupts. 2:0 reserved bit description bit description 7:0 revision id (rid) ? r/wo. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit description 7:0 programming interface ? ro.
datasheet 453 lpc interface bridge registers (d31:f0) 13.1.7 sccsub class code register (lpc i/fd31:f0) offset address: 0ah attribute: ro default value: 01h size: 8 bits 13.1.8 bccbase clas s code register (lpc i/fd31:f0) offset address: 0bh attribute: ro default value: 06h size: 8 bits 13.1.9 pltprimary la tency timer register (lpc i/fd31:f0) offset address: 0dh attribute: ro default value: 00h size: 8 bits 13.1.10 headtypheader type register (lpc i/fd31:f0) offset address: 0eh attribute: ro default value: 80h size: 8 bits bit description 7:0 sub class code ? ro. 8-bit value that indicates th e category of bridge for the lpc bridge. 01h = pci-to-isa bridge. bit description 7:0 base class code ? ro. 8-bit value that indicates the type of device for the lpc bridge. 06h = bridge device. bit description 7:3 master latency count (mlc) ? reserved 2:0 reserved bit description 7 multi-function device ? ro. this bit is 1 to indicate a multi-function device. 6:0 header type ? ro. this 7-bit field identifies the header layout of the configuration space.
lpc interface bridge registers (d31:f0) 454 datasheet 13.1.11 sssub system identifier s register (lpc i/fd31:f0) offset address: 2ch ? 2fh attribute: r/wo default value: 00000000h size: 32 bits this register is initialized to logic 0 by th e assertion of pltrst#. this register can be written only once after pltrst# deassertion. 13.1.12 pmbaseacpi base addres s register (lpc i/fd31:f0) offset address: 40h ? 43h attribute: r/w, ro default value: 00000001h size: 32 bit lockable: no usage: acpi, legacy power well: core sets base address for acpi i/o registers, gpio registers and tco i/o registers. these registers can be mapped anywhere in the 64-k i/o space on 128-byte boundaries. bit description 31:16 subsystem id (ssid) ? r/wo. this is written by bios. no hardware action taken on this value. 15:0 subsystem vendor id (ssvid) ? r/wo. this is written by bios. no hardware action taken on this value. bit description 31:16 reserved 15:7 base address ? r/w. this field provides 128 by tes of i/o space for acpi, gpio, and tco logic. this is placed on a 128-byte boundary. 6:1 reserved 0 resource type indicator (rte) ? ro. ha rdwired to 1 to indicate i/o space.
datasheet 455 lpc interface bridge registers (d31:f0) 13.1.13 acpi_cntlacpi control register (lpc i/f d31:f0) offset address: 44h attribute: r/w default value: 00h size: 8 bit lockable: no usage: acpi, legacy power well: core 13.1.14 gpiobasegpio base ad dress register (lpc i/f d31:f0) offset address: 48h?4bh attribute: r/w, ro default value: 00000001h size: 32 bit bit description 7 acpi enable (acpi_en) ? r/w. 0 = disable. 1 = decode of the i/o range pointed to by th e acpi base register is enabled, and the acpi power management fu nction is enabled. no te that the apm power management ranges (b2/b3h) are always en abled and are not affected by this bit. 6:3 reserved 2:0 sci irq select (sci_irq_sel) ? r/w. specifies on which irq the sci will internally appear. if not using the apic, the sci must be routed to irq9?11, and that interrupt is not sharable with the serirq stream, but is shareable with other pci interrupts. if using the apic, the sci can also be mapped to irq20?23, and can be shared with other interrupts. when the interrupt is mapped to apic interrupts 9, 10 or 11, the apic should be programmed for active-high re ception. when the interrupt is mapped to apic interrupts 20 through 23, the apic should be programmed for active-low reception. bits sci map 000b irq9 001b irq10 010b irq11 011b reserved 100b irq20 (only available if apic enabled) 101b irq21 (only available if apic enabled) 110b irq22 (only available if apic enabled) 111b irq23 (only available if apic enabled) bit description 31:16 reserved. always 0. 15:7 base address (ba) ? r/w. provides the 128 bytes of i/o space for gpio. 6:1 reserved. always 0. 0 ro. hardwired to 1 to indicate i/o space.
lpc interface bridge registers (d31:f0) 456 datasheet 13.1.15 gcgpio control register (lpc i/f d31:f0) offset address: 4ch attribute: r/w default value: 00h size: 8 bit bit description 7:5 reserved 4 gpio enable (en) ? r/w. this bit enables/disables decode of the i/o range pointed to by the gpio base address register (d31:f0:48h) and enables the gpio function. 0 = disable. 1 = enable. 3:1 reserved 0 gpio lockdown enable (gle) ? r/w. this bit enables lockdown of the following gpio registers: ? offset 00h: gpio_use_sel ? offset 04h: gp_io_sel ? offset 0ch: gp_lvl ? offset 30h: gpio_use_sel2 ? offset 34h: gp_io_sel2 ? offset 38h: gp_lvl2 ? offset 40h: gpio_use_sel3 ? offset 44h: gp_io_sel3 ? offset 48h: gp_lvl3 ? offset 60h: gp_rst_sel 0 = disable. 1 = enable. when this bit is written from 1-to-0, an smi# is generated, if en abled. this ensures that only smm code can change the above gp io registers after they are locked down.
datasheet 457 lpc interface bridge registers (d31:f0) 13.1.16 pirq[n]_routpirq[a,b,c, d] routing control register (lpc i/fd31:f0) offset address: pirqa?60h, pirqb?61h, attribute: r/w pirqc?62h, pirqd?63h default value: 80h size: 8 bit lockable: no power well: core bit description 7 interrupt routing enable (irqen) ? r/w. 0 = the corresponding pirq is routed to one of the isa-compatible interrupts specified in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 6:4 reserved 3:0 irq routing ? r/w. (isa compatible.) value irq value irq 0000b reserved 1000b reserved 0001b reserved 1001b irq9 0010b reserved 1010b irq10 0011b irq3 1011b irq11 0100b irq4 1100b irq12 0101b irq5 1101b reserved 0110b irq6 1110b irq14 0111b irq7 1111b irq15
lpc interface bridge registers (d31:f0) 458 datasheet 13.1.17 sirq_cntlserial irq control register (lpc i/fd31:f0) offset address: 64h attribute: r/w, ro default value: 10h size: 8 bit lockable: no power well: core bit description 7 serial irq enable (sirqen) ? r/w. 0 = the buffer is input only and internally serirq will be a 1. 1 = serial irqs will be recognized. the se rirq pin will be configured as serirq. 6 serial irq mode select (sirqmd) ? r/w. 0 = the serial irq machine will be in quiet mode. 1 = the serial irq machine wi ll be in continuous mode. note: for systems using quiet mode, this bit sh ould be set to 1 (continuous mode) for at least one frame after coming out of reset before switching back to quiet mode. failure to do so will result in the pch not recognizing serirq interrupts. 5:2 serial irq frame size (sirqsz) ? ro. fixed field that indicates the size of the serirq frame as 21 frames. 1:0 start frame pulse width (sfpw) ? r/w. this is the number of pci clocks that the serirq pin will be driven low by the serial irq machine to signal a start frame. in continuous mode, the pch will drive the start frame for the number of clocks specified. in quiet mode, the pch will drive the start frame for the number of clocks specified minus one, as the first clock was driven by the peripheral. 00 = 4 clocks 01 = 6 clocks 10 = 8 clocks 11 = reserved
datasheet 459 lpc interface bridge registers (d31:f0) 13.1.18 pirq[n]_routpirq[e,f,g, h] routing control register (lpc i/fd31:f0) offset address: pirqe ? 68h, pirqf ? 69h, attribute: r/w pirqg ? 6ah, pirqh ? 6bh default value: 80h size: 8 bit lockable: no power well: core 13.1.19 lpc_ibdfioxapic bus:device:function (lpc i/fd31:f0) offset address: 6ch?6dh attribute: r/w default value: 00f8h size: 16 bit bit description 7 interrupt routing enable (irqen) ? r/w. 0 = the corresponding pirq is routed to on e of the isa-compatible interrupts specified in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may su bsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 6:4 reserved 3:0 irq routing ? r/w. (isa compatible.) value irq value irq 0000b reserved 1000b reserved 0001b reserved 1001b irq9 0010b reserved 1010b irq10 0011b irq3 1011b irq11 0100b irq4 1100b irq12 0101b irq5 1101b reserved 0110b irq6 1110b irq14 0111b irq7 1111b irq15 bit description 15:0 ioxapic bus:device:function (ibdf) ? r/w. this field specifies the bus:device:function that pch?s ioxapi c will be using for the following: ? as the requester id when initiating interrupt messages to the processor. ? as the completer id when responding to the reads targeting the ioxapic?s memory-mapped i/o registers. the 16-bit field comp rises the following: this field defaults to bus 0: device 31: fu nction 0 after reset. bios can program this field to provide a unique bus:device:fun ction number for the internal ioxapic. bits description 15:8 bus number 7:3 device number 2:0 function number
lpc interface bridge registers (d31:f0) 460 datasheet 13.1.20 lpc_hnbdfhpet n bus:device:function (lpc i/fd31:f0) address offset h0bdf 70h?71h h1bdf 72h?73h h2bdf 74h?75h h3bdf 76h?77h h4bdf 78h?79h h5bdf 7ah?7bh h6bdf 7ch?7dh h7bdf 7eh?7fh attribute: r/w default value: 00f8h size: 16 bit bit description 15:0 hpet n bus:device:function (hnbdf) ? r/w. this field specifies the bus:device:function that the pch?s hpet n will be using in the following: ? as the requester id when initiating interrupt messages to the processor ? as the completer id when responding to the reads targeting the corresponding hpet?s memory-mapped i/o registers the 16-bit field comprises the following: this field is default to bus 0: device 31: fu nction 0 after reset. bi os shall program this field accordingly if unique bus:device :function number is required for the corresponding hpet. bits description 15:8 bus number 7:3 device number 2:0 function number
datasheet 461 lpc interface bridge registers (d31:f0) 13.1.21 lpc_i/o_deci/o de code ranges register (lpc i/fd31:f0) offset address: 80h attribute: r/w default value: 0000h size: 16 bit bit description 15:13 reserved 12 fdd decode range ? r/w. determines which range to decode for the fdd port 0 = 3f0h?3f5h, 3f7h (primary) 1 = 370h?375h, 377h (secondary) 11:10 reserved 9:8 lpt decode range ? r/w. this field determines which range to decode for the lpt port. 00 = 378h?37fh and 778h?77fh 01 = 278h?27fh (port 279h is read only) and 678h?67fh 10 = 3bch ?3beh and 7bch?7beh 11 = reserved 7reserved 6:4 comb decode range ? r/w. this field determines which range to decode for the comb port. 000 = 3f8h?3ffh (com1) 001 = 2f8h?2ffh (com2) 010 = 220h?227h 011 = 228h?22fh 100 = 238h?23fh 101 = 2e8h?2efh (com4) 110 = 338h?33fh 111 = 3e8h?3efh (com3) 3reserved 2:0 coma decode range ? r/w. this field determines which range to decode for the coma port. 000 = 3f8h?3ffh (com1) 001 = 2f8h?2ffh (com2) 010 = 220h?227h 011 = 228h?22fh 100 = 238h?23fh 101 = 2e8h?2efh (com4) 110 = 338h?33fh 111 = 3e8h?3efh (com3)
lpc interface bridge registers (d31:f0) 462 datasheet 13.1.22 lpc_enlpc i/f enables register (lpc i/fd31:f0) offset address: 82h?83h attribute: r/w default value: 0000h size: 16 bit power well: core bit description 15:14 reserved 13 cnf2_lpc_en ? r/w. microcontroller enable # 2. 0 = disable. 1 = enables the decoding of the i/o locati ons 4eh and 4fh to the lpc interface. this range is used for a microcontroller. 12 cnf1_lpc_en ? r/w. super i/o enable. 0 = disable. 1 = enables the decoding of the i/o locati ons 2eh and 2fh to the lpc interface. this range is used for super i/o devices. 11 mc_lpc_en ? r/w. microcontroller enable # 1. 0 = disable. 1 = enables the decoding of the i/o location s 62h and 66h to the lpc interface. this range is used for a microcontroller. 10 kbc_lpc_en ? r/w. keyboard enable. 0 = disable. 1 = enables the decoding of the i/o location s 60h and 64h to the lpc interface. this range is used for a microcontroller. 9 gameh_lpc_en ? r/w. high gameport enable 0 = disable. 1 = enables the decoding of the i/o locations 208h to 20fh to the lpc interface. this range is used for a gameport. 8 gamel_lpc_en ? r/w. low gameport enable 0 = disable. 1 = enables the decoding of the i/o locations 200h to 207h to the lpc interface. this range is used for a gameport. 7:4 reserved 3 fdd_lpc_en ? r/w. floppy drive enable 0 = disable. 1 = enables the decoding of the fdd range to the lpc interface. this range is selected in the lpc_fdd/lpt decode range register (d31:f0:80h, bit 12). 2 lpt_lpc_en ? r/w. parallel port enable 0 = disable. 1 = enables the decoding of the lptrange to th e lpc interface. this range is selected in the lpc_fdd/lpt decode range register (d31:f0:80h, bit 9:8). 1 comb_lpc_en ? r/w. com port b enable 0 = disable. 1 = enables the decoding of the comb rang e to the lpc interface. this range is selected in the lpc_com decode rang e register (d31:f0:80h, bits 6:4). 0 coma_lpc_en ? r/w. com port a enable 0 = disable. 1 = enables the decoding of the coma ra nge to the lpc interface. this range is selected in the lpc_com decode rang e register (d31:f0:80h, bits 3:2).
datasheet 463 lpc interface bridge registers (d31:f0) 13.1.23 gen1_declpc i/f generi c decode range 1 register (lpc i/fd31:f0) offset address: 84h ? 87h attribute: r/w default value: 00000000h size: 32 bit power well: core 13.1.24 gen2_declpc i/f generi c decode range 2 register (lpc i/fd31:f0) offset address: 88h ? 8bh attribute: r/w default value: 00000000h size: 32 bit power well: core bit description 31:24 reserved 23:18 generic i/o decode rang e address[7:2] mask ? r/w. a 1 in any bit position indicates that any value in the correspondin g address bit in a rece ived cycle will be treated as a match. the corresponding bit in the address field, belo w, is ignored. the mask is only provided for the lower 6 bits of the dword address, allowing for decoding blocks up to 256 bytes in size. 17:16 reserved 15:2 generic i/o decode range 1 base address (gen1_base) ? r/w. note: the pch does not provide decode down to the word or byte level 1reserved 0 generic decode range 1 enable (gen1_en) ? r/w. 0 = disable. 1 = enable the gen1 i/o range to be forwarded to the lpc i/f bit description 31:24 reserved 23:18 generic i/o decode rang e address[7:2] mask r/w. a 1 in any bit position indicates that any value in the correspondin g address bit in a rece ived cycle will be treated as a match. the corresponding bit in the address field, belo w, is ignored. the mask is only provided for the lower 6 bits of the dword address, allowing for decoding blocks up to 256 bytes in size. 17:16 reserved 15:2 generic i/o decode range 2 base address (gen1_base) ? r/w. note: the pch does not provide decode down to the word or byte level. 1reserved 0 generic decode range 2 enable (gen2_en) ? r/w. 0 = disable. 1 = enable the gen2 i/o range to be forwarded to the lpc i/f
lpc interface bridge registers (d31:f0) 464 datasheet 13.1.25 gen3_declpc i/f generi c decode range 3 register (lpc i/fd31:f0) offset address: 8ch ? 8eh attribute: r/w default value: 00000000h size: 32 bit power well: core 13.1.26 gen4_declpc i/f generi c decode range 4 register (lpc i/fd31:f0) offset address: 90h ? 93h attribute: r/w default value: 00000000h size: 32 bit power well: core bit description 31:24 reserved 23:18 generic i/o decode range address[7:2] mask ? r/w. a 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. the corresponding bit in the address field, belo w, is ignored. the mask is only provided for the lower 6 bits of the dword address, allowing for decoding blocks up to 256 bytes in size. 17:16 reserved 15:2 generic i/o decode range 3 base address (gen3_base) ? r/w. note: the pch does not provide decode down to the word or byte level 1 reserved 0 generic decode range 3 enable (gen3_en) ? r/w. 0 = disable. 1 = enable the gen3 i/o range to be forwarded to the lpc i/f bit description 31:24 reserved 23:18 generic i/o decode range address[7:2] mask ? r/w. a 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. the corresponding bit in the address field, belo w, is ignored. the mask is only provided for the lower 6 bits of the dword address, allowing for decoding blocks up to 256 bytes in size. 17:16 reserved 15:2 generic i/o decode range 4 base address (gen4_base) ? r/w. note: the pch does not provide decode down to the word or byte level 1 reserved 0 generic decode range 4 enable (gen4_en) ? r/w. 0 = disable. 1 = enable the gen4 i/o range to be forwarded to the lpc i/f
datasheet 465 lpc interface bridge registers (d31:f0) 13.1.27 ulkmc usb legacy keyboard / mouse control register (lpc i/fd31:f0) offset address: 94h?97h attribute: ro, r/wc, r/w default value: 00002000h size: 32 bit power well: core bit description 31:16 reserved 15 smi caused by end of pass-through (smibyendps) ? r/wc. this bit indicates if the event occurred. note that even if the co rresponding enable bit is not set in bit 7, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred 14:12 reserved 11 smi caused by port 64 write (trapby64w) ? r/wc. this bit indicates if the event occurred. note that even if the correspon ding enable bit is not set in bit 3, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. note that the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 10 smi caused by port 64 read (trapby64r) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in bit 2, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 9 smi caused by port 60 write (trapby60w) ? r/wc. this bit indicates if the event occurred. note that even if the correspon ding enable bit is not set in bit 1, this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. note that the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 8 smi caused by port 60 read (trapby60r) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 7 smi at end of pass-through enable (smiatendps) ? r/w. this bit enables smi at the end of a pass-through. this can occur if an smi is generated in the middle of a pass-through, and needs to be serviced later. 0 = disable 1 = enable 6 pass through state (pstate) ? ro. 0 = if software needs to reset this bit, it shou ld set bit 5 in all of the host controllers to 0. 1 = indicates that the state machine is in the middle of an a20gate pass-through sequence.
lpc interface bridge registers (d31:f0) 466 datasheet 13.1.28 lgmr lpc i/f gene ric memory range register (lpc i/fd31:f0) offset address: 98h?9bh attribute: r/w default value: 00000000h size: 32 bit power well: core 5 a20gate pass-through enable (a20passen) ? r/w. 0 = disable. 1 = enable. allows a20gate sequence pass-through function. a specific cycle sequence involving writes to port 60h and 64h does not result in the setting of the smi status bits. 4 smi on usb irq enable (usbsmien) ? r/w. 0 = disable 1 = enable. usb interrupt will cause an smi event. 3 smi on port 64 writes enable (64wen) ? r/w. 0 = disable 1 = enable. a 1 in bit 11 will cause an smi event. 2 smi on port 64 reads enable (64ren) ? r/w. 0 = disable 1 = enable. a 1 in bit 10 will cause an smi event. 1 smi on port 60 writes enable (60wen) ? r/w. 0 = disable 1 = enable. a 1 in bit 9 will cause an smi event. 0 smi on port 60 reads enable (60ren) ? r/w. 0 = disable 1 = enable. a 1 in bit 8 will cause an smi event. bit description bit description 31:16 memory address[31:16] ? r/w. this field specifies a 64 kb memory block anywhere in the 4 gb memory space that will be decoded to lpc as standard lpc memory cycle if enabled. 15:1 reserved 0 lpc memory range decode enable ? r/w. when this bit is set to 1, then the range specified in bits 31:16 of this regi ster is enabled fo r decoding to lpc.
datasheet 467 lpc interface bridge registers (d31:f0) 13.1.29 bios_sel1bios select 1 register (lpc i/fd31:f0) offset address: d0h ? d3h attribute: r/w, ro default value: 00112233h size: 32 bits bit description 31:28 bios_f8_idsel ? ro. idsel for two 512-kb bios memory ranges and one 128-kb memory range. this field is fixed at 0000. the idsel programmed in this field addresses the following memory ranges: fff8 0000h?ffff ffffh ffb8 0000h?ffbf ffffh 000e 0000h?000f ffffh 27:24 bios_f0_idsel ? r/w. idsel for two 512-kb bios memory ranges. the idsel programmed in this field addre sses the following memory ranges: fff0 0000h?fff7 ffffh ffb0 0000h?ffb7 ffffh 23:20 bios_e8_idsel ? r/w. idsel for two 512-kb bios memory ranges. the idsel programmed in this field addre sses the following memory ranges: ffe8 0000h?ffef ffffh ffa8 0000h?ffaf ffffh 19:16 bios_e0_idsel ? r/w. idsel for two 512-kb bios memory ranges. the idsel programmed in this field addre sses the following memory ranges: ffe0 0000h?ffe7 ffffh ffa0 0000h?ffa7 ffffh 15:12 bios_d8_idsel ? r/w. idsel for two 512-kb bios memory ranges. the idsel programmed in this field addre sses the following memory ranges: ffd8 0000h?ffdf ffffh ff98 0000h?ff9f ffffh 11:8 bios_d0_idsel ? r/w. idsel for two 512-kb bios memory ranges. the idsel programmed in this field addre sses the following memory ranges: ffd0 0000h?ffd7 ffffh ff90 0000h?ff97 ffffh 7:4 bios_c8_idsel ? r/w. idsel for two 512-kb bios memory ranges. the idsel programmed in this field addre sses the following memory ranges: ffc8 0000h?ffcf ffffh ff88 0000h?ff8f ffffh 3:0 bios_c0_idsel ? r/w. idsel for two 512-kb bios memory ranges. the idsel programmed in this field addre sses the following memory ranges: ffc0 0000h?ffc7 ffffh ff80 0000h?ff87 ffffh
lpc interface bridge registers (d31:f0) 468 datasheet 13.1.30 bios_sel2bios select 2 register (lpc i/fd31:f0) offset address: d4h ? d5h attribute: r/w default value: 4567h size: 16 bits bit description 15:12 bios_70_idsel ? r/w. idsel for two, 1-m bios memory ranges. the idsel programmed in this field addresse s the following memory ranges: ff70 0000h?ff7f ffffh ff30 0000h?ff3f ffffh 11:8 bios_60_idsel ? r/w. idsel for two, 1-m bios memory ranges. the idsel programmed in this field addresse s the following memory ranges: ff60 0000h?ff6f ffffh ff20 0000h?ff2f ffffh 7:4 bios_50_idsel ? r/w. idsel for two, 1-m bios memory ranges. the idsel programmed in this field addresse s the following memory ranges: ff50 0000h?ff5f ffffh ff10 0000h?ff1f ffffh 3:0 bios_40_idsel ? r/w. idsel for two, 1-m bios memory ranges. the idsel programmed in this field addresse s the following memory ranges: ff40 0000h?ff4f ffffh ff00 0000h?ff0f ffffh
datasheet 469 lpc interface bridge registers (d31:f0) 13.1.31 bios_dec_en1bios decode enable register (lpc i/fd31:f0) offset address: d8h ? d9h attribute: r/w, ro default value: ffcfh size: 16 bits bit description 15 bios_f8_en ? ro. this bit enables decoding two 512-kb bios memory ranges, and one 128-kb memory range. 0 = disable 1 = enable the following ranges for the bios fff80000h?ffffffffh ffb80000h?ffbfffffh 14 bios_f0_en ? r/w. this bit enables decoding two 512-kb bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios: fff00000h?fff7ffffh ffb00000h?ffb7ffffh 13 bios_e8_en ? r/w. this bit enables decoding two 512-kb bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios: ffe80000h?ffeffffh ffa80000h?ffafffffh 12 bios_e0_en ? r/w. this bit enables decoding two 512-kb bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios: ffe00000h?ffe7ffffh ffa00000h?ffa7ffffh 11 bios_d8_en ? r/w. this bit enables decoding two 512-kb bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios ffd80000h?ffdfffffh ff980000h?ff9fffffh 10 bios_d0_en ? r/w. this bit enables decoding two 512-kb bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios ffd00000h?ffd7ffffh ff900000h?ff97ffffh 9 bios_c8_en ? r/w. this bit enables decoding two 512-kb bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios ffc80000h?ffcfffffh ff880000h?ff8fffffh 8 bios_c0_en ? r/w. this bit enables decoding two 512-kb bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios ffc00000h?ffc7ffffh ff800000h?ff87ffffh
lpc interface bridge registers (d31:f0) 470 datasheet note: this register effects the bios decode regardless of whether the bios is resident on lpc or spi. the concept of feature space does not apply to spi-based flash. the pch simply decodes these ranges as memory accesses when enabled for the spi flash interface. 7 bios_legacy_f_en ? r/w. this enables the decodi ng of the legacy 64kb range at f0000h?fffffh. 0 = disable. 1 = enable the following legacy ranges for the bios f0000h?fffffh note: the decode for the bios legacy f segment is enabled only by this bit and is not affected by the gen_pmcon_1.ia64_en bit. 6 bios_legacy_e_en ? r/w. this enables the decodi ng of the legacy 64kb range at e0000h?effffh. 0 = disable. 1 = enable the following legacy ranges for the bios e0000h?effffh note: the decode for the bios legacy e segment is enabled only by this bit and is not affected by the gen_pmcon_1.ia64_en bit. 5:4 reserved 3 bios_70_en ? r/w. enables decoding tw o 1-m bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios ff70 0000h?ff7f ffffh ff30 0000h?ff3f ffffh 2 bios_60_en ? r/w. enables decoding tw o 1-m bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios ff60 0000h?ff6f ffffh ff20 0000h?ff2f ffffh 1 bios_50_en ? r/w. enables decoding two 1-m bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios ff50 0000h?ff5f ffffh ff10 0000h?ff1f ffffh 0 bios_40_en ? r/w. enables decoding tw o 1-m bios memory ranges. 0 = disable. 1 = enable the following ranges for the bios ff40 0000h?ff4f ffffh ff00 0000h?ff0f ffffh bit description
datasheet 471 lpc interface bridge registers (d31:f0) 13.1.32 bios_cntlbios control register (lpc i/fd31:f0) offset address: dch attribute: r/wlo, r/w, ro default value: 20h size: 8 bit lockable: no power well: core bit description 7:6 reserved 5 smm bios write protect disable (smm_bwp) ? r/wlo. this bit set defines when the bios region can be written by the host. 0 = bios region smm protection is disabled. the bios region is writable regardless if processors are in smm or not. (set this field to 0 for legacy behavior) 1 = bios region smm protection is enabled. the bios region is not writable unless all processors are in smm. 4 top swap status (tss) ? ro. this bit provides a read-only path to view the state of the top swap bit that is at offset 3414h, bit 0. 3:2 spi read configuration (src) ? r/w. this 2-bit field controls two policies related to bios reads on the spi interface: bit 3 ? prefetch enable bit 2 ? cache disable settings are su mmarized below: 1 bios lock enable (ble) ? r/wlo. 0 = setting the bioswe will not cause smis. 1 = enables setting the bioswe bit to caus e smis. once set, this bit can only be cleared by a pltrst# 0 bios write enable (bioswe) ? r/w. 0 = only read cycles result in firmware hub i/f cycles. 1 = access to the bios space is enabled for both read and write cycles. when this bit is written from a 0 to a 1 and bios lock en able (ble) is also set, an smi# is generated. this ensu res that only smi co de can update bios. bits 3:2 description 00b no prefetching, but caching enabled. 64b demand reads load the read buffer cache with ?valid ? data, allowing repeated code fetches to the same line to complete quickly 01b no prefetching and no caching. one-to-one correspondence of host bios reads to spi cycles. this value can be used to invalidate the cache. 10b prefetching and caching enabled. this mode is used for long sequences of short reads to consecutive addresses (i.e., shadowing). 11b reserved. this is an invalid configuration , caching must be enabled when prefetching is enabled.
lpc interface bridge registers (d31:f0) 472 datasheet 13.1.33 fdcapfeature detect ion capability id register (lpc i/fd31:f0) offset address: e0h?e1h attribute: ro default value: 0009h size: 16 bit power well: core 13.1.34 fdlenfeature detection capability length register (lpc i/fd31:f0) offset address: e2h attribute: ro default value: 0ch size: 8 bit power well: core 13.1.35 fdverfeature dete ction version register (lpc i/fd31:f0) offset address: e3h attribute: ro default value: 10h size: 8 bit power well: core 13.1.36 fvecidxfeature vector index register (lpc i/fd31:f0) offset address: e4h?e7h attribute: r/w default value: 00000000h size: 32 bit power well: core bit description 15:8 next item pointer (next) ? ro. configuration offset of th e next capability item. 00h indicates the last item in the capability list. 7:0 capability id ? ro. indicates a vendor specific capability bit description 7:0 capability length ? ro. indicates the length of this vendor specific capability, as required by pci specification. bit description 7:4 vendor-specific capability id ? ro. a value of 1h in this 4-bit field identifies this capability as feature detectio n type. this field allows so ftware to differentiate the feature detection capability from other vendor-specific capabilities 3:0 capability version ? ro. this field indicates the version of the feature detection capability bit description 31:6 reserved 5:2 index (idx) ? r/w. 4-bit index pointer into the 64-byte feature vector space. data is read from the fvecd register. th is points to a dword register. 1:0 reserved
datasheet 473 lpc interface bridge registers (d31:f0) 13.1.37 fvecdfeature vector data register (lpc i/fd31:f0) offset address: e8h?ebh attribute: ro default value: see description size: 32 bit power well: core 13.1.38 feature vector space 13.1.38.1 fvec0feature vector register 0 fvecidx.idx: 0000b attribute: ro default value: see description size: 32 bit power well: core bit description 31:0 data (data) ? ro. 32-bit data value that is re ad from the feature vector offset pointed to by fvecidx. bit description 31:12 reserved 11:10 usb port count capability ? ro 00 = 14 ports 01 = 12 ports 10 = 10 ports 11 = reserved 9:8 reserved 7 raid capability bit 1 ? ro see bit 5 de scription. 6 sata ports 2 and 3 ? ro 0 = capable 1 = disabled 5 raid capability bit 0? ro raid capability is defined by the combin ation of bits 7 and 5 of this register.: 5 raid capability bit 0? ro raid capability is defined by the combin ation of bits 7 and 5 of this register.: 4reserved 3 sata port 1 6 gb/s capability? ro 0 = capable 1 = disabled bit 7 bit 5 capability 00n o r a i d 01r e s e r v e d 1 0 raid 0/1/5/10 11 raid 0/1/5/10 and intel ? smart response te c h n o l o g y bit 7 bit 5 capability 00n o r a i d 01r e s e r v e d 1 0 raid 0/1/5/10 11r e s e r v e d
lpc interface bridge registers (d31:f0) 474 datasheet 13.1.38.2 fvec1feature vector register 1 fvecidx.idx: 0001b attribute: ro default value: see description size: 32 bit power well: core 13.1.38.3 fvec2feature vector register 2 fvecidx.idx: 0010b attribute: ro default value: see description size: 32 bit power well: core 2 sata port 0 6 gb/s capability? ro 0 = capable 1 = disabled 1 pci interface capability ? ro 0 = capable 1 = disabled 0 reserved bit description bit description 31:23 reserved 22 usb redirect (usbr) capability? ro 0 = capable 1 = disabled 21:0 reserved bit description 31:23 reserved 22 intel ? anti-theft technology capability ? ro 0 = disabled 1 = capable 21 pci express* ports 7 and 8? ro 0 = capable 1 = disabled 20:18 reserved 17 pch integrated graphics support capability ? ro 0 = capable 1 = disabled 16:0 reserved
datasheet 475 lpc interface bridge registers (d31:f0) 13.1.38.4 fvec3feature vector register 3 fvecidx.idx: 0011b attribute: ro default value: see description size: 32 bit power well: core 13.1.39 rcbaroot complex base address register (lpc i/fd31:f0) offset address: f0?f3h attribute: r/w default value: 00000000h size: 32 bit bit description 31:14 reserved 13 data center manageability inte rface (dcmi) capability ? ro 0 = capable 1 = disabled 12 node manager capability ? ro 0 = capable 1 = disabled 11:0 reserved bit description 31:14 base address (ba) ? r/w. base address for the root complex register block decode range. this address is aligned on a 16-kb boundary. 13:1 reserved 0 enable (en) ? r/w. when set, this bit enables the range specified in ba to be claimed as the root complex register block.
lpc interface bridge registers (d31:f0) 476 datasheet 13.2 dma i/o registers table 13-2. dma registers (sheet 1 of 2) port alias register name default type 00h 10h channel 0 dma base and current address undefined r/w 01h 11h channel 0 dma base and current count undefined r/w 02h 12h channel 1 dma base and current address undefined r/w 03h 13h channel 1 dma base and current count undefined r/w 04h 14h channel 2 dma base and current address undefined r/w 05h 15h channel 2 dma base and current count undefined r/w 06h 16h channel 3 dma base and current address undefined r/w 07h 17h channel 3 dma base and current count undefined r/w 08h 18h channel 0?3 dma command undefined wo channel 0?3 dma status undefined ro 0ah 1ah channel 0?3 dma write single mask 000001xxb wo 0bh 1bh channel 0?3 dma channel mode 000000xxb wo 0ch 1ch channel 0?3 dma clear byte pointer undefined wo 0dh 1dh channel 0?3 dma master clear undefined wo 0eh 1eh channel 0?3 dma clear mask undefined wo 0fh 1fh channel 0?3 dma write all mask 0fh r/w 80h 90h reserved page undefined r/w 81h 91h channel 2 dma memory low page undefined r/w 82h ? channel 3 dma memory low page undefined r/w 83h 93h channel 1 dma memory low page undefined r/w 84h?86h 94h?96h reserved pages undefined r/w 87h 97h channel 0 dma memory low page undefined r/w 88h 98h reserved page undefined r/w 89h 99h channel 6 dma memory low page undefined r/w 8ah 9ah channel 7 dma memory low page undefined r/w 8bh 9bh channel 5 dma memory low page undefined r/w 8ch?8eh 9ch?9eh reserved page undefined r/w 8fh 9fh refresh low page undefined r/w c0h c1h channel 4 dma base and current address undefined r/w c2h c3h channel 4 dma base and current count undefined r/w c4h c5h channel 5 dma base and current address undefined r/w c6h c7h channel 5 dma base and current count undefined r/w c8h c9h channel 6 dma base and current address undefined r/w cah cbh channel 6 dma base and current count undefined r/w cch cdh channel 7 dma base and current address undefined r/w ceh cfh channel 7 dma base and current count undefined r/w
datasheet 477 lpc interface bridge registers (d31:f0) 13.2.1 dmabase_cadma base and current address registers i/o address: ch. #0 = 00h; ch. #1 = 02h attribute: r/w ch. #2 = 04h; ch. #3 = 06h size: 16 bit (per channel), ch. #5 = c4h ch. #6 = c8h but accessed in two 8-bit ch. #7 = cch; quantities default value: undefined lockable: no power well: core d0h d1h channel 4?7 dma command undefined wo channel 4?7 dma status undefined ro d4h d5h channel 4?7 dma write single mask 000001xxb wo d6h d7h channel 4?7 dma channel mode 000000xxb wo d8h d9h channel 4?7 dma clear byte pointer undefined wo dah dbh channel 4?7 dma master clear undefined wo dch ddh channel 4?7 dma clear mask undefined wo deh dfh channel 4?7 dma write all mask 0fh r/w table 13-2. dma registers (sheet 2 of 2) port alias register name default type bit description 15:0 base and current address ? r/w. this register determin es the address for the transfers to be performed. the address specified po ints to two separate registers. on writes, the value is stored in the base address register and copied to the current address register. on read s, the value is returned from the current address register. the address increments/decrements in the current address register after each transfer, depending on the mode of the transfer. if the channel is in auto-initialize mode, the current address register will be reloaded from the base address register after a terminal count is generated. for transfers to/from a 16-bit slave (channels 5?7), the address is shifted left one bit location. bit 15 will be shifted into bit 16. the register is accessed in 8 bit quantities. the byte is po inted to by the current byte pointer flip/flop. before acce ssing an address regi ster, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first.
lpc interface bridge registers (d31:f0) 478 datasheet 13.2.2 dmabase_ccdma base an d current count registers i/o address: ch. #0 = 01h; ch. #1 = 03h attribute: r/w ch. #2 = 05h; ch. #3 = 07h size: 16-bit (per channel), ch. #5 = c6h; ch. #6 = cah but accessed in two 8-bit ch. #7 = ceh; quantities default value: undefined lockable: no power well:core 13.2.3 dmamem_lpdma memory low page registers i/o address: ch. #0 = 87h; ch. #1 = 83h ch. #2 = 81h; ch. #3 = 82h ch. #5 = 8bh; ch. #6 = 89h ch. #7 = 8ah; attribute: r/w default value: undefined size: 8-bit lockable: no power well: core bit description 15:0 base and current count ? r/w. this register determines the number of transfers to be performed. the address spec ified points to two separate registers. on writes, the value is stored in the base count register and copied to the current count register. on reads, the value is returned from the current count register. the actual number of transfers is one more than the number programmed in the base count register (that is, programming a count of 4h results in 5 transfers). the count is decrements in the current count register after each transfer. when the value in the register rolls from 0 to ffffh, a terminal count is generated. if the channel is in auto- initialize mode, the current count register will be re loaded from the base count register after a termin al count is generated. for transfers to/from an 8-bit slave (channels 0?3), the count register indicates the number of bytes to be transferred. for tran sfers to/from a 16-bit slave (channels 5?7), the count register indicates the nu mber of words to be transferred. the register is accessed in 8 bit quantities. the byte is po inted to by the current byte pointer flip/flop. before acce ssing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is ac cessed first. bit description 7:0 dma low page (isa address bits [23:16]) ? r/w. this register works in conjunction with the dma controller's cu rrent address register to de fine the complete 24-bit address for the dma channel. this register remains static throughout the dma transfer. bit 16 of this register is ignored when in 16 bit i/o count by words mode as it is replaced by the bit 15 shifted out from the current address register.
datasheet 479 lpc interface bridge registers (d31:f0) 13.2.4 dmacmddma command register i/o address: ch. #0 ? 3 = 08h; ch. #4 ? 7 = d0h attribute: wo default value: undefined size: 8-bit lockable: no power well: core 13.2.5 dmastadma status register i/o address: ch. #0 ? 3 = 08h; ch. #4 ? 7 = d0h attribute: ro default value: undefined size: 8-bit lockable: no power well: core bit description 7:5 reserved. must be 0. 4 dma group arbitration priority ? wo. each channel group is individually assigned either fixed or rotating arbitration priority. at part reset, each group is initialized in fixed priority. 0 = fixed priority to the channel group 1 = rotating priority to the group. 3 reserved. must be 0. 2 dma channel group enable ? wo. both channel groups are enabled following part reset. 0 = enable the dma channel group. 1 = disable. disabling channel group 4?7 al so disables channel group 0?3, which is cascaded through channel 4. 1:0 reserved. must be 0. bit description 7:4 channel request status ? ro. when a valid dma reques t is pending for a channel, the corresponding bit is set to 1. when a dma request is not pending for a particular channel, the corresponding bit is set to 0. the source of the dreq may be hardware or a software request. note that channel 4 is the cascade channel, so the request status of channel 4 is a logical or of the requ est status for chan nels 0 through 3. 4 = channel 0 5 = channel 1 (5) 6 = channel 2 (6) 7 = channel 3 (7) 3:0 channel terminal count status ? ro. when a channel reaches terminal count (tc), its status bit is set to 1. if tc has not been reached, the status bit is set to 0. channel 4 is programmed for cascade, so the tc bi t response for channel 4 is irrelevant: 0 = channel 0 1 = channel 1 (5) 2 = channel 2 (6) 3 = channel 3 (7)
lpc interface bridge registers (d31:f0) 480 datasheet 13.2.6 dma_wrsmskdma write single mask register i/o address: ch. #0 ? 3 = 0ah; ch. #4 ? 7 = d4h attribute: wo default value: 0000 01xx size: 8-bit lockable: no power well: core 13.2.7 dmach_modedma ch annel mode register i/o address: ch. #0 ? 3 = 0bh; ch. #4 ? 7 = d6h attribute: wo default value: 0000 00xx size: 8-bit lockable: no power well: core bit description 7:3 reserved. must be 0. 2 channel mask select ? wo. 0 = enable dreq for the selected channel. the channel is selected through bits [1:0]. therefore, only one ch annel can be masked / unmasked at a time. 1 = disable dreq for the selected channel. 1:0 dma channel select ? wo. these bits select the dma channel mode register to program. 00 = channel 0 (4) 01 = channel 1 (5) 10 = channel 2 (6) 11 = channel 3 (7) bit description 7:6 dma transfer mode ? wo. each dma channel can be programmed in one of four different modes: 00 = demand mode 01 = single mode 10 = reserved 11 = cascade mode 5 address increment/decrement select ? wo. this bit controls address increment/ decrement during dma transfers. 0 = address increment. (default af ter part reset or master clear) 1 = address decrement. 4 autoinitialize enable ? wo. 0 = autoinitialize feature is di sabled and dma transfers term inate on a terminal count. a part reset or master clea r disables autoinitialization. 1 = dma restores the base address and co unt registers to th e current registers following a terminal count (tc). 3:2 dma transfer type ? wo. these bits represent the direction of the dma transfer. when the channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type is irrelevant. 00 = verify ? no i/o or memory strobes generated 01 = write ? data transferred from the i/o devices to memory 10 = read ? data transferred from memory to the i/o device 11 = invalid 1:0 dma channel select ? wo. these bits select the dma ch annel mode register that will be written by bits [7:2]. 00 = channel 0 (4) 01 = channel 1 (5) 10 = channel 2 (6) 11 = channel 3 (7)
datasheet 481 lpc interface bridge registers (d31:f0) 13.2.8 dma clear byte pointer register i/o address: ch. #0 ? 3 = 0ch; ch. #4 ? 7 = d8h attribute: wo default value: xxxx xxxx size: 8-bit lockable: no power well: core 13.2.9 dma master clear register i/o address: ch. #0 ? 3 = 0dh; ch. #4 ? 7 = dah attribute: wo default value: xxxx xxxx size: 8-bit 13.2.10 dma_clmskdma cl ear mask register i/o address: ch. #0 ? 3 = 0eh; ch. #4 ? 7 = dch attribute: wo default value: xxxx xxxx size: 8-bit lockable: no power well: core bit description 7:0 clear byte pointer ? wo. no specific pattern. comm and enabled with a write to the i/o port address. writing to th is register initializes the byte pointer flip/flop to a known state. it clears the internal latch used to address the uppe r or lower byte of the 16-bit address and word count registers. the latch is also cleared by part reset and by the master clear command. this command prec edes the first acce ss to a 16-bit dma controller register. the first access to a 16-bit register will then access the significant byte, and the second access automatically accesses the most significant byte. bit description 7:0 master clear ? wo. no specific pattern. enabled wi th a write to the port. this has the same effect as the hardware reset. the command, status , request, and byte pointer flip/flop registers are cleared and the mask register is set. bit description 7:0 clear mask register ? wo. no specific pattern. command enabled with a write to the port.
lpc interface bridge registers (d31:f0) 482 datasheet 13.2.11 dma_wrmskdma writ e all mask register i/o address: ch. #0 ? 3 = 0fh; ch. #4 ? 7 = deh attribute: r/w default value: 0000 1111 size: 8-bit lockable: no power well: core 13.3 timer i/o registers bit description 7:4 reserved. must be 0. 3:0 channel mask bits ? r/w. this register permits all four channels to be simultaneously enabled/disabled instea d of enabling/disabling each channel individually, as is the case with the mask re gister ? write single mask bit. in addition, this register has a read path to allow the status of the channel mask bits to be read. a channel's mask bit is automatically set to 1 when the current byte/word count register reaches terminal count (unless the channel is in auto-initialization mode). setting the bit(s) to a 1 disa bles the corresponding dreq(s). setting the bit(s) to a 0 enables the corresponding dreq(s). bits [3:0] are set to 1 upon part reset or master clear. when read, bits [3:0] indicate the dma channel [3:0] ([7:4]) mask status. bit 0 = channel 0 (4)1 = masked, 0 = not masked bit 1 = channel 1 (5)1 = masked, 0 = not masked bit 2 = channel 2 (6)1 = masked, 0 = not masked bit 3 = channel 3 (7)1 = masked, 0 = not masked note: disabling channel 4 also disables channe ls 0?3 due to the cascade of channels 0?3 through channel 4. port aliases register name default value type 40h 50h counter 0 interval time st atus byte format 0xxxxxxxb ro counter 0 counter access port undefined r/w 41h 51h counter 1 interval time st atus byte format 0xxxxxxxb ro counter 1 counter access port undefined r/w 42h 52h counter 2 interval time st atus byte format 0xxxxxxxb ro counter 2 counter access port undefined r/w 43h 53h timer control word undefined wo timer control word register xxxxxxx0b wo counter latch command x0h wo
datasheet 483 lpc interface bridge registers (d31:f0) 13.3.1 tcwtimer control word register i/o address: 43h attribute: wo default value: all bits undefined size: 8 bits this register is programmed prior to any counter being accessed to specify counter modes. following part reset, the control words for each register are undefined and each counter output is 0. each timer must be programmed to bring it into a known state. there are two special commands that can be issued to the counters through this register, the read back command and th e counter latch command. when these commands are chosen, several bits within this register are redefined. these register formats are described as follows: bit description 7:6 counter select ? wo. the counter selection bits select the counter the control word acts upon as shown below. the read back command is selected when bits[7:6] are both 1. 00 = counter 0 select 01 = counter 1 select 10 = counter 2 select 11 = read back command 5:4 read/write select ? wo. these bits are the read/w rite control bits. the actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb 3:1 counter mode selection ? wo. these bits select one of six possible modes of operation for the selected counter. 0 binary/bcd countdown select ? wo. 0 = binary countdown is used. the la rgest possible binary count is 2 16 1 = binary coded decimal (bcd) count is us ed. the largest possible bcd count is 10 4 bit value mode 000b mode 0 out signal on end of count (=0) 001b mode 1 hardware retriggerable one- shot x10b mode 2 rate generator (divide by n counter) x11b mode 3 square wave output 100b mode 4 software triggered strobe 101b mode 5 hardware triggered strobe
lpc interface bridge registers (d31:f0) 484 datasheet rdbk_cmdread back command the read back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. status and/or count may be latched in any or all of the counters by selecting the counter during the register write. the count and status remain latched until read, and further latch commands are ignored until the count is read. both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to 0. if both are latched, the first read op eration from that counter returns the latched status. the next one or two reads, depend ing on whether the counter is programmed for one or two byte counts, returns the latched count. subsequent reads return an unlatched count. ltch_cmdcounter latch command the counter latch command latches the current count value. this command is used to insure that the count read from the counter is accurate. the count value is then read from each counter's count register through the counter ports access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2). the count must be read according to the programmed format; that is, if the counter is programmed for two byte counts, two bytes must be read. the tw o bytes do not have to be read one right after the other (read, write, or programm ing operations for other counters may be inserted between the reads). if a counter is latched once and then latched again before the count is read, the second counter latch command is ignored. bit description 7:6 read back command. must be 11 to select the read back command 5 latch count of selected counters . 0 = current count value of the se lected counters will be latched 1 = current count will not be latched 4 latch status of selected counters . 0 = status of the selected counters will be latched 1 = status will not be latched 3 counter 2 select . 1 = counter 2 count and/or status will be latched 2 counter 1 select . 1 = counter 1 count and/or status will be latched 1 counter 0 select . 1 = counter 0 count and/or status will be latched. 0 reserved. must be 0. bit description 7:6 counter selection. these bits select the counter for la tching. if ?11? is written, then the write is interpreted as a read back command. 00 = counter 0 01 = counter 1 10 = counter 2 5:4 counter latch command . 00 = selects the counter latch command. 3:0 reserved. must be 0.
datasheet 485 lpc interface bridge registers (d31:f0) 13.3.2 sbyte_fmtinterval timer status byte format register i/o address: counter 0 = 40h, counter 1 = 41h, attribute: ro counter 2 = 42h size: 8 bits per counter default value: bits[6:0] undefined, bit 7=0 each counter's status byte can be read follo wing a read back command. if latch status is chosen (bit 4=0, read back command) as a read back option for a given counter, the next read from the counter's counter access ports register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns th e status byte. the status byte returns the following: bit description 7 counter out pin state ? ro. 0 = out pin of the counter is also a 0 1 = out pin of the counter is also a 1 6 count register status ? ro. this bit indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). the exact time this happens depends on the counter mode, but until the count is loaded into the counting element (ce), the count value will be incorrect. 0 = count has been transf erred from cr to ce and is available for reading. 1 = null count. count has not been transferre d from cr to ce and is not yet available for reading. 5:4 read/write selection status ? ro. these reflect the re ad/write selection made through bits[5:4] of the control register. th e binary codes returned during the status read match the codes used to progra m the counter read/write selection. 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb 3:1 mode selection status ? ro. these bits return the counter mode programming. the binary code returned matche s the code used to program the counter mode, as listed under the bit function above. 000 = mode 0 ? out signal on end of count (=0) 001 = mode 1 ? hardware retriggerable one-shot x10 = mode 2 ? rate generator (divide by n counter) x11 = mode 3 ? square wave output 100 = mode 4 ? software triggered strobe 101 = mode 5 ? hardware triggered strobe 0 countdown type status ? ro. this bit reflects the current countdown type. 0 = binary countdown 1 = binary coded decimal (bcd) countdown.
lpc interface bridge registers (d31:f0) 486 datasheet 13.3.3 counter access ports register i/o address: counter 0 ? 40h, counter 1 ? 41h, attribute: r/w counter 2 ? 42h default value: all bits undefined size: 8 bit 13.4 8259 interrupt controller (pic) registers 13.4.1 interrupt controller i/o map the interrupt controller registers are located at 20h and 21h for the master controller (irq 0?7), and at a0h and a1h for the slave controller (irq 8?13). these registers have multiple functions, depending upon the data written to them. ta b l e 1 3 - 3 shows the different register possibilities for each address. note: refer to note addressing active-low interrupt sources in 8259 interrupt controllers section ( chapter 5.8 ). bit description 7:0 counter port ? r/w. each counter port address is used to program the 16-bit count register. the order of progra mming, either lsb only, msb only, or lsb then msb, is defined with the interval counter control regi ster at port 43h. the counter port is also used to read the current count from the coun t register, and return the status of the counter programming follow ing a read back command. table 13-3. pic registers port aliases register name default value type 20h 24h, 28h, 2ch, 30h, 34h, 38h, 3ch master pic icw1 init. cmd. word 1 undefined wo master pic ocw2 op ctrl. word 2 001xxxxxb wo master pic ocw3 op ctrl. word 3 x01xxx10b wo 21h 25h, 29h, 2dh, 31h, 35h, 39h, 3dh master pic icw2 init. cmd. word 2 undefined wo master pic icw3 init. cmd. word 3 undefined wo master pic icw4 init. cmd. word 4 01h wo master pic ocw1 op ctrl. word 1 00h r/w a0h a4h, a8h, ach, b0h, b4h, b8h, bch slave pic icw1 init. cmd. word 1 undefined wo slave pic ocw2 op ctrl. word 2 001xxxxxb wo slave pic ocw3 op ctrl. word 3 x01xxx10b wo a1h a5h, a9h, adh, b1h, b5h, b9h, bdh slave pic icw2 init. cmd. word 2 undefined wo slave pic icw3 init. cmd. word 3 undefined wo slave pic icw4 init. cmd. word 4 01h wo slave pic ocw1 op ctrl. word 1 00h r/w 4d0h ? master pic edge/level triggered 00h r/w 4d1h ? slave pic edge/level triggered 00h r/w
datasheet 487 lpc interface bridge registers (d31:f0) 13.4.2 icw1initialization command word 1 register offset address: master controller ? 20h attribute: wo slave controller ? a0h size: 8 bit /controller default value: all bits undefined a write to initialization command word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. the interrupt mask register is cleared. 2. irq7 input is assigned priority 7. 3. the slave mode address is set to 7. 4. special mask mode is cleared and status read is set to irr. once this write occurs, the controller expects writes to icw2, icw3, and icw4 to complete the initialization sequence. bit description 7:5 icw/ocw select ? wo. these bits are mcs-85 specific, and not needed. 000 = should be programmed to ?000? 4 icw/ocw select ? wo. 1 = this bit must be a 1 to select icw1 and enable the icw2, icw3, and icw4 sequence. 3 edge/level bank select (ltim) ? wo. disabled. replac ed by the edge/level triggered control registers (elc r, d31:f0:4d0h, d31:f0:4d1h). 2 adi ? wo. 0 = ignored for the pch. should be programmed to 0. 1 single or cascade (sngl) ? wo. 0 = must be programmed to a 0 to indicate two controllers operating in cascade mode. 0 icw4 write required (ic4) ? wo. 1 = this bit must be programmed to a 1 to indicate that icw4 needs to be programmed.
lpc interface bridge registers (d31:f0) 488 datasheet 13.4.3 icw2initialization command word 2 register offset address: master controller ? 21h attribute: wo slave controller ? a1h size: 8 bit /controller default value: all bits undefined icw2 is used to initialize the interrupt contro ller with the five most significant bits of the interrupt vector address. the value programmed for bits[7:3] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each irq on the controller. typical isa icw2 values are 08h for the master controller and 70h for the slave controller. 13.4.4 icw3master controller initialization command word 3 register offset address: 21h attribute: wo default value: all bits undefined size: 8 bits bit description 7:3 interrupt vector base address ? wo. bits [7:3] define the base address in the interrupt vector table for the interrupt routines as sociated with each interrupt request level input. 2:0 interrupt request level ? wo. when writing icw2, these bits should all be 0. during an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. this is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second inta# cycle. the code is a three bit binary code: code master interrupt slave interrupt 000b irq0 irq8 001b irq1 irq9 010b irq2 irq10 011b irq3 irq11 100b irq4 irq12 101b irq5 irq13 110b irq6 irq14 111b irq7 irq15 bit description 7:3 0 = these bits must be programmed to 0. 2 cascaded interrupt controller irq connection ? wo. this bit indicates that the slave controller is cascaded on irq2. when irq8#?irq15 is asserted, it goes through the slave controller?s priority resolver. the slave controller?s intr output onto irq2. irq2 then goes through the master controlle r?s priority solver. if it wins, the intr signal is asserted to the processor, and th e returning interrupt ac knowledge returns the interrupt vector for the slave controller. 1 = this bit must always be programmed to a 1. 1:0 0 = these bits must be programmed to 0.
datasheet 489 lpc interface bridge registers (d31:f0) 13.4.5 icw3slave controller initialization command word 3 register offset address: a1h attribute: wo default value: all bits undefined size: 8 bits 13.4.6 icw4initialization command word 4 register offset address: master controller ? 021h attribute:wo slave controller ? 0a1h size: 8 bits default value: 01h bit description 7:3 0 = these bits must be programmed to 0. 2:0 slave identification code ? wo. these bits are compared against the slave identification code broadcast by the master co ntroller from the trailing edge of the first internal inta# pulse to the trailing edge of the second internal inta# pulse. these bits must be programmed to 02h to match the co de broadcast by the master controller. when 02h is broadcast by the master contro ller during the inta# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector. bit description 7:5 0 = these bits must be programmed to 0. 4 special fully nested mode (sfnm) ? wo. 0 = should normally be disabled by writing a 0 to this bit. 1 = special fully nested mode is programmed. 3 buffered mode (buf) ? wo. 0 = must be programmed to 0 for the pch. this is non-buffered mode. 2 master/slave in buffered mode ? wo. not used. 0 = should always be programmed to 0. 1 automatic end of interrupt (aeoi) ? wo. 0 = this bit should normally be programmed to 0. this is the normal end of interrupt. 1 = automatic end of interrupt (aeoi) mode is programmed. 0 microprocessor mode ? wo. 1 = must be programmed to 1 to indicate that the controller is operating in an intel architecture-based system.
lpc interface bridge registers (d31:f0) 490 datasheet 13.4.7 ocw1operational contro l word 1 (interrupt mask) register offset address: master controller ? 021h attribute: r/w slave controller ? 0a1h size: 8 bits default value: 00h 13.4.8 ocw2operational control word 2 register offset address: master controller ? 020h attribute: wo slave controller ? 0a0h size: 8 bits default value: bit[4:0]=undefined, bit[7:5]=001 following a part reset or icw initialization, the controller enters the fully nested mode of operation. non-specific eoi without rotation is the default. both rotation mode and specific eoi mode are disabled following initialization. bit description 7:0 interrupt request mask ? r/w. when a 1 is written to any bit in this register, the corresponding irq line is masked. when a 0 is written to any bit in this register, the corresponding irq mask bit is cleared, and in terrupt requests will again be accepted by the controller. masking irq2 on the master controller will also mask the interrupt requests from the slave controller. bit description 7:5 rotate and eoi codes (r, sl, eoi) ? wo. these three bits control the rotate and end of interrupt modes and combinations of the two. 000 = rotate in auto eoi mode (clear) 001 = non-specific eoi command 010 = no operation 011 = *specific eoi command 100 = rotate in auto eoi mode (set) 101 = rotate on non-specific eoi command 110 = *set priority command 111 = *rotate on specific eoi command *l0 ? l2 are used 4:3 ocw2 select ? wo. when selecting ocw2, bits 4:3 = 00 2:0 interrupt level select (l2, l1, l0) ? wo. l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active. a simple binary code, outlined below, selects the channel for the command to act upon. when the sl bit is inactive, these bits do not have a defined function; prog ramming l2, l1 and l0 to 0 is sufficient in this case. code interrupt level code interrupt level 000b irq0/8 000b irq4/12 001b irq1/9 001b irq5/13 010b irq2/10 010b irq6/14 011b irq3/11 011b irq7/15
datasheet 491 lpc interface bridge registers (d31:f0) 13.4.9 ocw3operational co ntrol word 3 register offset address: master controller ? 020h attribute: wo slave controller ? 0a0h size: 8 bits default value: bit[6,0]=0, bit[7,4:2]=undefined, bit[5,1]=1 bit description 7 reserved. must be 0. 6 special mask mode (smm) ? wo. 1 = the special mask mode can be used by an interrupt service ro utine to dynamically alter the system priority structure while th e routine is executing, through selective enabling/disabling of the other channel's mask bits. bit 5, the esmm bit, must be set for this bit to have any meaning. 5 enable special mask mode (esmm) ? wo. 0 = disable. the smm bit becomes a ?don't care?. 1 = enable the smm bit to set or reset the special mask mode. 4:3 ocw3 select ? wo. when selecting ocw3, bits 4:3 = 01 2 poll mode command ? wo. 0 = disable. poll command is not issued. 1 = enable. the next i/o read to the interru pt controller is treated as an interrupt acknowledge cycle. an encoded byte is driv en onto the data bus, representing the highest priority level requesting service. 1:0 register read command ? wo. these bits provide cont rol for reading the in-service register (isr) and the interrupt request regi ster (irr). when bit 1=0, bit 0 will not affect the register read sele ction. when bit 1=1, bit 0 selects the register status returned following an ocw3 read. if bit 0=0, the irr will be read. if bit 0=1, the isr will be read. following icw initialization, th e default ocw3 port address read will be ?read irr?. to retain the curre nt selection (read isr or read irr), always write a 0 to bit 1 when programming this register. the se lected register can be read repeatedly without reprogramming ocw3. to select a new status register, ocw3 must be reprogrammed prior to attempting the read. 00 = no action 01 = no action 10 = read irq register 11 = read is register
lpc interface bridge registers (d31:f0) 492 datasheet 13.4.10 elcr1master controller edge/level trig gered register offset address: 4d0h attribute: r/w default value: 00h size: 8 bits in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high level. the cascade channel, irq2, the heart beat timer (irq 0), and the keyboard controller (irq1), cannot be put into level mode. bit description 7 irq7 ecl ? r/w. 0 = edge 1 = level 6 irq6 ecl ? r/w. 0 = edge 1 = level. 5 irq5 ecl ? r/w. 0 = edge 1 = level 4 irq4 ecl ? r/w. 0 = edge 1 = level 3 irq3 ecl ? r/w. 0 = edge 1 = level 2:0 reserved. must be 0.
datasheet 493 lpc interface bridge registers (d31:f0) 13.4.11 elcr2slave controller e dge/level triggered register offset address: 4d1h attribute: r/w default value: 00h size: 8 bits in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high level. the real time clock, irq8#, and the floating point error interru pt, irq13, cannot be programmed for level mode. bit description 7 irq15 ecl ? r/w. 0 = edge 1 = level 6 irq14 ecl ? r/w. 0 = edge 1 = level 5 reserved. must be 0. 4 irq12 ecl ? r/w. 0 = edge 1 = level 3 irq11 ecl ? r/w. 0 = edge 1 = level 2 irq10 ecl ? r/w. 0 = edge 1 = level 1 irq9 ecl ? r/w. 0 = edge 1 = level 0 reserved. must be 0.
lpc interface bridge registers (d31:f0) 494 datasheet 13.5 advanced programmabl e interrupt controller (apic) 13.5.1 apic register map the apic is accessed using an indirect addressing scheme. two registers are visible by software for manipulation of most of the apic registers. these registers are mapped into memory space. the address bits 19:12 of the address range are programmable through bits 7:0 of oic register (chipset config registers:offset 31feh) the registers are shown in table 13-4 . ta b l e 1 3 - 5 lists the registers which can be accessed within the apic using the index register. when accessing these registers, accesses must be done one dword at a time. for example, software should never access byte 2 from the data register before accessing bytes 0 and 1. the hardware will not attempt to recover from a bad programming model in this case. 13.5.2 indindex register memory address fec _ _ 0000h attribute: r/w default value: 00h size: 8 bits the index register will select which apic indirect register to be manipulated by software. the selector values for the indirect registers are listed in ta b l e 1 3 - 5 . software will program this register to select the desired apic internal register table 13-4. apic direct registers address mnemonic register name size type fec_ _0000h ind index 8 bits r/w fec_ _0010h dat data 32 bits r/w fec_ _0040h eoir eoi 32 bits wo table 13-5. apic indirect registers index mnemonic register name size type 00 id identification 32 bits r/w 01 ver version 32 bits ro 02?0f ? reserved ? ro 10?11 redir_tbl0 redirection table 0 64 bits r/w, ro 12?13 redir_tbl1 redirection table 1 64 bits r/w, ro ... ... ... ... ... 3e?3f redir_tbl23 redirection table 23 64 bits r/w, ro 40?ff ? reserved ? ro bit description 7:0 apic index ? r/w. this is an 8-bit pointer into the i/o apic register table.
datasheet 495 lpc interface bridge registers (d31:f0) 13.5.3 datdata register memory address fec _ _ 0000h attribute: r/w default value: 00000000h size: 32 bits this is a 32-bit register specifying the data to be read or written to the register pointed to by the index register. this register can only be accessed in dword quantities. 13.5.4 eoireoi register memory address fec _ _ 0000h attribute: r/w default value: n/a size: 32 bits the eoi register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. when a write is issued to this register, th e i/o apic will check the lower 8 bits written to this register, and compare it with the vector field for each entry in the i/o redirection table. when a match is found, the remote_irr bit (index offset 10h, bit 14) for that i/o redirection entry will be cleared. note: if multiple i/o redirection entries, for any reason, assign the same vector for more than one interrupt input, each of those entr ies will have the remote_irr bit reset to 0. the interrupt, which was prematurely reset, will not be lost because if its input remained active when the remote_irr bit wa s cleared, the interrupt will be reissued and serviced at a later time. note that only bits 7:0 are actually used. bits 31:8 are ignored by the pch. note: to provide for future expansion, the processo r should always write a value of 0 to bits 31:8. bit description 7:0 apic data ? r/w. this is a 32-bit register for the da ta to be read or written to the apic indirect register ( figure 13-5 ) pointed to by the index register (memory address fec0_0000h). bit description 31:8 reserved. to provide for future expansion, th e processor should always write a value of 0 to bits 31:8. 7:0 redirection entry clear ? wo. when a write is issued to this register, the i/o apic will check this field, and compare it with the vector field for each entry in the i/o redirection table. when a match is found, th e remote_irr bit for that i/o redirection entry will be cleared.
lpc interface bridge registers (d31:f0) 496 datasheet 13.5.5 ididentification register index offset: 00h attribute: r/w default value: 00000000h size: 32 bits the apic id serves as a physical name of the apic. the apic bus arbitration id for the apic is derived from its i/o apic id. this register is reset to 0 on power-up reset. 13.5.6 verversion register index offset: 01h attribute: ro, r/wo default value: 00170020h size: 32 bits each i/o apic contains a hardwired version register that identifies different implementation of apic and their versions . the maximum redirection entry information also is in this register, to let software kn ow how many interrupt are supported by this apic. bit description 31:28 reserved 27:24 apic id ? r/w. software must program th is value before using the apic. 23:16 reserved 15 scratchpad bit. 14:0 reserved bit description 31:24 reserved 23:16 maximum redirection entries (mre) ? r/wo. this is the entry number (0 being the lowest entry) of the highest entry in the redirection table. it is equal to the number of interrupt input pins minus one and is in the range 0 through 239. in the pch this field is hardwired to 17h to indicate 24 interrupts. bios must write to this field after pltrst# to lockdown the value. this allows bios to utilize some of the entries for its own pu rpose and thus advertising fewer ioxapic redirection entries to the os. 15 pin assertion register supported (prq) ? ro. indicate that the ioxapic does not implement the pin assertion register. 14:8 reserved 7:0 version (vs) ? ro. this is a version number that identifies the implementation version.
datasheet 497 lpc interface bridge registers (d31:f0) 13.5.7 redir_tblredirection table register index offset: 10h ? 11h (vector 0) through attribute:r/w, ro 3e ? 3fh (vector 23) default value: bit 16 = 1. all other bits undefined size: 64 bits each, (accessed as two 32 bit quantities) the redirection table has a dedicated entry for each interrupt input pin. the information in the redirection table is used to translate the interrupt manifestation on the corresponding interrupt pin into an apic message. the apic will respond to an edge triggered in terrupt as long as the interrupt is held until after the acknowledge cycle has begun. once the interrupt is detected, a delivery status bit internally to the i/o apic is set. the state machine will step ahead and wait for an acknowledgment from the apic unit th at the interrupt message was sent. only then will the i/o apic be able to recognize a new edge on that interrupt pin. that new edge will only result in a new invocation of the handler if its acceptance by the destination apic causes the interrupt request register bit to go from 0 to 1. (in other words, if the interrupt was not already pending at the destination.) bit description 63:56 destination ? r/w. if bit 11 of this entry is 0 (physical), then bits 59:56 specifies an apic id. in this case, bits 63:59 shou ld be programmed by software to 0. if bit 11 of this entry is 1 (logical), then bits 63:56 specify the logical destination address of a set of processors. 55:48 extended destination id (edid) ? ro. these bits are sent to a local apic only when in processor system bus mode. th ey become bits 11:4 of the address. 47:17 reserved 16 mask ? r/w. 0 = not masked: an edge or level on this in terrupt pin results in the delivery of the interrupt to the destination. 1 = masked: interrupts are not delivered nor held pending. setting this bit after the interrupt is accepted by a local apic has no effect on that inte rrupt. this behavior is identical to the device withdrawing th e interrupt before it is posted to the processor. it is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been ac cepted by a local apic unit but before the interrupt is dispen sed to the processor. 15 trigger mode ? r/w. this field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = edge triggered. 1 = level triggered. 14 remote irr ? r/w. this bit is used for level triggered interrupts; its meaning is undefined for edge tr iggered interrupts. 0 = reset when an eoi message is received from a local apic. 1 = set when local apic/s accept the level interrupt sent by the i/o apic. 13 interrupt input pin polarity ? r/w. this bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = active high. 1 = active low. 12 delivery status ? ro. this field contains the current st atus of the delivery of this interrupt. writes to th is bit have no effect. 0 = idle. no activity for this interrupt. 1 = pending. interrupt has been inject ed, but delivery is not complete.
lpc interface bridge registers (d31:f0) 498 datasheet note: delivery mode encoding: 000 = fixed. deliver the si gnal on the intr signal of all proces sor cores listed in the destination. trigger mode can be edge or level. 001 = lowest priority. deliver the signal on th e intr signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. trigger mode can be edge or level. 010 = smi (system management interrupt). requir es the interrupt to be programmed as edge triggered. the vector information is ignored but must be programmed to all 0s for future compatibility: not supported 011 = reserved 100 = nmi. deliver the signal on the nmi signal of all processor cores listed in the destination. vector information is ignored. nmi is treated as an edge triggered inte rrupt even if it is programmed as level triggered. for proper oper ation this redirection table entry must be programmed to edge triggered. the nmi delivery mode does not set the rirr bit. if the redirection table is incorrectly set to level, the loop count will co ntinue counting through the redirection table addresses. once the co unt for the nmi pin is reached again, the interrupt will be sent again: not supported 101 = init. deliver the signal to all processor co res listed in the destination by asserting the init signal. all addressed local apics will assu me their init state. init is always treated as an edge triggered interrupt even if programmed as level triggered. for proper operation this redirection table entry must be programmed to edge triggered. the init delivery mode does not set the rirr bit. if the redirection table is incorrectly set to level, the loop count will continue counting throug h the redirection table addresses. once the count for the init pin is reached again, the interrupt will be sent again: not supported 110 = reserved 111 = extint. deliver the signal to the intr signal of all processor cores listed in the destination as an interrupt that originated in an exte rnally connected 8259a compatible interrupt controller. the inta cycle that corresponds to this extint delivery will be routed to the external controller that is expected to supply the vector. requires the interrupt to be programmed as edge triggered. 11 destination mode ? r/w. this field dete rmines the interpretati on of the destination field. 0 = physical. destination apic id is identified by bits 59:56. 1 = logical. destinations are identified by matching bit 63:56 with the logical destination in the destination format regi ster and logical destination register in each local apic. 10:8 delivery mode ? r/w. this field specifies how the apics listed in the destination field should act upon reception of this signal. certain delivery modes will only operate as intended when used in conjunction with a specific trigger mode. these encodings are listed in the note below: 7:0 vector ? r/w. this field contains the interrupt vector for this interrupt. values range between 10h and feh. bit description
datasheet 499 lpc interface bridge registers (d31:f0) 13.6 real time clock registers 13.6.1 i/o register address map the rtc internal registers and ram are or ganized as two banks of 128 bytes each, called the standard and extended banks. the first 14 bytes of the standard bank contain the rtc time and date information along with four registers, a?d, that are used for configuration of the rtc. the extended bank contains a full 128 bytes of battery backed sram, and will be accessible even when the rtc module is disabled (using the rtc configuration register). registers a?d do not physically exist in the ram. all data movement between the host processor and the real-time clock is done through registers mapped to the standard i/o space. the register map is shown in ta b l e 1 3 - 6 . notes: 1. i/o locations 70h and 71h are the standard legacy location for the real-time clock. the map for this bank is shown in ta b l e 1 3 - 7 . locations 72h and 73h are for accessing the extended ram. the extended ram bank is also accessed using an indexed scheme. i/o address 72h is used as the address pointer and i/o address 73h is used as the data register. index addresses above 127h are not valid. if the extended ram is not needed, it may be disabled. 2. software must preserve the value of bit 7 at i/o addresses 70h and 74h. when writing to this address, software must first read the value, and then write the same value for bit 7 during the sequential address write. note that port 70h is not directly readable. the only way to read this register is through alt access mode. although rtc index bits 6:0 are readable fr om port 74h, bit 7 will always return 0. if the nmi# enable is not changed during normal operation, software can alternatively read this bit once and then retain the value for all subsequent writes to port 70h. table 13-6. rtc i/o registers i/o locations if u128e bit = 0 function 70h and 74h also alias to 72h and 76h real- time clock (standard ram) index register 71h and 75h also alias to 73h and 77h real-time clock (standard ram) target register 72h and 76h extended ram index register (if enabled) 73h and 77h extended ram targ et register (if enabled)
lpc interface bridge registers (d31:f0) 500 datasheet 13.6.2 indexed registers the rtc contains two sets of indexed registers that are accessed using the two separate index and target registers (70/71h or 72/73h), as shown in table 13-7 . table 13-7. rtc (standard) ram bank index name 00h seconds 01h seconds alarm 02h minutes 03h minutes alarm 04h hours 05h hours alarm 06h day of week 07h day of month 08h month 09h year 0ah register a 0bh register b 0ch register c 0dh register d 0eh?7fh 114 bytes of user ram
datasheet 501 lpc interface bridge registers (d31:f0) 13.6.2.1 rtc_regaregister a rtc index: 0a attribute: r/w default value: undefined size: 8-bit lockable: no power well: rtc this register is used for general configuratio n of the rtc functions. none of the bits are affected by rsmrst# or an y other pch reset signal. bit description 7 update in progress (uip) ? r/w. this bit may be monitored as a status flag. 0 = the update cycle will not start for at least 488 s. the time, calendar, and alarm information in ram is always av ailable when the uip bit is 0. 1 = the update is soon to occur or is in progress. 6:4 division chain select (dv[2:0]) ? r/w. these three bits cont rol the divider chain for the oscillator, and are not affected by rsmrst# or any other reset signal. 010 = normal operation 11x = divider reset 101 = bypass 15 stages (test mode only) 100 = bypass 10 stages (test mode only) 011 = bypass 5 stages (test mode only) 001 = invalid 000 = invalid 3:0 rate select (rs[3:0]) ? r/w. selects one of 13 taps of the 15 stage divider chain. the selected tap can generate a periodic interrupt if the pi e bit is set in register b. otherwise this tap will set the pf flag of register c. if the periodic interrupt is not to be used, these bits should all be set to 0. rs3 corresponds to bit 3. 0000 = interrupt never toggles 0001 = 3.90625 ms 0010 = 7.8125 ms 0011 = 122.070 s 0100 = 244.141 s 0101 = 488.281 s 0110 = 976.5625 s 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms
lpc interface bridge registers (d31:f0) 502 datasheet 13.6.2.2 rtc_regbregister b (general configuration) rtc index: 0bh attribute: r/w default value: u0u00uuu (u: undefined) size: 8-bit lockable: no power well: rtc bit description 7 update cycle inhibit (set) ? r/w. enables/inhibits the update cycles. this bit is not affected by rsmrst# nor any other reset signal. 0 = update cycle occurs normally once each second. 1 = a current update cy cle will abort and subs equent update cycles will not occur until set is returned to 0. when set is one, the bios may in itialize time and calendar bytes safely. note: this bit should be set then cleared ea rly in bios post after each powerup directly after coin-cell battery insertion. 6 periodic interrupt enable (pie) ? r/w. this bit is cleare d by rsmrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occur with a time base set with the rs bits of register a. 5 alarm interrupt enable (aie) ? r/w. this bit is cleared by rtcrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occur when the af is set by an alarm match from the update cycle. an alarm can occur once a se cond, one an hour, once a day, or one a month. 4 update-ended interrupt enable (uie) ? r/w. this bit is cleared by rsmrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occur when the update cycle ends. 3 square wave enable (sqwe) ? r/w. this bit serves no function in the pch. it is left in this register bank to provide compatibility with the motorola 146818b. the pch has no sqw pin. this bit is cleared by rsmrst#, but not on any other reset. 2 data mode (dm) ? r/w. this bit specifies either binary or bcd data representation. this bit is not affected by rs mrst# nor any other reset signal. 0 = bcd 1 = binary 1 hour format (hourform) ? r/w. this bit indicates the hour byte format. this bit is not affected by rsmrst# no r any other reset signal. 0 = twelve-hour mode. in twelve-hour mode, the seventh bit represents am as 0 and pm as one. 1 = twenty-four hour mode. 0 daylight savings legacy software support (dslsws) ? r/w. daylight savings functionality is no longer su pported. this bit is used to maintain legacy software support and has no associated functionality. if buc.dso bit is set, the dslsws bit continues to be r/w.
datasheet 503 lpc interface bridge registers (d31:f0) 13.6.2.3 rtc_regcregister c (flag register) rtc index: 0ch attribute: ro default value: 00u00000 (u: undefined) size: 8-bit lockable: no power well: rtc writes to register c have no effect. 13.6.2.4 rtc_regdregister d (flag register) rtc index: 0dh attribute: r/w default value: 10uuuuuu (u: undefined) size: 8-bit lockable: no power well: rtc bit description 7 interrupt request flag (irqf) ? ro. irqf = (pf * pie) + (af * aie) + (uf *ufe). this bit also causes the rtc interrupt to be asserted. this bit is cleared upon rsmrst# or a read of register c. 6 periodic interrupt flag (pf) ? ro. this bit is cleared upon rsmrst# or a read of register c. 0 = if no taps are specified using the rs bits in register a, this flag will not be set. 1 = periodic interrupt flag will be 1 when the ta p specified by the rs bits of register a is 1. 5 alarm flag (af) ? ro. 0 = this bit is cleared upon rtcrst# or a read of register c. 1 = alarm flag will be set after all alarm values match the current time. 4 update-ended flag (uf) ? ro. 0 = the bit is cleared upon rsmrst# or a read of register c. 1 = set immediately following an update cycle for each second. 3:0 reserved. will always report 0. bit description 7 valid ram and time bit (vrt) ? r/w. 0 = this bit should always be written as a 0 fo r write cycle, however it will return a 1 for read cycles. 1 = this bit is hardwired to 1 in the rtc power well. 6 reserved. this bit always returns a 0 and should be set to 0 for write cycles. 5:0 date alarm ? r/w. these bits store the date of month alarm value. if set to 000000b, then a don?t care state is as sumed. the host must configure the date alarm for these bits to do anything, yet they can be written at any time. if the date alarm is not enabled, these bits will return 0s to mimic the functionality of the motorola 146818b. these bits are not affected by any reset assertion.
lpc interface bridge registers (d31:f0) 504 datasheet 13.7 processor interface registers ta b l e 1 3 - 8 is the register address map for the processor interface registers. 13.7.1 nmi_scnmi status and control register i/o address: 61h attribute: r/w, ro default value: 00h size: 8-bit lockable: no power well: core table 13-8. processor interfac e pci register address map offset mnemonic register name default a ttribute 61h nmi_sc nmi status and control 00h r/w, ro 70h nmi_en nmi enable 80h r/w (special) 92h port92 fast a20 and init 00h r/w f0h coproc_err coprocessor error 00h wo cf9h rst_cnt reset control 00h r/w bit description 7 serr# nmi source status (serr#_nmi_sts) ? ro. 1 = bit is set if a pci agent detected a syst em error and pulses th e pci serr# line and if bit 2 (pci_serr_en) is cleared. this interrupt source is enabled by setting bit 2 to 0. to reset the interrupt, set bit 2 to 1 and then set it to 0. when writing to port 61h, this bit must be 0. note: this bit is set by any of the pch internal sources of serr; this includes serr assertions forwarded from the secondary pci bus, errors on a pci express* port, or other inte rnal functions that generate serr#. 6 iochk# nmi source status (iochk_nmi_sts) ? ro. 1 = bit is set if an lpc agent (using serirq) asserted iochk# and if bit 3 (iochk_nmi_en) is cleared. th is interrupt source is enabled by setting bit 3 to 0. to reset the interrupt, set bit 3 to 1 and then set it to 0. when writing to port 61h, this bit must be a 0. 5 timer counter 2 out status (tmr2_out_sts) ? ro. this bit reflects the current state of the 8254 counter 2 output. counter 2 must be programmed following any pci reset for this bit to have a de terminate value. when writing to port 61h, this bit must be a 0. 4 refresh cycle toggle (ref_toggle) ? ro. this signal toggles from either 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles would occur. when writing to port 61h, this bit must be a 0. 3 iochk# nmi enable (iochk_nmi_en) ? r/w. 0 = enabled. 1 = disabled and cleared. 2 pci serr# enable (pci_serr_en) ? r/w. 0 = serr# nmis are enabled. 1 = serr# nmis are di sabled and cleared. 1 speaker data enable ( spkr_dat_en) ? r/w. 0 = spkr output is a 0. 1 = spkr output is equivalent to the counter 2 out signal value. 0 timer counter 2 enable (tim_cnt2_en) ? r/w. 0 = disable 1 = enable
datasheet 505 lpc interface bridge registers (d31:f0) 13.7.2 nmi_ennmi enable (and real time clock index) register i/o address: 70h attribute: r/w (special) default value: 80h size: 8-bit lockable: no power well: core note: the rtc index field is write-only for normal operation. this field can only be read in alt- access mode. note, however, that this register is aliased to port 74h (documented in table 13-6 ), and all bits are readable at that address. 13.7.3 port92fast a20 and init register i/o address: 92h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core 13.7.4 coproc_errcoprocessor error register i/o address: f0h attribute: wo default value: 00h size: 8-bits lockable: no power well: core bits description 7 nmi enable (nmi_en) ? r/w (special). 0 = enable nmi sources. 1 = disable all nmi sources. 6:0 real time clock index address (rtc_indx) ? r/w (special). th is data goes to the rtc to select which register or cmos ram address is being accessed. bit description 7:2 reserved 1 alternate a20 gate (alt_a20_gate) ? r/w. this bit is or?d with the a20gate input signal to generate a20m# to the processor. 0 = a20m# signal can po tentially go active. 1 = this bit is set when init# goes active. 0 init_now ? r/w. when this bit transitions from a 0 to a 1, the pch will force init# active for 16 pci clocks. bits description 7:0 coprocessor error (coproc_err) ? wo. any value written to this register will cause ignne# to go active, if ferr# had ge nerated an internal irq13. for ferr# to generate an internal irq13, the coproc_err_en bit must be 1.
lpc interface bridge registers (d31:f0) 506 datasheet 13.7.5 rst_cntreset control register i/o address: cf9h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core bit description 7:4 reserved 3 full reset (full_rst) ? r/w. this bit is used to de termine the states of slp_s3#, slp_s4#, and slp_s5# after a cf9 hard rese t (sys_rst =1 and rst_cpu is set to 1), after pwrok going low (with rsmrst# high), or after two tco timeouts. 0 = pch will keep slp_s3#, slp_s4# and slp_s5# high. 1 = pch will drive slp_s3#, slp_s4# and slp_s5# low for 3?5 seconds. note: when this bit is set, it also causes the full power cycle (slp_s3/4/5# assertion) in response to sys_reset#, pwrok# , and watchdog timer reset sources. 2 reset processor (rst_cpu) ? r/w. when this bit transitions from a 0 to a 1, it initiates a hard or soft reset, as determined by the sys_rst bit (bit 1 of this register). 1 system reset (sys_rst) ? r/w. this bit is used to determine a hard or soft reset to the processor. 0 = when rst_cpu bit goes from 0 to 1, the pch performs a soft reset by activating init# for 16 pci clocks. 1 = when rst_cpu bit goes from 0 to 1, the pch performs a hard reset by activating pltrst# and sus_stat# active for a mini mum of about 1 milliseconds. in this case, slp_s3#, slp_s4# and slp_s5# state (assertion or deassertion) depends on full_rst bit setting. the pch main powe r well is reset when this bit is 1. it also resets the resume we ll bits (except for those noted throughout this document). 0 reserved
datasheet 507 lpc interface bridge registers (d31:f0) 13.8 power management registers the power management registers are distributed within the pci device 31: function 0 space, as well as a separate i/o range. each register is described below. unless otherwise indicated, bits are in the main (core) power well. bits not explicitly defined in each register are assumed to be reserved. when writing to a reserved bit, the value should always be 0. software should not attempt to use the value read from a reserved bit, as it may not be consistently 1 or 0. 13.8.1 power management pc i configuration registers (pmd31:f0) table 13-9 shows a small part of the configuration space for pci device 31: function 0. it includes only those registers dedicated for power management. some of the registers are only used for legacy power management schemes. table 13-9. power management pci register address map (pmd31:f0) offset mnemonic register name default a ttribute a0h?a1h gen_pmcon_1 general power management configuration 1 0000h r/w, r/wo, ro a2h gen_pmcon_2 general power management configuration 2 00h r/w, r/wc, ro a4h?a5h gen_pmcon_3 general power management configuration 3 4206h r/w, r/wc a6h gen_pmcon_lo ck general power management configuration lock 00h ro, r/wlo a9h cir4 chipset initialization register 4 03h r/w aah bm_break_en_2 bm_break_e n register #2 00h r/w, ro abh bm_break_en bm_break_en register 00h r/w ach?afh pmir power management initialization 00000000h r/w, r/wlo b8h?bbh gpi_rout gpi route control 00000000h r/w
lpc interface bridge registers (d31:f0) 508 datasheet 13.8.1.1 gen_pmcon_1general pm configuration 1 register (pmd31:f0) offset address: a0h attribute: r/w, ro, r/wo default value: 0000h size: 16-bit lockable: no usage: acpi, legacy power well: core bit description 15:12 reserved 11 gen_pmcon_1 field 1 ? r/w. bios must program this field to 1b. 10 bios_pci_exp_en ? r/w. this bit acts as a glob al enable for the sci associated with the pci express* ports. 0 = the various pci express ports and processor cannot cause the pci_exp_sts bit to go active. 1 = the various pci express ports and proc essor can cause the pci_exp_sts bit to go active. 9 pwrbtn_lvl ? ro. this bit indicates the curre nt state of the pwrbtn# signal. 0 = low. 1 = high. 8:5 reserved 4 smi_lock ? r/wo. when this bit is set, writes to the glb_smi_en bit (pmbase + 30h, bit 0) will have no effect. once the smi_lock bit is set, writes of 0 to smi_lock bit will have no effect (that is, once set, this bit can only be cleared by pltrst#). 3 (mobile only) reserved 3 (desktop only) pseudo clkrun_en(pseudo_clkrun_en) ? r/w. 0 = disable. 1 = enable internal clkrun# logic to al low dmi pll shutdown. this bit has no impact on state of external clkrun# pin. notes: 1. pseudo_clkrun_en bit does not result in stp_pci# assertion to actually stop the external pciclk. 2. this bit should be set mutually exclusive with the clkrun_en bit. setting pseudo_clkrun_en in a mobile sku could result in unspecified behavior. 2 (mobile only) pci clkrun# enable (clkrun_en) ? r/w. 0 = disable. pch drives the clkrun# signal low. 1 = enable clkrun# logic to control the system pci clock using the clkrun# and stp_pci# signals. notes: 1. when the slp_en# bit is set, the pch drives the clkrun# signal low regardless of the state of the clkrun_en bit. this ensures that the pci and lpc clocks continue running during a transition to a sleep state. 2. this bit should be set mutually exclusive with the pseudo_clkrun_en bit. setting clkrun_en in a non-mobile sku could result in unspecified behavior. 2 (desktop only) reserved
datasheet 509 lpc interface bridge registers (d31:f0) 13.8.1.2 gen_pmcon_2general pm configuration 2 register (pmd31:f0) offset address: a2h attribute: r/w, ro, r/wc default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: resume 1:0 periodic smi# rate select (per_smi_sel) ? r/w. set by software to control the rate at which periodic smi# is generated. 00 = 64 seconds 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds bit description bit description 7 dram initialization bit ? r/w. this bit does not affect hardware functionality in any way. bios is expected to set this bit prior to starting the dram initialization sequence and to clear this bit after completing the dram initialization sequence. bios can detect that a dram initialization sequence was interru pted by a reset by re ading this bit during the boot sequence. ? if the bit is 1, then the dram initialization was interrupted. ? this bit is reset by the as sertion of the rsmrst# pin. 6 reserved 5 memory placed in self-refresh (mem_sr) ? ro. ? if the bit is 1, dram should have rema ined powered and held in self-refresh through the last power state transition (tha t is, the last time the system left s0). ? this bit is reset by the as sertion of the rsmrst# pin. 4 system reset status (srs) ? r/wc. software clears this bit by writing a 1 to it. 0 = sys_reset# button not pressed. 1 = pch sets this bit when the sys_reset# button is pressed. bi os is expected to read this bit and clear it, if it is set. notes: 1. this bit is also reset by rsmrst# and cf9h resets. 2. the sys_reset# is implemented in th e main power well. this pin must be properly isolated and masked to preven t incorrectly setting this suspend well status bit. 3 processor thermal trip status (cts) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when pltrst# is inacti ve and thrmtrip# goes active while the system is in an s0 or s1 state. notes: 1. this bit is also reset by rsmrst#, an d cf9h resets. it is not reset by the shutdown and reboot associated with the processor thrmtrip# event. 2. the cf9h reset in the desc ription refers to cf9h ty pe core well reset which includes sys_reset#, pwrok/sys_pw rok low, smbus hard reset, tco timeout. this type of reset will clear cts bit.
lpc interface bridge registers (d31:f0) 510 datasheet 13.8.1.3 gen_pmcon_3general pm configuration 3 register (pmd31:f0) offset address: a4h attribute: r/w, r/wc default value: 4206h size: 16-bit lockable: no usage: acpi, legacy power well: rtc, sus 2 minimum slp_s4# assertion width violation status ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = hardware sets this bit when the slp_s4 # assertion width is less than the time programmed in the slp_s4# minimum assertion width fi eld (d31:f0:offset a4h:bits 5:4). the pch begi ns the timer when slp_s4# is asserted during s4/s5 entry or when the rsmrst# input is deas serted during sus we ll power-up. note that this bit is functional regardless of the values in the slp_s4# assertion stretch enable (d31:f0:offset a4h:bit 3) and in th e disable slp stretching after sus well power up (d31:f0:offset a4h:bit 12). note: this bit is reset by the a ssertion of the rsmrst# pin, but can be set in some cases before the default value is readable. 1 sys_pwrok failure (syspwr_flr) ? r/wc. 0 = this bit will be cleared only be software writing a 1 back to the bit or by sus well power loss. 1 = this bit will be set any time sys_pwro k drops unexpectedly when the system was in s0 or s1 state. 0 pwrok failure (pwrok_flr) ? r/wc. 0 = this bit will be cleared only be software writing a 1 back to the bit or by sus well power loss. 1 = this bit will be set any time pwrok goes low wh en the system was in s0 or s1 state. note: see chapter 5.13.10.3 for more details about th e pwrok pin functionality. bit description bit description 15 pme b0 s5 disable (pme_b0_s5_dis) ? r/w. when set to 1, this bit blocks wake events from pme_b0_sts in s5, regardless of the state of pme_b0_en. when cleared (default), wake events from pme_b0_sts are allowed in s5 if pme_b0_en = 1. wakes from power states other than s5 are not affected by this policy bit. the net effect of setting pme_b0_s5_dis = '1' is described by the truth table below: y = wake; n = don't wake; b0 = pme_b0_en; ov = wol enable override this bit is cleared by the rtcrst# pin. b0/ov s1/s3/s4 s5 00 n n 01 n y (lan only) 11 y (all pme b0 sources) y (lan only) 10 y (all pme b0 sources) n
datasheet 511 lpc interface bridge registers (d31:f0) 14 sus well power failure (sus_pwr_flr) ? r/wc. 0 = software writes a 1 to this bit to clear it. 1 = this bit is set to '1' whenever sus well power is lost, as indicated by rsmrst# assertion. this bit is in the sus well, and defaults to '1' based on rsmrst# assertion (not cleared by any type of reset). 13 wol enable overri de (wol_en_ovrd) ? r/w. 0 = wol policies are determined by pmeb 0 enable bit and appropriate lan status bits 1 = enable appropriately configured integrated lan to wake the system in s5 only regardless of the value in the pme_ b0_en bit in the gpe0_en register. this bit is cleared by the rtcrst# pin. 12 disable slp stretching after sus well power up (dis_slp_strch_sus_up) ? r/w 0 = enables stretching on slp signals after sus power failure as enabled and configured in other fields. 1 = disables stretching on slp signals wh en powering up after a sus well power loss. regardless of the st ate of the slp_s4# assertion stretch enable (bit 3). this bit is cleared by the rtcrst# pin. notes: 1. this field is ro when the slp stre tching policy lock-down bit is set. 2. if this bit is cleared, slp stretch ti mers start on sus well power up (the pch has no ability to count stretch time while the sus well is powered down). 3. this policy bit has a different effect on slp_sus# stretc hing than on the other slp_* pins since slp_sus# is the control signal for one of the scenarios where sus well power is lost (deep s4/s5). the effect of setting this bit to '1' on: ? slp_s3# and slp_s4# stretching: disabled after any sus power loss. ? slp_sus# stretching: disabled after g3, but no impact on deep s4/s5. 11:10 slp_s3# minimum assertion width r/w. this 2-bit value indicates the minimum assertion width of the slp_s3# si gnal to ensure th at the main power supplies have been fully power-cycled. valid settings are: 00 = 60 us 01 = 1 ms 10 = 50 ms 11 = 2 s this bit is cleared by the rsmrst# pin. note: this field is ro when the slp stre tching policy lock-down bit is set. 9 general reset status (gen_rst_sts) ? r/wc. this bit is set by hardware whenever pltrst# asserts for any reason other than going into a software- entered sleep state (using pm1cnt.slp_en write) or a suspend well power failure (rsmrst# pin assertion). bios is expected to consult and then write a 1 to clear this bit during the boot flow before de termining what action to take based on pm1_sts.wak_sts = 1. if gen_rst_sts = 1, the cold reset boot path should be followed rather than the resume path, regardless of the setting of wak_sts. this bit is cleared by the rsmrst# pin. bit description
lpc interface bridge registers (d31:f0) 512 datasheet 8 slp_lan# default value (slp_lan_default) ? r/w. this bit specifies the value to drive on the slp_lan# pin when in sx/moff and intel me fw nor host bios has configured slp_lan#. when this bit is set to 1 slp_lan# will default to be driven high, when set to 0 slp_la n# will default to be driven low. this bit will always determine slp_lan# behavior when in s4/s5/moff after sus power loss, in s5/moff after a host partit ion reset with power down and when in s5/moff due to an unconditional power down. this bit is cleared by rtcrst#. 7:6 swsmi_rate_sel ? r/w. this field indicates wh en the swsmi timer will time out. valid values are: 00 = 1.5 ms 0.6 ms 01 = 16 ms 4 ms 10 = 32 ms 4 ms 11 = 64 ms 4 ms these bits are not cleared by an y type of reset except rtcrst#. 5:4 slp_s4# minimum assertion width ? r/w. this field indicates the minimum assertion width of the slp_s4# signal to ensure that the dram modules have been safely power-cycled. valid values are: 11 = 1 second 10 = 2 seconds 01 = 3 seconds 00 = 4 seconds this value is used in two ways: 1. if the slp_s4# assertion width is ever shorter than this time, a status bit is set for bios to read when s0 is entered. 2. if enabled by bit 3 in this register , the hardware will prevent the slp_s4# signal from deasserting wi thin this minimum time period after asserting. rtcrst# forces this field to the conservative default state (00b). notes: 1. this field is ro when the slp stre tching policy lock-down bit is set. 2. note that the logic that measures this time is in the suspend power well. therefore, when leaving a g3 or deep s4/s5 state, the minimum time is measured from the deassertion of the internal suspend well reset (unless the ?disable slp stretching after sus well power up? bit is set). 3 slp_s4# assertion stretch enable ? r/w. 0 = the slp_s4# minimum assertion time is defined in power sequencing and reset signal timings table. 1 = the slp_s4# signal minimally assert for the time specified in bits 5:4 of this register. this bit is cleared by rtcrst#. note: this bit is ro when th e slp stretching policy lock-down bit is set. 2 rtc power status (rtc_pwr_sts) ? r/w. this bit is set when rtcrst# indicates a weak or missing battery. the bit is not cleared by any type of reset. the bit will remain set until the so ftware clears it by writing a 0 back to this bit position. bit description
datasheet 513 lpc interface bridge registers (d31:f0) note: rsmrst# is sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by the pch. 1 power failure (pwr_flr) ? r/wc. this bit is in the deeps4/s5 well and defaults to 1 based on dpwr ok deassertion (not cleared by any type of reset). 0 = indicates that the trickle current has not failed since the last time the bit was cleared. software clears this bit by writing a 1 to it. 1 = indicates that the trickle current (from the main battery or trickle supply) was removed or failed. note: clearing cmos in a pch-based platform can be done by using a jumper on rtcrst# or gpi. implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. 0 afterg3_en ? r/w. this bit determines what state to go to when power is re- applied after a power failure (g3 state). th is bit is in the rtc well and is only cleared by rtcr st# assertion. 0 = system will return to s0 stat e (boot) after power is re-applied. 1 = system will return to the s5 state (excep t if it was in s4, in which case it will return to s4). in the s5 state, the only enabled wake event is the power button or any enabled wake event th at was preserved through the power failure. bit description
lpc interface bridge registers (d31:f0) 514 datasheet 13.8.1.4 gen_pmcon_lockgeneral power management configuration lock register offset address: a6h attribute: ro, r/wlo default value: 00h size: 8-bit lockable: no usage: acpi power well: core 13.8.1.5 cir4chipset initializ ation register 4 (pmd31:f0) offset address: a9h attribute: r/w default value: 03h size: 8-bit lockable: no usage: acpi, legacy power well: core 13.8.1.6 bm_break_en_2 register #2 (pmd31:f0) offset address: aah attribute: r/w, ro default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: core bit description 7:3 reserved 2 slp stretching policy lock -down (slp_str_pol_lock) ? r/wlo. when set to 1, this bit locks down the disable slp stretching after sus well power up, slp_s3# minimum assertion width, slp_s4# minimum assertion width, slp_s4# assertion stretch enable bi ts in the gen_pmcon_3 regi ster, making them read- only. this bit becomes locked when a value of 1b is written to it. writes of 0 to this bit are always ignored. this bit is cleared by platform reset. 1 acpi_base_lock ? r/wlo. when set to 1, this bit locks down the acpi base address register (abase) at offset 40h. the base address field becomes read- only. this bit becomes locked when a value of 1b is written to it. writes of 0 to this bit are always ignored. once locked by writing 1, the only way to clear this bit is to perform a platform reset. 0 reserved bit description 7:0 cir4 field 1 ? r/w. bios must program this field to 47h. bit description 7:1 reserved 0 sata3 break enable (sata3_break_en) ? r/w. 0 = sata3 traffic will not cause bm_sts to be set. 1 = sata3 traffic will cause bm_sts to be set.
datasheet 515 lpc interface bridge registers (d31:f0) 13.8.1.7 bm_break_en register (pmd31:f0) offset address: abh attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: core bit description 7 storage break enable (storage_break_en) ? r/w. 0 = serial ata traffic will not cause bm_sts to be set. 1 = serial ata traffic will cause bm_sts to be set. 6 pcie_break_en ? r/w. 0 = pci express* traffic will not cause bm_sts to be set. 1 = pci express traffic will cause bm_sts to be set. 5 pci_break_en ? r/w. 0 = pci traffic will not cause bm_sts to be set. 1 = pci traffic will cause bm_sts to be set. 4:3 reserved 2 ehci_break_en ? r/w. 0 = ehci traffic will not cause bm_sts to be set. 1 = ehci traffic will cause bm_sts to be set. 1 reserved 0 hda_break_en ? r/w. 0 = intel ? high definition audio traffic wi ll not cause bm_sts to be set. 1 = intel ? high definition audio traffic will cause bm_sts to be set.
lpc interface bridge registers (d31:f0) 516 datasheet 13.8.1.8 pmirpower management in itialization register (pmd31:f0) offset address: ach attribute: r/w, r/wlo default value: 00000000h size: 32-bit power well: suspend 13.8.1.9 gpio_routgpio routing control register (pmd31:f0) offset address: b8h?bbh attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: resume note: gpios that are not implemented will not have the corresponding bits implemented in this register. bit description 31:26 reserved 25 slp_lan# low on dc po wer (slp_lan_low_dc) r/w. when set to '1' and the platform is on dc power (acpresent deasserted), the pch will drive slp_lan# low while in sx/moff even if the host and intel me policy bits indicate that the phy should remain powered. if th e platform subsequently switches to ac power (acpresent asserts), slp_lan# will be driven high and the pch will re- configure the phy for wake on magic packet. 24:0 reserved bit description 31:30 gpio15 route ? r/w. see bits 1:0 for description. same pattern for gpio14 through gpio3 5:4 gpio2 route ? r/w. see bits 1:0 for description. 3:2 gpio1 route ? r/w. see bits 1:0 for description. 1:0 gpio0 route ? r/w. gpio can be routed to ca use an nmi, smi# or sci when the gpio[n]_sts bit is set. if the gpio0 is not set to an input, this field has no effect. if the system is in an s1?s5 state and if the gpe0_en bit is also set, then the gpio can cause a wake event, even if the gpio is no t routed to cause an nmi, smi# or sci. 00 = no effect. 01 = smi# (if corresponding alt_gpi_smi_en bit is also set) 10 = sci (if corresponding gpe0_en bit is also set) 11 = nmi (if corresponding gpi_nmi_en is also set)
datasheet 517 lpc interface bridge registers (d31:f0) 13.8.2 apm i/o de code register table 13-10 shows the i/o registers associated with apm support. this register space is enabled in the pci device 31: function 0 space (apmdec_en), and cannot be moved (fixed i/o location). 13.8.2.1 apm_cntadvanced power management control port register i/o address: b2h attribute: r/w default value: 00h size: 8-bit lockable: no usage: legacy only power well: core 13.8.2.2 apm_stsadvanced power management status port register i/o address: b3h attribute: r/w default value: 00h size: 8-bit lockable: no usage: legacy only power well: core table 13-10. apm register map address mnemonic register name default type b2h apm_cnt advanced power management control port 00h r/w b3h apm_sts advanced power management status port 00h r/w bit description 7:0 used to pass an apm command between the os and the smi handler. writes to this port not only store data in the apmc regi ster, but also generates an smi# when the apmc_en bit is set. bit description 7:0 used to pass data between the os and the smi handler. basically, this is a scratchpad register and is not affected by any other register or functi on (other than a pci reset).
lpc interface bridge registers (d31:f0) 518 datasheet 13.8.3 power manageme nt i/o registers table 13-11 shows the registers associated with acpi and legacy power management support. these registers locations are all offs ets from the acpi base address defined in the pci device 31: function 0 space (pmb ase), and can be moved to any 128-byte aligned i/o location. in order to access thes e registers, the acpi enable bit (acpi_en) must be set. the registers are defined to support the acpi 4. 0a specification and generally use the same bit names. note: all reserved bits and registers will always re turn 0 when read, and will have no effect when written. table 13-11. acpi and legacy i/o register map pmbase + offset mnemonic register name default attribute 00h?01h pm1_sts pm1 status 0000h r/wc 02h?03h pm1_en pm1 enable 0000h r/w 04h?07h pm1_cnt pm1 control 00000000h r/w, wo 08h?0bh pm1_tmr pm1 timer xx000000h ro 20h?27h gpe0_sts general purpose event 0 status 0000000000 000000h r/wc 28h?2fh gpe0_en general purpose event 0 enables 00000000 00000000h r/w 30h?33h smi_en smi# control and enable 00000002h r/w, wo, r/wo 34h?37h smi_sts smi status 00000000h r/wc, ro 38h?39h alt_gp_smi_en alternat e gpi smi enable 0000h r/w 3ah?3bh alt_gp_smi_sts alternate gpi smi status 0000h r/wc 3ch?3dh uprwc usb per-port registers write control 0000h r/wc, r/w, r/wo 42h gpe_cntl general purp ose event control 00h r/w 44h?45h devact_sts device ac tivity status 0000h r/wc 50h pm2_cnt pm2 control 00h r/w 60h?7fh ? reserved for tco ? ?
datasheet 519 lpc interface bridge registers (d31:f0) 13.8.3.1 pm1_stspower management 1 status register i/o address: pmbase + 00h attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 12-15: resume bit 11: rtc, bits 8 and 10: dsw if bit 10 or 8 in this register is set, an d the corresponding _en bit is set in the pm1_en register, then the pch will generate a wake event. once back in an s0 state (or if already in an s0 state when the event occurs), the pch will also generate an sci if the sci_en bit is set, or an smi# if the sci_en bit is not set. note: bit 5 does not cause an smi# or a wake event. bit 0 does not cause a wake event but can cause an smi# or sci. bit description 15 wake status (wak_sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the system is in one of the sleep states (using the slp_en bit) and an enabled wake event occurs. upon setting this bit, the pch will transition the system to the on state. if the afterg3_en bit is not set and a po wer failure (such as removed batteries) occurs without the slp_en bit set, the system will return to an s0 state when power returns, and the wak_sts bit will not be set. if the afterg3_en bit is set and a power fail ure occurs without the slp_en bit having been set, the system will go into an s5 state when power return s, and a subsequent wake event will cause the wak_sts bit to be set. note that any subsequent wake event would have to be caused by either a power bu tton press, or an enabled wake event that was preserved through the power fail ure (enable bit in the rtc well). 14 pci express wake status (pciexpwak_sts) ? r/wc. 0 = software clears this bit by writing a 1 to it. if the wake# pin is still active during the write or the pme message received indi cation has not been cleared in the root port, then the bit will remain active (that is, all inputs to this bit are level- sensitive). 1 = this bit is set by hardware to indicate that the system woke due to a pci express wakeup event. this wakeup event can be caused by the pci express wake# pin being active or receipt of a pci express pm e message at a root po rt. this bit is set only when one of these events causes the system to transition from a non-s0 system power state to the s0 system power state. this bit is set independent of the state of the pciexp_wake_dis bit. note: this bit does not itself cause a wake event or prevent entry to a sleeping state. thus, if the bit is 1 and the system is put into a sleeping state, the system will not automatically wake. 13:12 reserved
lpc interface bridge registers (d31:f0) 520 datasheet 11 power button override status (pwrbtnor_sts) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a power button override occurs (that is, the power button is pressed for at least 4 consecutive second s), due to the corresponding bit in the smbus slave message, intel me initiated po wer button override, intel me initiated host reset with power down or due to an internal thermal sensor catastrophic condition. the power button override causes an uncondit ional transition to the s5 state. the bios or sci handle r clears this bit by writing a 1 to it. this bit is not affected by hard rese ts using cf9h writes, and is no t reset by rsmrst#. thus, this bit is preserved through power failures. note that if this bit is still asserted when the global sci_en is set then an sci will be generated. 10 rtc status (rtc_sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 write, but is reset by dpwrok. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the rtc generates an alarm (assertion of the irq8# signal). additionally if the rtc_en bit (pmbase + 02h, bit 10) is set, the setting of the rtc_sts bit will generate a wake event. 9 reserved 8 power button status ( pwrbtn__sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 writ e but is reset by dpwrok. 0 = if the pwrbtn# signal is held low for mo re than 4 seconds, the hardware clears the pwrbtn_sts bit, sets the pwrbtnor_sts bit, and the system transitions to the s5 state with only pwrbtn# enabled as a wake event. this bit can be cleared by software by writing a one to the bit position. 1 = this bit is set by hardware when the pw rbtn# signal is assert ed low, independent of any other enable bit. in the s0 state, while pwrbtn_en and pwrbtn_sts are both set, an sci (or smi# if sci_en is not set) will be generated. in any sleeping state s1?s5, while pwrbtn_en (pmbase + 02h, bit 8) and pwrbtn_sts are both set, a wake event is generated. note: if the pwrbtn_sts bit is cleared by soft ware while the pwrbtn# signal is sell asserted, this will not cause the pwrbn_sts bit to be set. the pwrbtn# signal must go inactive and active ag ain to set the pwrbtn_sts bit. 7:6 reserved 5 global status (gbl _sts) ? r/wc. 0 = the sci handler should then clear this bit by writing a 1 to the bit location. 1 = set when an sci is generated due to bios wanting the attention of the sci handler. bios has a corresponding bit, bi os_rls, which will cause an sci and set this bit. 4 bus master status (bm_sts) ? r/wc. this bit will not cause a wake event, sci or smi#. 0 = software clears this bit by writing a 1 to it. 1 = set by the pch when a pch-visible bus ma ster requests access to memory or the bm_busy# signal is active. 3:1 reserved 0 timer overflow status (tmrof_sts) ? r/wc. 0 = the sci or smi# handler clears this bit by writing a 1 to the bit location. 1 = this bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). this will occur every 2. 3435 seconds. when the tmrof_en bit (pmbase + 02h, bit 0) is set, then the setting of the tmrof_sts bit will additionally generate an sci or smi# (depending on the sci_en). bit description
datasheet 521 lpc interface bridge registers (d31:f0) 13.8.3.2 pm1_enpower management 1 enable register i/o address: pmbase + 02h attribute: r/w default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 9, 11 ? 15: resume, bit 10: rtc bit description 15 reserved 14 pci express* wake disable(pciexpwak_dis) ? r/w. modification of this bit has no impact on the value of the pciexp_wake_sts bit. 0 = inputs to the pciexp_wake_sts bit in th e pm1 status register enabled to wake the system. 1 = inputs to the pciexp_wake_sts bit in the pm1 status regi ster disabled from waking the system. 13:11 reserved 10 rtc event enable (rtc_en) ? r/w. this bit is in the rtc well to allow an rtc event to wake after a power failure. in addition to being cleared by rt crst# assertion, the pch also clears this bit due to a power button override event, intel me initiated power button override, intel me initiated host reset with power down, smbus unconditional power down, processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 0 = no sci (or smi#) or wake event is generated then rtc_sts (pmbase + 00h, bit 10) goes active. 1 = an sci (or smi#) or wake event will occur when this bit is set and the rtc_sts bit goes active. 9reserved 8 power button enab le (pwrbtn_en) ? r/w. this bit is used to enable the setting of the pwrbtn_sts bit to generate a power management event (smi#, sci). pwrbtn_en has no effect on the pwrbtn_sts bit (pmbase + 00h, bi t 8) being set by the assertion of the power button. the powe r button is always enabled as a wake event. 0 = disable. 1 = enable. 7:6 reserved 5 global enable (gbl_en) ? r/w. when both the gbl_en and the gbl_sts bit (pmbase + 00h, bit 5) are set, an sci is raised. 0 = disable. 1 = enable sci on gbl_sts going active. 4:1 reserved 0 timer overflow interrupt enable (tmrof_en) ? r/w. works in conjunction with the sci_en bit (pmbase + 04h, bit 0) as described below: tmrof_en sci_en effect when tmrof_sts is set 0 x no smi# or sci 10 s m i # 11 s c i
lpc interface bridge registers (d31:f0) 522 datasheet 13.8.3.3 pm1_cntpower management 1 control register i/o address: pmbase + 04h attribute: r/w, wo default value: 00000000h size: 32-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 12: rtc, bits 13 ? 15: resume bit description 31:14 reserved 13 sleep enable ( slp_en) ? wo. setting this bit causes the system to sequence into the sleep state defined by the slp_typ field. 12:10 sleep type (slp_typ) ? r/w. this 3-bit field defi nes the type of sleep the system should enter when the slp_en bit is set to 1. these bits are only reset by rtcrst#. 9:3 reserved 2 global release (gbl_rls) ? wo. 0 = this bit always reads as 0. 1 = acpi software writes a 1 to this bit to raise an event to the bios. bios software has a corresponding enable and status bits to control its ability to receive acpi events. 1 bus master reload (bm_rld) ? r/w. this bit is treated as a scratchpad bit. this bit is reset to 0 by pltrst# 0 = bus master requests will not cause a break from the c3 state. 1 = enables bus master requests (internal or external) to cause a break from the c3 state. if software fails to set this bit before going to c3 state, the pch will still return to a snoopable state from c3 or c4 st ates due to bus master activity. 0 sci enable ( sci_en) ? r/w. selects the sci interrupt or the smi# interrupt for various events including the bits in the pm1_ sts register (bit 10, 8, 0), and bits in gpe0_sts. 0 = these events will generate an smi#. 1 = these events will generate an sci. code master interrupt 000b on: typically maps to s0 state. 001b puts processor core in s1 state. 010b reserved 011b reserved 100b reserved 101b suspend-to-ram. assert slp_s3#: typically maps to s3 state. 110b suspend-to-disk. assert slp_s3#, and slp_s4#: typically maps to s4 state. 111b soft off. assert slp_s3#, slp_s4#, and slp_s5#: typically maps to s5 state.
datasheet 523 lpc interface bridge registers (d31:f0) 13.8.3.4 pm1_tmrpower management 1 timer register i/o address: pmbase + 08h attribute: ro default value: xx000000h size: 32-bit lockable: no usage: acpi power well: core bit description 31:24 reserved 23:0 timer value (tmr_val) ? ro. returns the running count of the pm timer. this counter runs off a 3.579545 mhz clock (14.31818 mhz divided by 4). it is reset to 0 during a pci reset, and then continues counting as long as the system is in the s0 state. after an s1 state, the counter will not be reset (it will continue counting from the last value in s0 state. anytime bit 22 of the timer goes high to low (bits referenced from 0 to 23), the tmrof_sts bit (pmbase + 00h, bit 0) is set. the high-to-low transition will occur every 2.3435 seconds. if the tmrof_en bit (pmbase + 02h, bit 0) is set, an sci interrupt is also generated.
lpc interface bridge registers (d31:f0) 524 datasheet 13.8.3.5 gpe0_stsgeneral purpose event 0 status register i/o address: pmbase + 20h attribute: bits 0:32,35 r/wc bits 33:34, 36:63 ro default value: 0000000000000000h size: 64-bit lockable: no usage: acpi power well: bits 0?34, 56?63: resume, bit 35: dsw this register is symmetrical to the gene ral purpose event 0 enable register. unless indicated otherwise below, if the corresponding _en bit is set, then when the _sts bit get set, the pch will generate a wake event. on ce back in an s0 state (or if already in an s0 state when the event occurs), the pch wi ll also generate an sci if the sci_en bit is set, or an smi# if the sci_en bit (pmbas e + 04h, bit 0) is not set. bits 31:16 are reset by a cf9h full reset; bits 63:32 and 15:0 are not. all bits (except bit 35) are reset by rsmrst#. bit 35 is reset by dpwrok. bit description 63:36 reserved 35 gpio27_sts ? r/wc. 0 = disable. 1 = set by hardware and can be reset by writing a one to this bit position or a resume well reset. this bit is set at the level specified in gp27io_pol. note that gpio27 is always monitored as an inpu t for the purpose of setting this bit, regardless of the actu al gpio configuration. 34:32 reserved 31:16 gpion_sts ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = these bits are set any time the correspon ding gpio is set up as an input and the corresponding gpio signal is high (or low if the corresponding gp_inv bit is set). if the corresponding enable bit is set in the gpe0_en register, then when the gpio[n]_sts bit is set: ? if the system is in an s1?s5 state, the event will also wake the system. ? if the system is in an s0 state (or upon wa king back to an s0 state), a sci will be caused depending on the gpio_rout bits (d31:f0:b8h, bits 31:30) for the corresponding gpi. note: mapping is as follows: bit 31 corre sponds to gpio[15]... and bit 16 corresponds to gpio[0]. 15:14 reserved
datasheet 525 lpc interface bridge registers (d31:f0) 13 pme_b0_sts ? r/wc. this bit will be set to 1 by the pch when any internal device with pci power management ca pabilities on bus 0 asserts the equivalent of the pme# signal. additionally , if the pme_b0_en bit and sci_en bits are set, and the system is in an s0 state, then the setting of the pme_b0_sts bit will generate an sci (or smi# if sci_en is not set). if the pme_b0_sts bi t is set, and the syst em is in an s1?s4 state (or s5 state due to slp_typ and slp_en), then the setting of the pme_b0_sts bit will generate a wake event. if the syst em is in an s5 state due to power button override, then the pme_b0_sts bit will not cause a wake event or sci. the default for this bit is 0. writing a 1 to this bit position clears this bit. the following are internal devices which can set this bit: ?intel hd audio ? intel management engine ?maskable? wake events ?integrated lan ?sata ?ehci 12 reserved 11 pme_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the pme# signal goes active. additionally, if the pme_en and sci_en bits are set, and the system is in an s0 state, then the setting of the pme_sts bit will generate an sci or smi# (if sci_en is not set). if the pme_en bit is set, and the system is in an s1?s4 state (o r s5 state due to setting slp_typ and slp_en), then the setting of the pme_sts bit will generate a wake event. if the system is in an s5 state due to power button override or a power failure, then pme_sts will not cause a wake event or sci. 10 (desktop only) reserved 10 (mobile only) batlow_sts ? r/wc. (mobile only) so ftware clears this bit by writing a 1 to it. 0 = batlow# not asserted 1 = set by hardware when the batlow# signal is asserted. 9 pci_exp_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware to indicate that: ? the pme event message was received on one or more of the pci express* ports ? an assert pmegpe me ssage received from the processor using dmi notes: 1. the pci wake# pin has no impact on this bit. 2. if the pci_exp_sts bit went active due to an assert pmegpe message, then a deassert pmegpe message mu st be received prior to the software write in order for the bit to be cleared. 3. if the bit is not cleared and the corre sponding pci_exp_en bit is set, the level-triggered sci will remain active. 4. a race condition exists where the pci express device sends another pme message because the pci express device was not serviced within the time when it must resend the message. this may result in a spurious interrupt, and this is comprehended and approved by the pci express* specification, revision 1.0a . the window for this race condition is approximately 95?105 milliseconds. bit description
lpc interface bridge registers (d31:f0) 526 datasheet 8 ri_sts ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = set by hardware when the ri# input signal goes active. 7 smbus wake status (smb_wak_sts) ? r/wc. the smbus controller can independently cause an smi# or sci, so this bit does not need to do so (unlike the other bits in this register). software clears this bit by writing a 1 to it. 0 = wake event not caused by the pch?s smbus logic. 1 = set by hardware to indicate that the wake event was caused by the pch?s smbus logic. this bit will be set by the wake/s mi# command type, even if the system is already awake. the smi handler should then clear this bit. notes: 1. the smbus controller will independently cause an smi# so this bit does not need to do so (unlike the ot her bits in this register). 2. this bit is set by the smbus slave command 01h (wake/smi#) even when the system is in the s0 state. therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the wake/smi# command or just pr ior to entering the sleep state. 3. the smbalert_sts bit (d31:f3:i/o offs et 00h:bit 5) shou ld be cleared by software before the smb_wak_sts bit is cleared. 6 tcosci_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = toc logic or thermal sens or logic did not cause sci. 1 = set by hardware when the tco logic or thermal sensor logic causes an sci. 5:3 reserved 2 swgpe_sts ? r/wc. the swgpe_ctrl bit (bit 1 of gpe_ctrl re g) acts as a level input to this bit. 1 hot_plug_sts ? r/wc. 0 = this bit is cleared by writ ing a 1 to this bit position. 1 = when a pci express* hot-plug event oc curs. this will cause an sci if the hot_plug_en and sci_ en bits are set. 0 reserved bit description
datasheet 527 lpc interface bridge registers (d31:f0) 13.8.3.6 gpe0_engeneral purp ose event 0 enables register i/o address: pmbase + 28h attribute: r/w default value: 0000000000000000h size: 64-bit lockable: no usage: acpi power well: bits 0?7, 9, 12, 14?34, 36?63 resume, bits 8, 10?11, 13,35 rtc this register is symmetrical to the general purpose event 0 status register. bit description 63:36 reserved 35 gpio27_en ? r/w. 0 = disable. 1 = enable the setting of the gpio27_sts bit to generate a wake event/sci/smi#. gpio27 is a valid host wake event from deep s4/s5. the wake enable configuration persists after a g3 state. 34:32 reserved 31:16 gpin_en ? r/w. these bits enable the corresp onding gpi[n]_sts bits being set to cause a sci, and/or wake event. these bits are cleared by rsmrst#. note: mapping is as follows: bit 31 corre sponds to gpio15. .. and bit 16 corresponds to gpio0. 15:14 reserved 13 pme_b0_en ? r/w. 0 = disable note: enables the setting of the pme_b0_sts bit to generate a wake event and/or an sci or smi#. in addition to being cleared by rtcrst# assertion, the pch also clears this bit due to a power butt on override event, intel me initiated power button override, intel me initiated host reset with power down, smbus unconditional power do wn, processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 12 reserved 11 pme_en ? r/w. 0 = disable. 1 = enables the setting of the pme_sts to generate a wake event and/or an sci. pme# can be a wake event from the s1 ?s4 state or from s5 (if entered using slp_en, but not power button override). in addition to being cleared by rtcrst# as sertion, the pch also clears this bit due to a power button override event, intel me initiated po wer button override, intel me initiated host reset with power down, smbus unconditi onal power down, processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 10 (desktop only) reserved
lpc interface bridge registers (d31:f0) 528 datasheet 10 (mobile only) batlow_en ? r/w. (mobile only) 0 = disable. 1 = enables the batlow# signal to caus e an smi# or sci (depending on the sci_en bit) when it goes low. this bit does not prevent the batlow# signal from inhibiting the wake event. in addition to being cleared by rtcrst# as sertion, the pch also clears this bit due to a power button override event, intel me initiated power button override, intel me initiated host reset with power do wn, smbus unconditional power down, processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 9 pci_exp_en ? r/w. 0 = disable sci generation upon pci_exp_sts bit being set. 1 = enables pch to cause an sci when pci_exp_sts bit is set. this is used to allow the pci express* ports, incl uding the link to the processor, to cause an sci due to wake/pme events. 8 ri_en ? r/w. the value of this bit will be maintained through a g3 state and is not affected by a hard reset caused by a cf9h write. 0 = disable. 1 = enables the setting of the ri_sts to generate a wake event. in addition to being cleared by rtcrst# as sertion, the pch also clears this bit due to a power button override event, intel me initiated power button override, intel me initiated host reset with power do wn, smbus unconditional power down, processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 7 reserved 6 tcosci_en ? r/w. 0 = disable. 1 = enables the setting of the tc osci_sts to generate an sci. in addition to being cleared by rsmrst# assertion, the pch also clears this bit due to a power button override event, intel me initiated power button override, intel me initiated host reset with power do wn, smbus unconditional power down, processor thermal trip event, or due to an internal thermal sensor catastrophic condition. 5:3 reserved 2 swgpe_en ? r/w. this bit allows software to control the assertion of swgpe_sts bit. this bit this bit, when set to 1, enables the sw gpe function. if swgpe_ctrl is written to a 1, hardware will se t swgpe_sts (acts as a level input) if swgpe_sts, swgpe_en, and sci_en ar e all 1's, an sci will be generated if swgpe_sts = 1, swgpe_en = 1, sci_en = 0, and gbl_smi_en = 1 then an smi# will be generated 1 hot_plug_en ? r/w. 0 = disables sci generation upon the hot_plug_sts bit being set. 1 = enables the pch to cause an sci when the hot_plug_sts bit is set. this is used to allow the pci express ports to cause an sci due to hot-plug events. 0 reserved bit description
datasheet 529 lpc interface bridge registers (d31:f0) 13.8.3.7 smi_ensmi control and enable register i/o address: pmbase + 30h attribute: r/w, r/wo, wo default value: 00000002h size: 32 bit lockable: no usage: acpi or legacy power well: core note: this register is symmetrical to the smi status register. bit description 31:28 reserved 27 gpio_unlock_smi_en ? r/wo. setting this bit will cause the pch to generate an smi# when the gpio_unlock_smi_sts bi t is set in the smi_sts register. once written to 1, this bit ca n only be cleared by pltrst#. 26:19 reserved 18 intel_usb2_en ? r/w. 0 = disable 1 = enables intel-specific eh ci smi logic to cause smi#. 17 legacy_usb2_en ? r/w. 0 = disable 1 = enables legacy ehci logic to cause smi#. 16:15 reserved 14 periodic_en ? r/w. 0 = disable. 1 = enables the pch to generate an smi# when the periodic_sts bit (pmbase + 34h, bit 14) is set in the smi_sts register (pmbase + 34h). 13 tco_en ? r/w. 0 = disables tco logic generating an smi#. note that if the nmi2smi_en bit is set, smis that are caused by re-routed nmis wi ll not be gated by th e tco_en bit. even if the tco_en bit is 0, nmis will still be routed to cause smis. 1 = enables the tco logic to generate smi#. note: this bit cannot be written on ce the tco_lock bit is set. 12 reserved 11 mcsmi_en microcontroller smi enable (mcsmi_en) ? r/w. 0 = disable. 1 = enables pch to trap accesses to the microcontroller range (62h or 66h) and generate an smi#. note that ?trapped? cycl es will be claimed by the pch on pci, but not forwarded to lpc. 10:8 reserved 7 bios release (bios_rls) ? wo. 0 = this bit will always return 0 on reads. writes of 0 to this bit have no effect. 1 = enables the generation of an sci interrup t for acpi software when a one is written to this bit position by bios software. note: gbl_sts being set will caus e an sci, even if the sci_en bit is not set. software must take great care not to set the bios_rls bit (which causes gbl_sts to be set) if the sci handler is not in place.
lpc interface bridge registers (d31:f0) 530 datasheet 6 software smi# timer enable (swsmi_tmr_en) ? r/w. 0 = disable. clearing the swsmi_tmr_en bit before the timer expires will reset the timer and the smi# will not be generated. 1 = starts software smi# timer. when the swsmi timer expires (t he timeout period depends upon the swsmi_rate_sel bit se tting), swsmi_tmr_sts is set and an smi# is generated. swsm i_tmr_en stays set until cleared by software. 5 apmc_en ? r/w. 0 = disable. writes to the apm_cnt register will not cause an smi#. 1 = enables writes to the apm_cn t register to cause an smi#. 4 slp_smi_en ? r/w. 0 = disables the generation of smi# on slp_ en. note that this bi t must be 0 before the software attempts to transition the sy stem into a sleep state by writing a 1 to the slp_en bit. 1 = a write of 1 to the slp_en bit (bit 13 in pm1_cnt register) will generate an smi#, and the system will not transition to the sleep state based on that write to the slp_en bit. 3 legacy_usb_en ? r/w. 0 = disable. 1 = enables legacy usb circuit to cause smi#. 2 bios_en ? r/w. 0 = disable. 1 = enables the generation of smi# when acpi software writes a 1 to the gbl_rls bit (d31:f0:pmbase + 04h:bit 2). note that if the bios_sts bit (d31:f0:pmbase + 34h:bit 2), which gets set when software writes 1 to gbl_rls bit, is already a 1 at the time that bios_en becomes 1, an smi# will be generated when bios_en gets set. 1 end of smi (eos) ? r/w (special). this bi t controls the arbitration of the smi signal to the processor. this bit mu st be set for the pch to asse rt smi# low to the processor after smi# has been asserted previously. 0 = once the pch asserts smi# low, th e eos bit is automatically cleared. 1 = when this bit is set to 1, smi# signal wi ll be deasserted for 4 pci clocks before its assertion. in th e smi handler, the processor should clear all pending smis (by servicing them and then clearing their resp ective status bits), set the eos bit, and exit smm. this will allow the smi arbiter to re-assert smi upon detection of an smi event and the setting of a smi status bit. note: the pch is able to generate 1st smi after reset even though eos bit is not set. subsequent smi require eos bit is set. 0 gbl_smi_en ? r/w. 0 = no smi# will be generated by pch. this bit is reset by a pci reset event. 1 = enables the generation of smi# in the system upon any enabled smi event. note: when the smi_lock bit is set, this bit cannot be changed. bit description
datasheet 531 lpc interface bridge registers (d31:f0) 13.8.3.8 smi_stssmi status register i/o address: pmbase + 34h attribute: ro, r/wc default value: 00000000h size: 32-bit lockable: no usage: acpi or legacy power well: core note: if the corresponding _en bit is set when the _sts bit is set, the pch will cause an smi# (except bits 8?10 and 12, which do not need enable bits since they are logic ors of other registers that have enable bits). th e pch uses the same gpe0_en register (i/o address: pmbase+2ch) to enable/disable bo th smi and acpi sci general purpose input events. acpi os assumes that it owns the entire gpe0_en register per the acpi specification. problems arise when some of the general-purpose inputs are enabled as smi by bios, and some of the general purpose inputs are enabled for sci. in this case acpi os turns off the enabled bit for any gp ix input signals that are not indicated as sci general-purpose events at boot, and exit from sleeping states. bios should define a dummy control method which prevents the acpi os from clearing the smi gpe0_en bits. bit description 31:28 reserved 27 gpio_unlock_smi_sts ? r/wc. this bit will be set if the gpio registers lockdown logic is requesting an smi#. writing a 1 to this bit position clears this bit to 0. 26 spi_sts ? ro. this bit will be set if the spi logic is generating an smi#. this bit is read only because the sticky status and enable bits associat ed with this function are located in the spi registers. 25:22 reserved 21 monitor_sts ? ro. this bit will be set if the trap/smi logic has caused the smi. this will occur when the processor or a bus master accesses an assigned register (or a sequence of accesses). see section 10.1.20 through section 10.1.34 for details on the specific cause of the smi. 20 pci_exp_smi_sts ? ro. pci express* smi event occurre d. this could be due to a pci express pme event or hot-plug event. 19 reserved 18 intel_usb2_sts ? ro. this non-sticky read-only bit is a logical or of each of the smi status bits in the intel-specific eh ci smi status register anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. writes to this bit will have no effect. all integrated ehcis are re presented with this bit. 17 legacy_usb2_sts ? ro. this non-sticky read-only bit is a logical or of each of the smi status bits in the ehci legacy suppo rt register anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. writes to this bit will have no effect. all integrated echis are re presented with this bit.
lpc interface bridge registers (d31:f0) 532 datasheet 16 smbus smi status (smbus_smi_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = this bit is set from the 64 khz clock do main used by the sm bus. software must wait at least 15.63 ? s after the initial assertion of this bit before clearing it. 1 = indicates that the smi# was caused by: 1. the smbus slave receiving a message that an smi# should be caused, or 2. the smbalert# signal goes active and the smb_smi_en bit is set and the smbalert_dis bit is cleared, or 3. the smbus slave receiving a host notify message and the host_notify_intren and the sm b_smi_en bits are set, or 4. the pch detecting the smlink_slave_smi command while in the s0 state. 15 serirq_smi_sts ? ro. 0 = smi# was not caused by the serirq decoder. 1 = indicates that the smi# was caused by the serirq decoder. note: this is not a sticky bit 14 periodic_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set at the rate determined by the per_smi_sel bits. if the periodic_en bit (pmbase + 30h, bit 14) is also set, the pch generates an smi#. 13 tco_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = smi# not caused by tco logic. 1 = indicates the smi# was caused by the tco logic. note that this is not a wake event. 12 device monitor status (devmon_sts) ? ro. 0 = smi# not caused by device monitor. 1 = set if bit 0 of the devact_sts register (pmbase + 44h) is set. the bit is not sticky, so writes to this bit will have no effect. 11 microcontroller smi# status ( mcsmi_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = indicates that there has been no access to the power management microcontroller range (62h or 66h). 1 = set if there has been an access to the power management microcontroller range (62h or 66h) and the microcontroller deco de enable #1 bit in the lpc bridge i/o enables configuration register is 1 (d31 :f0:offset 82h:bit 11). note that this implementation assumes that the microcontroller is on lpc. if this bit is set, and the mcsmi_en bit is also set, the pch will generate an smi#. 10 gpe0_sts ? ro. this bit is a logical or of the bi ts in the alt_gp_smi_sts register that are also set up to cause an smi# (a s indicated by the gpi_rout registers) and have the corresponding bit set in the alt_gp_smi_en register. bits that are not routed to cause an smi# will have no effect on this bit. 0 = smi# was not generated by a gpi assertion. 1 = smi# was generated by a gpi assertion. 9 gpe0_sts ? ro. this bit is a logical or of the bits 47:32, 14:10, 8, 6:2, and 0 in the gpe0_sts register (pmbase + 28h) that also have the co rresponding bit set in the gpe0_en register (pmbase + 2ch). 0 = smi# was not generated by a gpe0 event. 1 = smi# was generated by a gpe0 event. 8 pm1_sts_reg ? ro. this is an ors of the bits in the acpi pm1 status register (offset pmbase+00h) that can cause an smi#. 0 = smi# was not generated by a pm1_sts event. 1 = smi# was generated by a pm1_sts event. bit description
datasheet 533 lpc interface bridge registers (d31:f0) 13.8.3.9 alt_gp_smi_enalternate gpi smi enable register i/o address: pmbase +38h attribute: r/w default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: resume 7 reserved 6 swsmi_tmr_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = software smi# timer has not expired. 1 = set by the hardware when th e software smi# timer expires. 5 apm_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = no smi# generated by writ e access to apm control register with apmch_en bit set. 1 = smi# was generated by a write access to the apm control register with the apmc_en bit set. 4 slp_smi_sts ? r/wc. software clears this bit by writing a 1 to the bit location. 0 = no smi# caused by write of 1 to slp_ en bit when slp_smi_en bit is also set. 1 = indicates an smi# was caused by a write of 1 to slp_en bit when slp_smi_en bit is also set. 3 legacy_usb_sts ? ro. this bit is a logical or of each of the smi status bits in the usb legacy keyboard/mouse control regist ers anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. 0 = smi# was not generated by usb legacy event. 1 = smi# was generated by usb legacy event. 2 bios_sts ? r/wc. 0 = no smi# generated due to acpi software requesti ng attention. 1 = this bit gets set by hardware when a 1 is written by software to the gbl_rls bit (d31:f0:pmbase + 04h:bit 2). when bo th the bios_en bit (d31:f0:pmbase + 30h:bit 2) and the bios_sts bit are se t, an smi# will be generated. the bios_sts bit is cleared when softwa re writes a 1 to its bit position. 1:0 reserved bit description bit description 15:0 alternate gpi smi enable ? r/w. these bits are used to enable the corresponding gpio to cause an smi#. for th ese bits to have any effect, the following must be true. ? the corresponding bit in the alt_gp_smi_en register is set. ? the corresponding gpi must be routed in the gpi_rout register to cause an smi. ? the corresponding gpio must be implemented. note: mapping is as follows: bit 15 correspon ds to gpio15... bit 0 corresponds to gpio0.
lpc interface bridge registers (d31:f0) 534 datasheet 13.8.3.10 alt_gp_smi_stsaltern ate gpi smi status register i/o address: pmbase +3ah attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: resume 13.8.3.11 gpe_cntlgeneral purpose control register i/o address: pmbase +42h attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi or legacy power well: bits 0?1, 3?7: resume bit 2: rtc bit description 15:0 alternate gpi smi status ? r/wc. these bits report th e status of the corresponding gpios. 0 = inactive. software clears th is bit by writing a 1 to it. 1 = active these bits are sticky. if the following conditions are true, then an smi# will be generated and the gpe0_sts bit set: ? the corresponding bit in the alt_gpi_sm i_en register (pmbase + 38h) is set ? the corresponding gpio must be routed in the gpi_rout register to cause an smi. ? the corresponding gpio must be implemented. all bits are in the resume well. default for these bits is dependent on the state of the gpio pins. bit description 7:2 reserved 2 gpio27_pol ? r/w. this bit controls the polarity of the gpio27 pin needed to set the gpio27_sts bit. 0 = gpio27 = 0 will set the gpio27_sts bit. 1 = gpio27 = 1 will set the gpio27_sts bit this bit is cleared by rtcrst# assertion. 1 swgpe_ctrl ? r/w. this bit allows software to control the assert ion of swgpe_sts bit. this bit is used by hardware as the le vel input signal for the swgpe_sts bit in the gpe0_sts register. when swgpe_ ctrl is 1, swgpe_sts will be set to 1, and writes to swgpe_sts with a value of 1 to clear swgp e_sts will result in swgpe_sts being set back to 1 by hardware. when swgpe_ctrl is 0, writes to swgpe_ sts with a value of 1 will clear swgpe_sts to 0. in addition to being cleared by rsmrst# assertion, the pch also clears this bit due to a power button override even t, intel me initiated powe r button override, intel me initiated host reset with power down, smbus unconditional power down, processor thermal trip event, or due to an intern al thermal sensor ca tastrophic condition. 0 reserved
datasheet 535 lpc interface bridge registers (d31:f0) 13.8.3.12 devact_sts device activity status register i/o address: pmbase +44h attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: legacy only power well: core each bit indicates if an access has occurred to the corresponding device?s trap range, or for bits 6:9 if the corresponding pci interru pt is active. this register is used in conjunction with the periodic smi# timer to detect any system activity for legacy power management. the periodic smi# timer indicates if it is the right time to read the devact_sts register (pmbase + 44h). note: software clears bits that are set in this register by writing a 1 to the bit position. 13.8.3.13 pm2_cntpower management 2 control register i/o address: pmbase + 50h attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi power well: core bit description 15:13 reserved 12 kbc_act_sts ? r/wc. kbc (60/64h). 0 = indicates that there has been no access to this device i/o range. 1 = this device i/o range has been accessed. clear this bit by writing a 1 to the bit location. 11:10 reserved 9 pirqdh_act_sts ? r/wc. pirq[d or h]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active . clear this bit by writing a 1 to the bit location. 8 pirqcg_act_sts ? r/wc. pirq[c or g]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active . clear this bit by writing a 1 to the bit location. 7 pirqbf_act_sts ? r/wc. pirq[b or f]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active . clear this bit by writing a 1 to the bit location. 6 pirqae_act_sts ? r/wc. pirq[a or e]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pci interrupts has been active . clear this bit by writing a 1 to the bit location. 5:0 reserved bit description 7:1 reserved 0 arbiter disabl e (arb_dis) ? r/w this bit is a scratchp ad bit for legacy software compatibility.
lpc interface bridge registers (d31:f0) 536 datasheet 13.9 system management tco registers the tco logic is accessed using registers mapped to the pci configuration space (device 31:function 0) and the system i/o space. for tco pci configuration registers, see lpc device 31:function 0 pci configuration registers. tco register i/o map the tco i/o registers reside in a 32-byte range pointed to by a tcobase value, which is, pmbase + 60h in the pci config space. the following table shows the mapping of the registers within that 32-byte range. each register is described in the following sections. 13.9.1 tco_rldtco timer reload and current value register i/o address: tcobase +00h attribute: r/w default value: 0000h size: 16-bit lockable: no power well: core table 13-12. tco i/o register address map tcobase + offset mnemonic register name default attribute 00h?01h tco_rld tco timer reload and current value 0000h r/w 02h tco_dat_in tco data in 00h r/w 03h tco_dat_out tco data out 00h r/w 04h?05h tco1_sts tco1 status 0000h r/wc, ro 06h?07h tco2_sts tco2 status 0000h r/wc 08h?09h tco1_cnt tco1 control 0000h r/w, r/wlo, r/wc 0ah?0bh tco2_cnt tco2 control 0008h r/w 0ch?0dh tco_message1, tco_message2 tco message 1 and 2 00h r/w 0eh tco_wdcnt tco watchdog control 00h r/w 0fh ? reserved ? ? 10h sw_irq_gen software irq generation 03h r/w 11h ? reserved ? ? 12h?13h tco_tmr tco timer initial value 0004h r/w 14h?1fh ? reserved ? ? bit description 15:10 reserved 9:0 tco timer value ? r/w. reading this register will return the current count of the tco timer. writing any value to this register wi ll reload the timer to prevent the timeout.
datasheet 537 lpc interface bridge registers (d31:f0) 13.9.2 tco_dat_intco data in register i/o address: tcobase +02h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core 13.9.3 tco_dat_outtco data out register i/o address: tcobase +03h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core 13.9.4 tco1_ststco1 status register i/o address: tcobase +04h attribute: r/wc, ro default value: 2000h size: 16-bit lockable: no power well: core (except bit 7, in rtc) bit description 7:0 tco data in value ? r/w. this data register field is used for passing commands from the os to the smi handler. writes to this register will cause an smi and set the sw_tco_smi bit in the tco1_sts register (d31:f0:04h). bit description 7:0 tco data out value ? r/w. this data register fi eld is used for passing commands from the smi handler to the os. writes to this register will set the tco_int_sts bit in the tco1_sts register. it will also cause an interrupt, as selected by the tco_int_sel bits. bit description 15:14 reserved 13 tco_slvsel (tco slave select) ? ro. this register bit is read only by host and indicates the value of tco slave select soft strap. refer to the pch soft straps section of the spi chapter for details. 12 dmiserr_sts ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = pch received a dmi special cycle message using dmi indicating that it wants to cause an serr#. the software must read the processor to determine the reason for the serr#. 11 reserved 10 dmismi_sts ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = pch received a dmi special cycle message using dmi indicating that it wants to cause an smi. the software must read the processor to determine the reason for the smi.
lpc interface bridge registers (d31:f0) 538 datasheet 9 dmisci_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = pch received a dmi special cycle message using dmi indicating that it wants to cause an sci. the so ftware must read the processo r to determine the reason for the sci. 8 bioswr_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = pch sets this bit and generates and smi# to indicate an invalid attempt to write to the bios. this occurs when either: a) the bioswp bit is changed from 0 to 1 and the bld bit is also set, or b) any write is attempted to the bios and the bioswp bit is also set. note: on write cycles attempted to the 4 mb lower alias to the bios space, the bioswr_sts will not be set. 7 newcentury_sts ? r/wc. this bit is in the rtc well. 0 = cleared by writing a 1 to the bit position or by rtcrst# going active. 1 = this bit is set when the year byte (rtc i/o space, index offset 09h) rolls over from 99 to 00. setting this bit will cause an smi# (but not a wake event). note: the newcentury_sts bit is not valid when the rtc battery is first installed (or when rtc power has not been maintain ed). software can determine if rtc power has not been maintained by checking the rtc_pwr_sts bit (d31:f0:a4h, bit 2), or by other means (such as a checksum on rtc ram). if rtc power is determined to have not been maintained, bios should set the time to a valid value and then clear the newcentury_sts bit. the newcentury_sts bit may take up to 3 rt c clocks for the bit to be cleared after a 1 is written to the bit to clear it. after writing a 1 to this bit, software should not exit the smi handler until verifying that the bit has actu ally been cleared. th is will ensure that the smi is not re-entered. 6:4 reserved 3 timeout ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by pch to indicate that the smi was caused by the tco timer reaching 0. 2 tco_int_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = smi handler caused the interrupt by writing to the tco_dat_out register (tcobase + 03h). 1 sw_tco_smi ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = software caused an smi# by writing to the tco_dat_in register (tcobase + 02h). 0 nmi2smi_sts ? ro. 0 = cleared by clearing the associated nmi status bit. 1 = set by the pch when an smi# occurs because an event occurred that would otherwise have caused an nmi (because nmi2smi_en is set). bit description
datasheet 539 lpc interface bridge registers (d31:f0) 13.9.5 tco2_ststco2 status register i/o address: tcobase +06h attribute: r/wc default value: 0000h size: 16-bit lockable: no power well: resume (except bit 0, in rtc) bit description 15:5 reserved 4 smlink slave smi status (smlink_slv_smi_sts) ? r/wc. allow the software to go directly into a pre-determ ined sleep state. this avoids race conditions. software clears this bit by writing a 1 to it. 0 = the bit is reset by rsmrst#, but not du e to the pci reset associated with exit from s3?s5 states. 1 = pch sets this bit to 1 when it rece ives the smi message on the smlink slave interface. 3 reserved 2 boot_sts ? r/wc. 0 = cleared by pch based on rsmrst# or by so ftware writing a 1 to this bit. note that software should first clear the second_to_ sts bit before writing a 1 to clear the boot_sts bit. 1 = set to 1 when the second_to_sts bit go es from 0 to 1 and the processor has not fetched the firs t instruction. if rebooting due to a second tco timer timeout, and if the boot_sts bit is set, the pch will reboot using the ?safe? multiplier (1111). this allows the system to recover from a processor frequency multiplier that is too high, and allows the bios to check the boot_sts bit at boot. if the bit is set and the frequency multiplier is 1111, then the bios knows that the processor has been programmed to an invalid multiplier. 1 second_to_sts ? r/wc. 0 = software clears this bit by wr iting a 1 to it, or by a rsmrst#. 1 = pch sets this bit to 1 to indicate that the timeout bit had been (or is currently) set and a second timeout occurred before the tco_rld register was written. if this bit is set and the no_reboot config bit is 0, then the pch will reboot the system after the second timeout. the reboot is done by asserting pltrst#. 0 intruder detect (intrd_det) ? r/wc. 0 = software clears this bit by writin g a 1 to it, or by rtcrst# assertion. 1 = set by pch to indicate that an intrusion was detected. this bit is set even if the system is in g3 state. notes: 1. this bit has a recovery time. after writing a 1 to this bit position (to clear it), the bit may be read back as a 1 for up 65 microsecon ds before it is read as a 0. software must be aware of this recovery time when reading this bit after clearing it. 2. if the intruder# si gnal is active when the soft ware attempts to clear the intrd_det bit, the bit will remain as a 1, and the smi# will be generated again immediately. the smi handler can clear th e intrd_sel bits (tco base + 0ah, bits 2:1), to avoid further smis. however, if the intruder# signals goes inactive and then active again, there will not be further smi?s (because the intrd_sel bits would select that no smi# be generated). 3. if the intruder# si gnal goes inactive some poin t after the intrd_det bit is written as a 1, then the intrd_det signal will go to a 0 when intruder# input signal goes inactive. note that this is slightly different th an a classic st icky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit.
lpc interface bridge registers (d31:f0) 540 datasheet 13.9.6 tco1_cnttco1 control register i/o address: tcobase +08h a ttribute: r/w, r/wlo, r/wc default value: 0000h size: 16-bit lockable: no power well: core bit description 15:13 reserved 12 tco_lock ? r/wlo. when set to 1, this bi t prevents writes from changing the tco_en bit (in offset 30h of power management i/o space). once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. a core-well reset is required to change this bit from 1 to 0. this bit defaults to 0. 11 tco timer halt (tco_tmr_hlt) ? r/w. 0 = the tco timer is enabled to count. 1 = the tco timer will halt. it will not count, and thus cannot reach a value that will cause an smi# or set the second_to_sts bit. when set, this bit will prevent rebooting and prevent alert on lan event messages from being transmitted on the smlink (but not alert on lan* heartbeat messages). 10 reserved 9 nmi2smi_en ? r/w. 0 = normal nmi functionality. 1 = forces all nmis to instead cause smis. the functionality of this bit is dependent upon the settings of the nmi_en bit and the gbl_smi_en bit as detailed in the following table: 8 nmi_now ? r/wc. 0 = software clears this bit by writing a 1 to it. the nmi handler is expected to clear this bit. another nmi will not be generated until the bit is cleared. 1 = writing a 1 to this bit causes an nmi. this allows the bios or smi handler to force an entry to the nmi handler. 7:0 reserved nmi_en gbl_smi_en description 0b 0b no smi# at all because gbl_smi_en = 0 0b 1b smi# will be caused due to nmi events 1b 0b no smi# at all because gbl_smi_en = 0 1b 1b no smi# due to nmi because nmi_en = 1
datasheet 541 lpc interface bridge registers (d31:f0) 13.9.7 tco2_cnttco2 control register i/o address: tcobase +0ah attribute: r/w default value: 0008h size: 16-bit lockable: no power well: resume 13.9.8 tco_message1 and tc o_message2 registers i/o address: tcobase +0ch (message 1)attribute: r/w tcobase +0dh (message 2) default value: 00h size: 8-bit lockable: no power well: resume bit description 15:6 reserved 5:4 os_policy ? r/w. os-based software writes to these bits to select the policy that the bios will use after the pl atform resets due the wdt. the following convention is recommended for the bios and os: 00 = boot normally 01 = shut down 10 = do not load os. hold in pre-boot state and use lan to determine next step 11 = reserved note: these are just scratchpad bits. they should not be reset when the tco logic resets the platform due to watchdog timer. 3 gpio11_alert_disable ? r/w. at reset (using rsmrst# asserted) this bit is set and gpio[11] alerts are disabled. 0 = enable. 1 = disable gpio11/smbalert# as an alert source for the heartbeats and the smbus slave. 2:1 intrd_sel ? r/w. this field selects the action to take if the intruder# signal goes active. 00 = no interrupt or smi# 01 = interrupt (as sele cted by tco_int_sel). 10 = smi 11 = reserved 0 reserved bit description 7:0 tco_message[ n ] ? r/w. bios can write into these registers to indicate its boot progress. the external microc ontroller can read these registers to monitor the boot progress.
lpc interface bridge registers (d31:f0) 542 datasheet 13.9.9 tco_wdcnttco watc hdog control register offset address: tcobase + 0eh attribute: r/w default value: 00h size: 8 bits power well: resume 13.9.10 sw_irq_gensoftware irq generation register offset address: tcobase + 10h attribute: r/w default value: 03h size: 8 bits power well: core 13.9.11 tco_tmrtco timer initial value register i/o address: tcobase +12h attribute: r/w default value: 0004h size: 16-bit lockable: no power well: core bit description 7:0 the bios or system management software can write into this register to indicate more details on the boot progress. the register will reset to 00h based on a rsmrst# (but not pltrst#). the external microcontroller can read this register to monitor boot progress. bit description 7:2 reserved 1 irq12_cause ? r/w. when software sets this bit to 1, irq12 will be asserted. when software sets this bit to 0, irq12 will be deasserted. 0 irq1_cause ? r/w. when software sets this bit to 1, irq1 will be asserted. when software sets this bit to 0, irq1 will be deasserted. bit description 15:10 reserved 9:0 tco timer initial value ? r/w. value that is loaded into the timer each time the tco_rld register is written. values of 0000h or 0001h will be ignored and should not be attempted. the timer is clocked at a pproximately 0.6 seconds, and thus allows timeouts ranging from 1.2 second to 613.8 seconds. note: the timer has an error of 1 tick (0.6 s). the tco timer will only count down in the s0 state.
datasheet 543 lpc interface bridge registers (d31:f0) 13.10 general purpose i/o registers the control for the general purpose i/o signals is handled through a 128-byte i/o space. the base offset for this space is selected by the gpiobase register. table 13-13. registers to control gpio address map gpiobase + offset mnemonic register name default attribute 00h?03h gpio_use_sel gpio use select b96ba1ffh r/w 04h?07h gp_io_sel gpio input/output select f6ff6effh r/w 08h?0bh ? reserved 0h ? 0ch?0fh gp_lvl gpio level for input or output 02fe0100h r/w 10h?13h ? reserved 0h ? 14h?17h ? reserved 0h ? 18h?1bh gpo_blink gpio bl ink enable 00040000h r/w 1ch?1fh gp_ser_blink gp serial blink 00000000h r/w 20h?23h gp_sb_cmdsts gp serial blink command status 00080000h r/w 24h?27h gp_sb_data gp seri al blink data 00000000h r/w 28h?29h gpi_nmi_en gpi nmi enable 0000h r/w 2ah?2bh gpi_nmi_sts gpi nmi status 0000h r/wc 2ch?2fh gpi_inv gpio signal invert 00000000h r/w 30h?33h gpio_use_sel2 gpio use select 2 020300feh (mobile only) / 020300ffh (desktop only) r/w 34h?37h gp_io_sel2 gpio input/ou tput select 2 1f57fff4h r/w 38h?3bh gp_lvl2 gpio level for input or output 2 a4aa0007h r/w 3ch?3fh ? reserved 0h ? 40h?43h gpio_use_sel3 gpio use select 3 00000030h (mobile only)/ 00000130h (desktop only) r/w 44h?47h gpio_sel3 gpio input/output select 3 00000f00h r/w 48h?4bh gp_lvl3 gpio level for input or output 3 000000c0h r/w 4ch?5fh ? reserved ? ? 60h?63h gp_rst_sel1 gpio re set select 1 01000000h r/w 64h?67h gp_rst_sel2 gpio re set select 2 00000000h r/w 68h?6bh gp_rst_sel3 gpio reset select 3 00000000h r/w 6ch?7fh ? reserved ? ?
lpc interface bridge registers (d31:f0) 544 datasheet 13.10.1 gpio_use_selgpio use select register offset address: gpiobase + 00h attribute: r/w default value: b96ba1ffh size: 32-bit lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 13.10.2 gp_io_selgpio input/output select register offset address: gpiobase +04h attribute: r/w default value: f6ff6effh size: 32-bit lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:0 gpio_use_sel[31:0] ? r/w. each bit in this regi ster enables the corresponding gpio (if it exists) to be used as a gp io, rather than for the native function. 0 = signal used as native function. 1 = signal used as a gpio. notes: 1. the following bits are always 1 because they are always unmultiplexed: 8, 15, 24, 27, and 28. 2. after a full reset (rsmrst#) all multip lexed signals in the resume and core wells are configured as their default function. after only a pltrst#, the gpios in the core well are configur ed as their default function. 3. when configured to gpio mode, the mult iplexing logic will present the inactive state to native logic that uses the pin as an input. 4. by default, all gpios are reset to th e default state by cf9h reset except gpio24. other resume well gpios' reset behavior can be programmed using gp_rst_sel registers. 5. bit 29 can be configured to gpio when slp_lan#/gpio29 select soft-strap is set to 1 (gpio usage). 6. gpio18, gpio25, and gpio26 are mobile only gpios. bit description 31:0 gp_io_sel[31:0] ? r/w. when configured in native mode (gpio_use_ sel[n] is 0), writes to these bits have no effect. the value reported in this register is undefined when programmed as native mode. 0 = output. the corresponding gpio signal is an output. 1 = input. the corresponding gpio signal is an input.
datasheet 545 lpc interface bridge registers (d31:f0) 13.10.3 gp_lvlgpio level for input or output register offset address: gpiobase +0ch attribute: r/w default value: 02fe0100h size: 32-bit lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 13.10.4 gpo_blinkgpo b link enable register offset address: gpiobase +18h attribute: r/w default value: 00040000h size: 32-bit lockable: no power well: core for 0:7, 16:23, resume for 8:15, 24:31 note: gpio18 will blink by default imme diately after reset. this signal could be connected to an led to indicate a failed boot (by programmin g bios to clear gp_blink18 after successful post). bit description 31:0 gp_lvl[31:0] ? r/w. these registers are implemente d as dual read/write with dedicated storage each. write value will be stored in the write register, while read is coming from the read register which will always reflect the value of the pin. if gpio[n] is programmed to be an outp ut (using the corresponding bit in the gp_io_sel register), then the corresponding gp_lvl[n] write register value will drive a high or low value on the output pin. 1 = high, 0 = low. when configured in native mode (gpio_use_ sel[n] is 0), writes to these bits are stored but have no effect to the pin value. the value reported in this register is undefined when programmed as native mode. note: bit 29 setting will be ignored if intel me fw is configuring slp_lan# behavior. when gpio29/slp_lan# select soft-strap is set to 1 (gpio usage), bit 29 can be used as regular gp_lvl bit. bit description 31:0 gp_blink[31:0] ? r/w. the setting of this bit has no effect if the corresponding gpio signal is programmed as an input. 0 = the corresponding gpio will function normally. 1 = if the corresponding gpio is programmed as an output, the output signal will blink at a rate of approximately once per second. the high and low times have approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. the value of the corresponding gp_lvl bit remains unchanged during the blink process, and does not effect the blink in any way. the gp_lvl bit is not altered when programmed to blink. it wi ll remain at its previous value. these bits correspond to gpio in the resu me well. these bits revert to the default value based on rsmrst# or a write to the cf9h register (but not just on pltrst#).
lpc interface bridge registers (d31:f0) 546 datasheet 13.10.5 gp_ser_blinkgp serial blink register offset address: gpiobase +1ch attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: core for 0:7, 16:23, resume for 8:15, 24:31 13.10.6 gp_sb_cmdstsgp serial blink command status register offset address: gpiobase +20h attribute: r/w, ro default value: 00080000h size: 32-bit lockable: no power well: core bit description 31:0 gp_ser_blink[31:0] ? r/w. the setting of this bit has no effect if the corresponding gpio is programmed as an in put or if the corresponding gpio has the gpo_blink bit set. when set to a 0, the corresponding gpio will function normally. when using serial blink, this bit should be set to a 1 while the corresponding gp_io_sel bit is set to 1. setting the gp_io_sel bit to 0 after the gp_ser_blink bit ensures pch will not drive a 1 on the pin as an output. when this corresponding bit is set to a 1 and the pin is configured to ou tput mode, the serial blink capability is enabled. the pch will serialize messages through an open-drain buffer configuration. the value of the corresponding gp_lvl bi t remains unchanged and does not impact the serial blink capability in any way. writes to this register have no effect wh en the corresponding pin is configured in native mode and the read va lue returned is undefined. bit description 31:24 reserved 23:22 data length select (dls) ? r/w. this field determines the number of bytes to serialize on gpio. 00 = serialize bits 7:0 of gp_sb_data (1 byte) 01 = serialize bits 15:0 of gp_sb_data (2 bytes) 10 = undefined ? software must not write this value 11 = serialize bits 31:0 of gp_sb_data (4 bytes) software should not modify the value in this register unless the busy bit is clear. writes to this register have no effect when the co rresponding pin is configured in native mode and the read value returned is undefined. 21:16 data rate select (drs) ? r/w. this field selects the number of 120ns time intervals to count between manchester data transitions. the default of 8h results in a 960 ns minimum time between transitions. a value of 0h in this register produces undefined behavior. software should not modify the value in th is register unless the busy bit is clear. 15:9 reserved 8 busy ? ro. this read-only status bit is the hard ware indication that a serialization is in progress. hardware se ts this bit to 1 based on the go bit being set. hardware clears this bit when the go bit is cleared by the hardware. 7:1 reserved 0 go ? r/w. this bit is set to 1 by software to start the serializatio n process. hardware clears the bit after the serialized data is sent. writes of 0 to this register have no effect. software should not write this bit to 1 unless the busy status bit is cleared.
datasheet 547 lpc interface bridge registers (d31:f0) 13.10.7 gp_sb_datagp seri al blink data register offset address: gpiobase +24h attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: core 13.10.8 gpi_nmi_engpi nmi enable register offset address: gpiobase +28h attribute: r/w default value: 00000h size: 16-bit lockable: no power well: core for 0:7 resume for 8:15 13.10.9 gpi_nmi_stsgpi nmi status register offset address: gpiobase +2ah attribute: r/wc default value: 00000h size: 16-bit lockable: yes power well: core for 0:7 resume for 8:15 bit description 31:0 gp_sb_data[31:0] ? r/w. this register contains the data serialized out. the number of bits shifted out are selected through the dls field in the gp_sb_cmdsts register. this register should not be modifi ed by software when the busy bit is set. bit description 15:0 gpi_nmi_en[15:0]. gpi nmi enable: this bit only has effect if the corresponding gpio is used as an inpu t and its gpi_rout register is being programmed to nmi functional ity. when set to 1, it us ed to allow active-low and active-high inputs (depends on inversion bit) to cause nmi. bit description 15:0 gpi_nmi_sts[15:0]. gpi nmi status: gpi_nmi_sts[15:0]. gpi nmi status: this bit is set if the corresponding gpio is used as an input, and its gpi_rout register is being programmed to nmi func tionality and also gpi_nmi_en bit is set when it detects either: 1) active-high edge when its corresponding gpi_inv is configured with value 0. 2) active-low edge when its correspondi ng gpi_inv is configured with value 1. note: writing value of 1 will clear the bit, while writing value of 0 have no effect.
lpc interface bridge registers (d31:f0) 548 datasheet 13.10.10 gpi_invgpio sign al invert register offset address: gpiobase +2ch attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: core for 17, 16, 7:0 13.10.11 gpio_use_sel2gpio use select 2 register offset address: gpiobase +30h attribute: r/w default value: 020300ffh (desktop) size: 32-bit 020300feh (mobile) lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:16 reserved 15:0 input inversion (gp_inv[n]) ? r/w. this bit only has effect if the corresponding gpio is used as an input and used by the gpe logic, where the polarity matters. when set to ?1?, then the gpi is inverted as it is sent to the gpe logic that is using it. this bit has no effect on the value that is reported in the gp_lvl register. these bits are used to allow both active-low and active-high inputs to cause smi# or sci. note that in the s0 or s1 state, the input signal must be active for at least two pci clocks to ensure detection by the pch. in the s3, s4 or s5 states the input signal must be active for at least 2 rtc clocks to ensure detection. the setting of these bits has no effect if the corresponding gpio is programm ed as an output. these bits correspond to gpi that are in the resume well, and will be reset to their default values by rsmrst# or by a write to the cf9h register. 0 = the corresponding gpi_sts bit is set when the pch detects the state of the input pin to be high. 1 = the corresponding gpi_sts bit is set when the pch detects the state of the input pin to be low. bit description 31:0 gpio_use_sel2[63:32] ? r/w. each bit in this regi ster enables the corresponding gpio (if it exists) to be used as a gpio, rather than for the native function. 0 = signal used as native function. 1 = signal used as a gpio. notes: 1. the following bits are always 1 becaus e they are always unmultiplexed: 3, 25. the following bit is unmultiplexe d in desktop and is also 1: 0. 2. if gpio[n] does not exist, then, the (n-32) bit in this register will always read as 0 and writes will have no effect. the following bit is also not used in mobile and is always 0 on mobile: 0. 3. after a full reset rsmrst# all multiplexe d signals in the resume and core wells are configured as their default function. after only a pltrst#, the gpios in the core well are configured as their default function. 4. when configured to gpio mode, the multiplexing logic will present the inactive state to native logic that uses the pin as an input. 5. bit 26 is ignored, functionality is conf igured by bits 9:8 of flmap0 register. 6. gpio47 and gpio56 are mobile only gpios. this register corresponds to gpio[63:32]. bit 0 corresponds to gpio32 and bit 31 corresponds to gpio63.
datasheet 549 lpc interface bridge registers (d31:f0) 13.10.12 gp_io_sel2gpio input/ output select 2 register offset address: gpiobase +34h attribute: r/w default value: 1f57fff4h lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 13.10.13 gp_lvl2gpio level for input or output 2 register offset address: gpiobase +38h attribute: r/w default value: a4aa0007h size: 32-bit lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:0 gp_io_sel2[63:32] ? r/w. 0 = gpio signal is programmed as an output. 1 = corresponding gpio signal (if enab led in the gpio_use_sel2 register) is programmed as an input. this register corresponds to gpio[6 3:32]. bit 0 corresponds to gpio32. bit description 31:0 gp_lvl[63:32] ? r/w. these registers are implemented as dual read/write with dedicated storage each. write value will be stored in the write register, while read is coming from the read register which will alwa ys reflect the value of the pin. if gpio[n] is programmed to be an output (using the corresponding bi t in the gp_io_sel register), then the corresponding gp_lvl[n] wr ite register value will drive a high or low value on the output pin. 1 = high, 0 = low. when configured in native mode (gpio_use_ sel[n] is 0), writes to these bits are stored but have no effect to the pin value. the value reported in this register is undefined when programmed as native mode. note: this register corresponds to gpio[6 3:32]. bit 0 corresponds to gpio32.
lpc interface bridge registers (d31:f0) 550 datasheet 13.10.14 gpio_use_sel3gpio use select 3 register offset address: gpiobase +40h attribute: r/w default value: 00000130h (desktop) size: 32-bit 00000030h (mobile) lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 13.10.15 gpio_sel3gpio input/ output select 3 register offset address: gpiobase +44h attribute: r/w default value: 00000f00h size: 32-bit lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:12 always 0. no corresponding gpio. 11:0 gpio_use_sel3[75:64] ? r/w. each bit in this regi ster enables the corresponding gpio (if it exists) to be used as a gpio, rather than for the native function. 0 = signal used as native function. 1 = signal used as a gpio. notes: 1. the following bit is always 1 because it is always unmultiplexed: 8 2. if gpio[n] does not exist, then, the (n-64) bit in this register will always read as 0 and writes will have no effect. 3. after a full reset rsmrst# all multiplexe d signals in the resume and core wells are configured as their default function. after only a pltrst#, the gpios in the core well are configured as their default function. 4. when configured to gpio mode, the multiplexing logic will present the inactive state to native logic that uses the pin as an input. 5. gpio73 is a mobile only gpio. this register corresponds to gpio[95:64]. bit 0 corresponds to gpio64 and bit 11 corresponds to gpio75. bit description 31:12 always 0. no corresponding gpio. 11:8 gpio_io_sel3[75:72] ? r/w. 0 = gpio signal is programmed as an output. 1 = corresponding gpio signal (if enab led in the gpio_use_sel3 register) is programmed as an input. 7:4 always 0. no corresponding gpio. 3:0 gpio_io_sel3[67:64] ? r/w. 0 = gpio signal is programmed as an output. 1 = corresponding gpio signal (if enab led in the gpio_use_sel3 register) is programmed as an input. this register corresponds to gpio[9 5:64]. bit 0 corresponds to gpio64.
datasheet 551 lpc interface bridge registers (d31:f0) 13.10.16 gp_lvl3gpio level for input or output 3 register offset address: gpiobase +48h attribute: r/w default value: 000000c0h size: 32-bit lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 13.10.17 gp_rst_sel1gpio reset select register offset address: gpiobase +60h attribute: r/w default value: 01000000h size: 32-bit lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:12 always 0. no corresponding gpio. 11:8 gp_lvl[75:72] ? r/w. these registers are implemented as dual read /write with dedicated storage each. write value will be stored in the write register, while read is coming from the read register which will always reflect the value of the pin. if gpio[n] is programmed to be an output (using the corresponding bi t in the gp_io_sel register ), then the corresponding gp_lvl[n] write register value will drive a high or low value on the output pin. 1 = high, 0 = low. when configured in native mode (gpio_use_ sel[n] is 0), writes to these bits are stored but have no effect to the pin value. the value reported in this register is undefined when programmed as native mode. 7:4 always 0. no corresponding gpio. 3:0 gp_lvl[67:64] ? r/w. these registers are implemented as dual read /write with dedicated storage each. write value will be stored in the write register, while read is coming from the read register which will always reflect the value of the pin. if gpio[n] is programmed to be an output (using the corresponding bi t in the gp_io_sel register ), then the corresponding gp_lvl[n] write register value will drive a high or low value on the output pin. 1 = high, 0 = low. when configured in native mode (gpio_use_ sel[n] is 0), writes to these bits are stored but have no effect to the pin value. the value reported in this register is undefined when programmed as native mode. this register corresponds to gpio[95:64]. bit 0 corresponds to gpio64. bit description 31:24 gp_rst_sel[31:24] ? r/w. 0 = corresponding gpio registers will be re set by pwrok deassertio n, cf9h reset (06h or 0eh), or sys_reset# assertion. 1 = corresponding gpio registers will be reset by rsmrst# assertion only. note: gpio[24] register bits are not cl eared by cf9h reset by default. 23:16 reserved 15:8 gp_rst_sel[15:8] ? r/w. 0 = corresponding gpio registers will be re set by pwrok deassertio n, cf9h reset (06h or 0eh), or sys_reset# assertion. 1 = corresponding gpio registers will be reset by rsmrst# assertion only. 7:0 reserved
lpc interface bridge registers (d31:f0) 552 datasheet 13.10.18 gp_rst_sel2gpio reset select register offset address: gpiobase +64h attribute: r/w default value: 00000000h size: 32-bit lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 13.10.19 gp_rst_sel3gpio reset select register offset address: gpiobase +68h attribute: r/w default value: 00000000h size: 32-bit lockable: yes power well: core for 0:7, 16:23, resume for 8:15, 24:31 bit description 31:24 gp_rst_sel[63:56] ? r/w. 0 = corresponding gpio registers will be re set by pwrok deassertion, cf9h reset (06h or 0eh), or sys_reset# assertion. 1 = corresponding gpio registers will be reset by rsmrst# assertion only. 23:16 reserved 15:8 gp_rst_sel[47:40] ? r/w. 0 = corresponding gpio registers will be re set by pwrok deassertion, cf9h reset (06h or 0eh), or sys_reset# assertion. 1 = corresponding gpio registers will be reset by rsmrst# assertion only. 7:0 reserved bit description 31:12 reserved 11:8 gp_rst_sel[75:72] ? r/w. 0 = corresponding gpio registers will be re set by pwrok deassertion, cf9h reset (06h or 0eh), or sys_reset# assertion. 1 = corresponding gpio registers will be reset by rsmrst# assertion only. 7:0 reserved
datasheet 553 sata controller registers (d31:f2) 14 sata controller registers (d31:f2) 14.1 pci configuration registers (sataCd31:f2) note: address locations that are not shown should be treated as reserved. all of the sata registers are in the core well. none of the registers can be locked. table 14-1. sata controller pci register address map (sataCd31:f2) (sheet 1 of 2) offset mnemonic register name default attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 02b0h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface see register description see register description 0ah scc sub class code see register description see register description 0bh bcc base class code 01h ro 0dh pmlt primary master latency timer 00h ro 0eh htype header type 00h ro 10h?13h pcmd_bar primary command block base address 00000001h r/w, ro 14h?17h pcnl_bar primary control block base address 00000001h r/w, ro 18h?1bh scmd_bar secondary command block base address 00000001h r/w, ro 1ch?1fh scnl_bar secondary control block base address 00000001h r/w, ro 20h?23h bar legacy bus master base address 00000001h r/w, ro 24h?27h abar / sidpba ahci base address / sata index data pair base address see register description see register description 2ch?2dh svid subsystem vendor identification 0000h r/wo 2eh?2fh sid subsystem identification 0000h r/wo 34h cap capabilities pointer 80h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description ro 40h?41h ide_tim primary ide timing register 0000h r/w
sata controller registers (d31:f2) 554 datasheet note: the pch sata controller is not arbitrated as a pci device; therefore, it does not need a master latency timer. 42h?43h ide_tim secondary ide timing register 0000h r/w 70h?71h pid pci power management capability id see register description ro 72h?73h pc pci power management capabilities see register description ro 74h?75h pmcs pci power management control and status see register description r/w, ro, r/wc 80h?81h msici message signaled in terrupt capability id 7005h ro 82h?83h msimc message signaled interrupt message control 0000h ro, r/w 84h?87h msima message signaled interrupt message address 00000000h ro, r/w 88h?89h msimd message signaled interrupt message data 0000h r/w 90h map address map 0000h r/w, r/wo 92h?93h pcs port control and status 0000h r/w, ro 94h?97h sclkcg sata clock gating control 00000000h r/w 9ch?9fh sclkgc sata clock general configuration 00000000h r/w, r/wo a8h?abh satacr0 sata capability register 0 0010b012h ro, r/wo ach?afh satacr1 sata capability register 1 00000048h ro b0h?b1h flrcid flr capability id 0009h ro b2h?b3h flrclv flr capability length and version see register description r/wo, ro b4h?b5h flrc flr control 0000h ro, r/w c0h atc apm trapping control 00h r/w c4h ats atm trapping status 00h r/wc d0h?d3h sp scratch pad 00000000h r/w e0h?e3h bfcs bist fis control/status 00000000h r/w, r/wc e4h?e7h bftd1 bist fis transmit data, dw1 00000000h r/w e8h?ebh bftd2 bist fis transmit data, dw2 00000000h r/w table 14-1. sata controller pci register address map (sataCd31:f2) (sheet 2 of 2) offset mnemonic register name default attribute
datasheet 555 sata controller registers (d31:f2) 14.1.1 vidvendor identificati on register (satad31:f2) offset address: 00h ? 01h attribute: ro default value: 8086h size: 16 bit lockable: no power well: core 14.1.2 diddevice identificati on register (satad31:f2) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16 bit lockable: no power well: core 14.1.3 pcicmdpci command register (sataCd31:f2) address offset: 04h ? 05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the pch sata controller. note: the value of this field will change dependent upon the value of the map register. see section 14.1.30 bit description 15:11 reserved 10 interrupt disable ? r/w. this disables pin-based intx# interrupts. this bit has no effect on msi operation. 0 = internal intx# messages are generated if there is an interrupt and msi is not enabled. 1 = internal intx# messages will not be generated. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? ro. hardwired to 0. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? r/w. 0 = disabled. sata controller will not gene rate perr# when a data parity error is detected. 1 = enabled. sata controller will generate pe rr# when a data parity error is detected. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle en able (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. this bit controls the sata controller?s ability to act as a master for data transfers. this bit do es not impact the generation of completions for split transaction commands. 1 memory space enable (mse) ? r/w / ro. controls access to the sata controller?s target memory space (for ahci). this bi t is ro 0 when not in ahci/raid modes. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disables access to the legacy or native ide ports (both primary and secondary) as well as the bus mast er i/o registers. 1 = enable. note that the base address register for the bus master registers should be programmed before this bit is set.
sata controller registers (d31:f2) 556 datasheet 14.1.4 pcists pci status register (sataCd31:f2) address offset: 06h ? 07h attribute: r/wc, ro default value: 02b0h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected by sata controller. 1 = sata controller detects a parity error on its interface. 14 signaled system error (sse) ? ro. hardwired to 0. 13 received master abort (rma) ? r/wc. 0 = master abort not generated. 1 = sata controller, as a master , generated a master abort. 12 reserved ? r/wc. 11 signaled target abort (sta) ? ro. hardwired to 0. 10:9 devsel# timing status (dev_sts) ? ro. 01 = hardwired; controls the devi ce select time for the sata controller?s pci interface. 8 data parity error detected (dped) ? r/wc. for pch, this bit can only be set on read completions received from the bus when there is a parity error. 0 = no data parity error received. 1 = sata controller, as a master, either detect s a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6reserved 5 66mhz capable (66mhz_cap) ? ro. hardwired to 1. 4 capabilities list (cap_list) ? ro. this bit indicates the presence of a capabilities list. the minimum requirement for the capabili ties list must be pci power management for the sata controller. 3 interrupt status (ints) ? ro. reflects the state of intx# messages, irq14 or irq15. 0 = interrupt is cleared (ind ependent of the state of in terrupt disabl e bit in the command register [offset 04h]). 1 = interrupt is to be asserted 2:0 reserved
datasheet 557 sata controller registers (d31:f2) 14.1.5 ridrevision identificati on register (satad31:f2) offset address: 08h attribute: ro default value: see bit description size: 8 bits 14.1.6 piprogrammin g interface register (sataCd31:f2) 14.1.6.1 when sub class code register (d31:f2:offset 0ah) = 01h address offset: 09h attribute: r/w, ro default value: 8ah size: 8 bits 14.1.6.2 when sub class code register (d31:f2:offset 0ah) = 04h address offset: 09h attribute: ro default value: 00h size: 8 bits bit description 7:0 revision id ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit description 7 this read-only bit is a 1 to indicate that the pch supports bus master operation 6:4 reserved. will always return 0. 3 secondary mode native capable (snc) ? ro. hardwired to ?1? to indicate secondary controller supports both legacy and native modes. 2 secondary mode nati ve enable (sne) ? r/w. determines the mode th at the secondary channel is operating in. 0 = secondary controller operatin g in legacy (compatibility) mode 1 = secondary controller operating in native pci mode. if this bit is set by software, then the pne bit (bit 0 of this register ) must also be set by software. while in theory these bits can be programmed separately, such a configuration is not supported by hardware. 1 primary mode native capable (pnc) ? ro. hardwired to ?1? to indicate primary controller supports both legacy and native modes. 0 primary mode native enable (pne) ? r/w. determines the mode that the primary channel is operating in. 0 = primary controller operating in legacy (compatibility) mode. 1 = primary controller operating in native pci mode. if this bit is set by software, then the sne bit (bit 2 of this register) must also be set by software simultaneously. bit description 7:0 interface (if) ? ro. when configured as raid, this register becomes read only 0.
sata controller registers (d31:f2) 558 datasheet 14.1.6.3 when sub class code regi ster (d31:f2:offset 0ah) = 06h address offset: 09h attribute: ro default value: 01h size: 8 bits 14.1.7 sccsub class code register (sataCd31:f2) address offset: 0ah attribute: ro default value: see bit description size: 8 bits 14.1.8 bccbase class code register (sataCd31:f2sataCd31:f2) address offset: 0bh attribute: ro default value: 01h size: 8 bits bit description 7:0 interface (if) ? ro. indicates that the sata controller is an ahci hba that has a major revision of 1. bit description 7:0 sub class code (scc) this field specifies the sub-class code of the controller, per the table below: note: not all scc values may be available for a given sku. see section 1.3 for details on storage controller capabilities. map.sms (d31:f2:offset 90h:bit 7:6) value scc register value 00b 01h (ide controller) 01b 06h (ahci controller) 10b 04h (raid controller) bit description 7:0 base class code (bcc) ? ro. 01h = mass storage device
datasheet 559 sata controller registers (d31:f2) 14.1.9 pmltprimary master latency timer register (sataCd31:f2) address offset: 0dh attribute: ro default value: 00h size: 8 bits 14.1.10 htypeheader type register (sataCd31:f2) address offset: 0eh attribute: ro default value: 00h size: 8 bits 14.1.11 pcmd_barprimary co mmand block base address register (sataCd31:f2) address offset: 10h ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits note: this 8-byte i/o space is used in native mo de for the primary controller?s command block. bit description 7:0 master latency timer count (mltc) ? ro. 00h = hardwired. the sata controller is im plemented internally, and is not arbitrated as a pci device, so it does no t need a master latency timer. bit description 7 multi-function device (mfd) ? ro. indicates this sata controller is no t part of a multifunction device. 6:0 header layout (hl) ? ro. indicates that the sata controller uses a target device layout. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the ba se address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space.
sata controller registers (d31:f2) 560 datasheet 14.1.12 pcnl_barprimary contro l block base address register (sataCd31:f2) address offset: 14h ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mo de for the primary controller?s control block. 14.1.13 scmd_barsecondary co mmand block base address register (sata d31:f2) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 8-byte i/o space is used in native mode for the secondary controller?s command block. 14.1.14 scnl_barsecondary co ntrol block base address register (sata d31:f2) address offset: 1ch ? 1fh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary cont roller?s control block. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the ba se address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the ba se address of the i/o space (4 consecutive i/o locations). 1reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space.
datasheet 561 sata controller registers (d31:f2) 14.1.15 barlegacy bus mast er base address register (sataCd31:f2) address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits the bus master ide interface function uses base address register 5 to request a 16- byte i/o space to provide a software interface to the bus master functions. only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). only bits [15:4] are used to decode the address. 14.1.16 abar/sidpba1ahci base address register/serial ata index data pair base address (sataCd31:f2) when the programming interface is not ide (that is, scc is not 01h), this register is named abar. when the programming interface is ide, this register becomes sidpba. note that hardware does not clear those ba bits when switching from ide component to non-ide component or vice versa. bios is responsible for clearing those bits to 0 since the number of writable bits changes after component switching (as indicated by a change in scc). in th e case, this register will then have to be re-programmed to a proper value. 14.1.16.1 when scc is not 01h when the programming interface is not ide, the register represents a memory bar allocating space for the ahci memory registers defined in section 14.4 . . address offset: 24?27h attribute: r/w, ro default value: 00000000h size: 32 bits note: 1. the abar register must be set to a value of 0001_0000h or greater. bit description 31:16 reserved 15:5 base address ? r/w. this field provides the base address of the i/o space (16 consecutive i/o locations). 4 base ? r/w / ro. when scc is 01h, this bit will be r/w resulting in requesting 16b of i/o space. when scc is not 01h, this bit will be read only 0, resulting in requesting 32b of i/o space. 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:11 base address (ba) ? r/w. base address of register memory space (aligned to 2 kb) 10:4 reserved 3 prefetchable (pf) ? ro. indicates that this range is not pre-fetchable 2:1 type (tp) ? ro. indicates that this range can be mapped anywhere in 32-bit address space. 0 resource type indicator (rte) ? ro. hardwired to 0 to indicate a request for register memory space.
sata controller registers (d31:f2) 562 datasheet 14.1.16.2 when scc is 01h when the programming interface is ide, the register becomes an i/o bar allocating 16 bytes of i/o space for the i/o-mapped registers defined in section 14.2 . note that although 16 bytes of locations are allocated, only 8 bytes are used as sindx and sdata registers; with the remaining 8 bytes preserved for future enhancement. address offset: 24h ? 27h attribute: r/wo default value: 00000001h size: 32 bits 14.1.17 svidsubsystem vendor identification register (sataCd31:f2) address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core function level reset: no 14.1.18 sidsubsystem identifica tion register (sataCd31:f2) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core function level reset: no 14.1.19 capcapabilities poin ter register (sataCd31:f2) address offset: 34h attribute: ro default value: 80h size: 8 bits bit description 31:16 reserved 15:4 base address (ba) ? r/w. base address of the i/o space. 3:1 reserved 0 resource type indicator (rte) ? ro. indicates a request for i/o space. bit description 15:0 subsystem vendor id (svid) ? r/wo. value is written by bios. no hardware action taken on this value. bit description 15:0 subsystem id (sid) ? r/wo. value is written by bios. no hardware action taken on this value. bit description 7:0 capabilities pointer (cap_ptr) ? ro. indicates that the first capability pointer offset is 80h. this value changes to 70h if the sub class code (scc) (dev 31:f2:0ah) is configure as ide mode (value of 01).
datasheet 563 sata controller registers (d31:f2) 14.1.20 int_lninterrupt line register (sataCd31:f2) address offset: 3ch attribute: r/w default value: 00h size: 8 bits function level reset: no 14.1.21 int_pninterrupt pi n register (sataCd31:f2) address offset: 3dh attribute: ro default value: see register description size: 8 bits 14.1.22 ide_timide timing register (sataCd31:f2) address offset: primary: 40h ? 41h attribute: r/w secondary: 42h ? 43h default value: 0000h size: 16 bits 14.1.23 pidpci power management capability identification register (sataCd31:f2) address offset: 70h ? 71h attribute: ro default value: see register description size: 16 bits bit description 7:0 interrupt line ? r/w. this field is used to communicate to software the interrupt line that the interrupt pin is connected to. interrupt line register is not reset by flr. bit description 7:0 interrupt pin ? ro. this reflects the value of d31ip.sip (chipset config registers:offset 3100h:bits 11:8). bit description 15 ide decode enable (ide) ? r/w. individually enable/disable the primary or secondary decode. 0 = disable. 1 = enables the pch to decode the associat ed command blocks (1f0?1f7h for primary, 170?177h for secondary, or their native mode bar equivalents) and control block (3f6h for primary, 376h for secondary, or their native mode bar equivalents). this bit effects the ide deco de ranges for both legacy and native-mode decoding. 14:0 reserved bits description 15:8 next capability (next) ? ro. b0h ? if scc = 01h (ide mode) indicating next item is flr capability pointer. a8h ? for all other values of scc to po int to the next capability structure. 7:0 capability id (cid) ? ro. hardwired to 01h. indicates that this pointer is a pci power management.
sata controller registers (d31:f2) 564 datasheet 14.1.24 pcpci power manageme nt capabilities register (sataCd31:f2) address offset: 72h ? 73h attribute: ro default value: see register description size: 16 bits bits description 15:11 pme support (pme_sup) ? ro. 00000 = if scc = 01h, indicates no pme support in ide mode. 01000 = if scc is not 01h, in a non-ide mode, indicates pme# can be generated from the d3 hot state in the sata host controller. 10 d2 support (d2_sup) ? ro. hardwired to 0. the d2 state is not supported 9 d1 support (d1_sup) ? ro. hardwired to 0. the d1 state is not supported 8:6 auxiliary current (aux_cur) ? ro. pme# from d3 cold state is not supported, therefore this field is 000b. 5 device specific initialization (dsi) ? ro. ha rdwired to 0 to indicate that no device- specific initialization is required. 4 reserved 3 pme clock (pme_clk) ? ro. hardwired to 0 to in dicate that pci clock is not required to generate pme#. 2:0 version (ver) ? ro. hardwired to 011 to indicates support for revision 1.2 of the pci power management specification.
datasheet 565 sata controller registers (d31:f2) 14.1.25 pmcspci power mana gement control and status register (sataCd31:f2) address offset: 74h ? 75h attribute: r/w, r/wc default value: 0008h size: 16 bits function level reset: no (bits 8 and 15) bits description 15 pme status (pmes) ? r/wc. bit is set when a pme event is to be requested, and if this bit and pmee is set, a pme# will be generated from the sata controller note: whenever scc = 01h, hardware will auto matically change the attribute of this bit to ro 0. software is advised to clear pmee and pmes together prior to changing scc thru map.sms. this bit is not reset by function level reset. 14:9 reserved 8 pme enable (pmee) ? r/w. when set, the sata co ntroller generates pme# form d3 hot on a wake event. note: whenever sccscc = 01h, hardware will automatically change the attribute of this bit to ro 0. software is advised to clear pmee and pmes together prior to changing scc thru map.sms. this bit is not reset by function level reset. 7:4 reserved 3 no soft reset (nsfrst) ? ro. these bits are used to indicate whether devices transitioning from d3 hot state to d0 state will perform an internal reset. 0 = device transitioning from d3 hot state to d0 state perfo rm an internal reset. 1 = device transitioning from d3 hot state to d0 state do not perform an internal reset. configuration content is preserved. upon transition from the d3 hot state to d0 state initialized state, no addition al operating system interventi on is required to preserve configuration context beyond writing to the powerstate bits. regardless of this bit, the controller transition from d3 hot state to d0 state by a system or bus segment reset will return to the state d0 uninitialized with only pme context preserved if pme is supported and enabled. 2reserved 1:0 power state (ps) ? r/w. these bits are used both to determine the current power state of the sata controller and to set a new power state. 00 = d0 state 11 = d3 hot state when in the d3 hot state, the controller?s configurat ion space is available, but the i/o and memory spaces are not. addi tionally, interrupts are blocked.
sata controller registers (d31:f2) 566 datasheet 14.1.26 msicimessage signal ed interrupt capability identification register (sataCd31:f2) address offset: 80h ? 81h attribute: ro default value: 7005h size: 16 bits note: there is no support for msi when the software is operating in legacy (ide) mode when ahci is not enabled. prior to switching from ahci to ide mode, software must make sure that msi is disabled. 14.1.27 msimcmessage sign aled interrupt message control register (sataCd31:f2) address offset: 82h ? 83h attribute: r/w, ro default value: 0000h size: 16 bits note: there is no support for msi when the software is operating in legacy (ide) mode when ahci is not enabled. prior to switching from ahci to ide mode, software must make sure that msi is disabled. bits description 15:8 next pointer (next) ? ro. indicates the next item in the list is the pci power management pointer. 7:0 capability id (cid) ? ro. capabilities id indicates msi. bits description 15:8 reserved 7 64 bit address capable (c64) ? ro. capable of generating a 32-bit message only.
datasheet 567 sata controller registers (d31:f2) 6:4 multiple message enable (mme) ? ro. = 000 (and msie is set), a single msi messag e will be generated fo r all sata ports, and bits [15:0] of the message vector will be driven from md[15:0]. all other mme values are reserved. if this field is set to one of these reserved values, the results are undefined. note: the ccc interrupt is generated on unimple mented port (ahci pi register bit equal to 0). if ccc interrupt is disabled, no msi shall be gene rated for the port dedicated to the ccc interrupt. when ccc interrupt occurs, md[2:0] is dependant on ccc_ctl.int (in addition to mme). 3:1 multiple message ca pable (mmc) ? ro. mmc is not supported. 0 msi enable (msie) ? r/w /ro. if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. this bit is r/w when sc.scc is not 01h and is read- only 0 when scc is 01h. note that cmd.id bit has no effect on msi. note: software must clear this bit to 0 to di sable msi first before changing the number of messages allocated in the mmc field. software must also make sure this bit is cleared to ?0? when operating in legacy mode (when ghc.ae = 0). bits description for 6 port components: mme value driven on msi memory write bits[15:3] bit[2] bit[1] bit[0] 000, 001, 010 md[15:3] md[2] md[1] md[0] 011 md[15:3] port 0: 0 port 1: 0 port 2: 0 port 3: 0 port 4: 1 port 5: 1 port 0: 0 port 1: 0 port 2: 1 port 3: 1 port 4: 0 port 5: 0 port 0: 0 port 1: 1 port 2: 0 port 3: 1 port 4: 0 port 5: 1 for 4 port components: mme value driven on msi memory write bits[15:3] bit[2] bit[1] bit[0] 000, 001, 010 md[15:3] md[2] md[1] md[0] 011 md[15:3] port 0: 0 port 1: 0 port 4: 1 port 5: 1 port 0: 0 port 1: 0 port 2: 0 port 3: 0 port 0: 0 port 1: 1 port 2: 0 port 3: 1
sata controller registers (d31:f2) 568 datasheet 14.1.28 msima message sign aled interrupt message address register (sataCd31:f2) address offset: 84h ? 87h attribute: r/w default value: 00000000h size: 32 bits note: there is no support for msi when the software is operating in legacy (ide) mode when ahci is not enabled. prior to switching from ahci to ide mode, software must make sure that msi is disabled. 14.1.29 msimdmessage sign aled interrupt message data register (sataCd31:f2) address offset: 88h?89h attribute: r/w default value: 0000h size: 16 bits note: there is no support for msi when the software is operating in legacy (ide) mode when ahci is not enabled. prior to switching from ahci to ide mode, software must make sure that msi is disabled. bits description 31:2 address (addr) ? r/w. lower 32 bits of the system specified message address, always dword aligned. 1:0 reserved bits description 15:0 data (data) ? r/w. this 16-bit field is programmed by system software if msi is enabled. its content is driven onto the lowe r word of the data bu s of the msi memory write transaction. note that when the mme field is set to ?001? or ?010?, bit [0] and bits [1:0] respectively of the msi memory write transaction will be driven based on the source of the interrupt rather than from md[2:0]. see the description of the mme field.
datasheet 569 sata controller registers (d31:f2) 14.1.30 mapaddress map re gister (sataCd31:f2) address offset: 90h attribute: r/w, r/wo default value: 0000h size: 16 bits function level reset: no (bits 7:5 and 13:8 only) bits description 15:8 reserved 7:6 sata mode select (sms) ? r/w. software programs these bi ts to control the mode in which the sata controller should operate: 00b = ide mode 01b = ahci mode 10b = raid mode 11b = reserved notes: 1. the sata function device id will chan ge based on the value of this register. 2. when switching from ahci or raid mode to ide mode, a 2 port sata controller (device 31, function 5) will be enabled. 3. sw shall not manipulate sms during runt ime operation; that is. the os will not do this. the bios may choose to switch from one mode to another during post. 4. not all register values may be available for a given sku. see section 1.3 for details on storage cont roller capabilities. these bits are not reset by function level reset. 5 sata port-to-controller configuration (sc) ? r/w. this bit changes the number of sata ports available within each sata controller. 0 = up to 4 sata ports are available for cont roller 1 (device 31 func tion 2) with ports [3:0] and up to 2 sata ports are available for controller 2 (device 31 function 5) with ports [5:4]. 1 = up to 6 sata ports are available for cont roller 1 (device 31 func tion 2) with ports [5:0] and no sata ports are available for controller 2 (device 31 function 5). note: this bit should be set to 1 in ahci/raid mode. this bit is no t reset by function level reset. 4:0 reserved
sata controller registers (d31:f2) 570 datasheet 14.1.31 pcsport control and status register (sataCd31:f2) address offset: 92h ? 93h attribute: r/w, ro default value: 0000h size: 16 bits function level reset: no by default, the sata ports are set to the di sabled state (bits [5:0] = 0). when enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices. when disabled, the port is in the ?off? state and cannot detect any devices. if an ahci-aware or raid enabled operating system is being booted, then system bios shall insure that all supported sata ports are enabled prior to passing control to the os. once the ahci aware os is booted, it becomes the enabling/disabling policy owner for the individual sata ports. this is acco mplished by manipulating a port?s pxsctl and pxcmd fields. because an ahci or raid awar e os will typically not have knowledge of the pxe bits and because the pxe bits act as master on/off switches for the ports, pre- boot software must insure that these bits are set to 1 prior to booting the os, regardless as to whether or not a device is currently on the port. bits description 15 oob retry mode (orm) ? r/w. 0 = the sata controller will not retry after an oob failure 1 = the sata controller will continue to retry after an oob fa ilure until successful (infinite retry) 14 reserved 13 port 5 present (p5p) ? ro. the status of this bit ma y change at any time. this bit is cleared when the port is disabled using p5e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 5 has been detected. 12 port 4 present (p4p) ? ro. the status of this bit ma y change at any time. this bit is cleared when the port is disabled using p4e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 4 has been detected. 11 port 3 present (p3p) ? ro. the status of this bit ma y change at any time. this bit is cleared when the port is disabled using p3e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 3 has been detected. note: bit may be reserved depending on if po rt is available in the given sku. see section 1.3 for details if port is available. 10 port 2 present (p2p) ? ro. the status of this bit ma y change at any time. this bit is cleared when the port is disabled using p2e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 2 has been detected. note: bit may be reserved depending on if po rt is available in the given sku. see section 1.3 for details if port is available. 9 port 1 present (p1p) ? ro. the status of this bit ma y change at any time. this bit is cleared when the port is disabled using p1e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 1 has been detected.
datasheet 571 sata controller registers (d31:f2) 8 port 0 present (p0p) ? ro. the status of this bit ma y change at any time. this bit is cleared when the port is disabled using p0e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 0 has been detected. 7:6 reserved 5 port 5 enabled (p5e) ? r/w / ro. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition betwee n the on, partial, and slumber states and can detect devices. note: 1. this bit takes precedence over p5cmd.sud (offset abar+398h:bit 1) 2. if map.sc is 0, scc is 01h, or map.spd[5] is 1h, then this bit will be read only 0. 4 port 4 enabled (p4e) ? r/w / ro. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition betwee n the on, partial, and slumber states and can detect devices. note: 1. this bit takes precedence over p4cmd.sud (offset abar+318h:bit 1) 2. if map.sc is 0, scc is 01h, or map.spd[4] is 1h, then this bit will be read only 0. 3 port 3 enabled (p3e) ? r/w / ro. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition betwee n the on, partial, and slumber states and can detect devices. note: 1. this bit takes precedence over p3cm d.sud (offset abar+2 98h:bit 1). when map.spd[3] is 1 this is re served and is read-only 0. 2. bit may be reserved and ro depending on if port is availabl e in the given sku. see section 1.3 for details if port is available. 2 port 2 enabled (p2e) ? r/w / ro. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition betwee n the on, partial, and slumber states and can detect devices. note: 1. this bit takes precedence over p2cm d.sud (offset abar+2 18h:bit 1). when map.spd[2] is 1 this is re served and is read-only 0. 2. bit may be reserved and ro depending on if port is availabl e in the given sku. see section 1.3 for details if port is available. 1 port 1 enabled (p1e) ? r/w / ro. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition betwee n the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p1cm d.sud (offset abar+1 98h:bit 1). when map.spd[1] is 1 this is re served and is read-only 0. 0 port 0 enabled (p0e) ? r/w / ro. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition betwee n the on, partial, and slumber states and can detect devices. note: th is bit takes precedence over p0cm d.sud (offset abar+1 18h:bit 1). when map.spd[0] is 1 this is re served and is read-only 0. bits description
sata controller registers (d31:f2) 572 datasheet 14.1.32 sclkcgsata clock gating control register address offset: 94h?97h attribute: r/w default value: 00000000h size: 32 bits 14.1.33 sclkgcsata clock gene ral configuration register address offset: 9ch?9fh attribute: r/w, r/wo default value: 00000000h size: 32 bits function level reset: no bit description 31:30 reserved 29:24 port clock disable (pcd) ? r/w. 0 = all clocks to the associated port logic will operate normally. 1 = the backbone clock driven to the associated port lo gic is gated and will not toggle. bit 29: port 5 bit 28: port 4 bit 27: port 3 bit 26: port 2 bit 25: port 1 bit 24: port 0 if a port is not available, software shall set the corresponding bi t to 1. software can also set the corresponding bits to 1 on ports that are disabled. software cannot set the pcd [port x]=1 if the corresponding pcs.pxe=1 in either dev31func2 or dev31func5 (dual controller ide mode) or ahci ghc.pi[x] = ?1?. 23:9 reserved 8:0 sclkcg field 1 ? r/w. bios must program these bits to 183h. bit description 31:8 reserved 7 (non-raid capable skus only) reserved 7 (raid capable skus only) alternate id enable (aie) ? r/wo. 0 = when in raid mode the sata controller located at device 31: function 2 will report the device id 2822h for desktop or 282ah for mobile and the microsoft windows vista* and windows* 7 in-box version of the intel ? rapid storage manager will load on the platform. 1 = when in raid mode the sata controller located at device 31: function 2 will report the device id 1c04h for deskto p raid 0/1/5/10 without intel? smart response technology, 1c06h for desktop raid 0/1/5/10 with intel smart response technology, or 1c05h for mobile to prevent the microsoft windows vista or windows 7 in-box version of the intel ? rapid storage manager from loading on the platform and will require the user to perform an ?f6? installation of the appropriate intel ? rapid storage manager. note: this field is applicable when the ah ci is configured for raid mode of operation. it has no impact for ahci and ide modes of operation. bios is recommended to program this bit prio r to programming the map.sms field to reflect raid. this fi eld is reset by pltrst#. bios is required to reprogram the value of this bit after resuming from s3, s4, and s5. 6:1 reserved
datasheet 573 sata controller registers (d31:f2) 14.1.34 satacr0sata capabilit y register 0 (sataCd31:f2) address offset: a8h?abh attribute: ro, r/wo default value: 0010b012h size: 32 bits function level reset: no (bits 15:8 only) note: this register is read-only 0 when scc is 01h. 0 sata 4-port all master config uration indicator (sata4pmind) ? ro. 0 = normal configuration. 1 = two ide controllers are implemented, each supporting two ports for a primary master and a secondary master. note: bios must also make sure that corres ponding port clocks are gated (using sclkcg configuration register). bit description bit description 31:24 reserved 23:20 major revision (majrev) ? ro. major revision number of the sata capability pointer implemented. 19:16 minor revision (minrev) ? ro. minor revision number of the sata capability pointer implemented. 15:8 next capability pointer (next) ? r/wo. points to the next capability structure. these bits are not reset by function level reset. 7:0 capability id (cap) ? ro. this value of 12h has been assigned by the pci sig to designate the sata capability structure.
sata controller registers (d31:f2) 574 datasheet 14.1.35 satacr1sata capability register 1 (sataCd31:f2) address offset: ach?afh attribute: ro default value: 00000048h size: 32 bits note: this register is read-only 0 when scc is 01h. 14.1.36 flrcidflr capability id register (sataCd31:f2) address offset: b0?b1h attribute: ro default value: 0009h size: 16 bits bit description 31:16 reserved 15:4 bar offset (barofst) ? ro. indicates the offset into the bar where the index/data pair are located (in dword granularity). the index and data i/o registers are located at offset 10h within the i/o space defined by lbar. a value of 004h indicates offset 10h. 000h = 0h offset 001h = 4h offset 002h = 8h offset 003h = bh offset 004h = 10h offset ... fffh = 3fffh offset (max 16kb) 3:0 bar location (barloc) ? ro. indicates the absolute pci configuration register address of the bar containing the index/data pair (in dword granularity). the index and data i/o registers reside within the space defined by lb ar in the sata controller. a value of 8h indicates offs et 20h, which is lbar. 0000 ? 0011b = reserved 0100b = 10h => bar0 0101b = 14h => bar1 0110b = 18h => bar2 0111b = 1ch => bar3 1000b = 20h => lbar 1001b = 24h => bar5 1010?1110b = reserved 1111b = index/data pair in pci configuratio n space. this is not supported in the pch. bit description 15:8 next capability pointer ? ro. 00h indicates the final item in the capability list. 7:0 capability id ? ro. the value of this fiel d depends on the flrcssel (rcba+3410h:bit 12) bit. flrcssel (rcba+3410h:bit 12) value capability id register value 0b 13h 1b 09h (vendor specific)
datasheet 575 sata controller registers (d31:f2) 14.1.37 flrclvflr capability le ngth and version register (sataCd31:f2) address offset: b2?b3h attribute: ro, r/wo default value: xx06h size: 16 bits function level reset: no (bit 9:8 only when flrcssel = 0) when flrcssel (rcba+3410h:bit 12) = 0, this register is defined as follows: when flrcssel = 1, this register is defined as follows: 14.1.38 flrcflr control re gister (sataCd31:f2) address offset: b4?b5h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:10 reserved 9 flr capability ? r/wo. 1 = support for function level reset. this bit is not reset by the function level reset. 8 txp capability ? r/wo. 1 = support for transactions pending (txp) bit. txp must be supported if flr is supported. 7:0 vendor-specific capability id ? ro. this field indicates the number of bytes of this vendor specific capability as required by th e pci specification. it has the value of 06h for the flr capability. bit description 15:12 vendor-specific capability id ? ro. a value of 2h identifi es this capability as the function level reset (flr). 11:8 capability version ? ro. this field indicates the version of the flr capability. 7:0 vendor-specific capability id ? ro. this field indicates the number of bytes of this vendor specific capability as required by th e pci specification. it has the value of 06h for the flr capability. bit description 15:9 reserved 8 transactions pending (txp) ? ro. 0 = controller has received all non-posted requests. 1 = controller has issued non-posted requests which has not been completed. 7:1 reserved 0 initiate flr ? r/w. used to initiate flr transition. a write of 1 indicates flr transition. since hardware must not respond to any cycles till flr completion the value read by software from this bit is 0.
sata controller registers (d31:f2) 576 datasheet 14.1.39 atcapm trapping cont rol register (sataCd31:f2) address offset: c0h attribute: r/w default value: 00h size: 8 bits function level reset: no 14.1.40 atsapm trapping stat us register (sataCd31:f2) address offset: c4h attribute: r/wc default value: 00h size: 8 bits function level reset: no 14.1.41 sp scratch pad register (sataCd31:f2) address offset: d0h attribute: r/w default value: 00000000h size: 32 bits bit description 7:4 reserved 3 secondary slave trap (sst) ? r/w. enables trapping and smi# assertion on legacy i/o accesses to 170h?177h and 376h. the active device on the secondary interface must be device 1 for the trap and/or smi# to occur. 2 secondary master trap (spt) ? r/w. enables trapping and smi# assertion on legacy i/o accesses to 170h-177h and 376h. the active device on the secondary interface must be device 0 for the trap and/or smi# to occur. 1 primary slave trap (pst) ? r/w. enables trapping and smi# assertion on legacy i/ o accesses to 1f0h?1f7h and 3f6h. the active device on the primary interface must be device 1 for the trap and/or smi# to occur. 0 primary master trap (pmt) ? r/w. enables trapping and smi# assertion on legacy i/o accesses to 1f0h?1f7h and 3f6h. the acti ve device on the pr imary interface must be device 0 for the trap and/or smi# to occur. bit description 7:4 reserved 3 secondary slave trap (sst) ? r/wc. indicates that a trap occurred to the secondary slave device. 2 secondary master trap (spt) ? r/wc. indicates that a trap occurred to the secondary master device. 1 primary slave trap (pst) ? r/wc. indicates that a trap occurred to the primary slave device. 0 primary master trap (pmt) ? r/wc. indicates that a trap occurred to the primary master device. bit description 31:0 data (dt) ? r/w. this is a read/write register that is available for software to use. no hardware action is taken on this register.
datasheet 577 sata controller registers (d31:f2) 14.1.42 bfcsbist fis control/st atus register (sataCd31:f2) address offset: e0h ? e3h attribute: r/w, r/wc default value: 00000000h size: 32 bits bits description 31:16 reserved 15 port 5 bist fis initiate (p5bfi) ? r/w. when a rising edge is detected on this bit field, the pch initiates a bist fis to the device on port 5, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 5 is present and read y (not partial/slumber state). after a bist fis is successfully completed, soft ware must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fiss or to return the pch to a normal op erational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p5bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully. 14 port 4 bist fis initiate (p4bfi) ? r/w. when a rising edge is detected on this bit field, the pch initiates a bist fis to the device on port 4, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 4 is present and read y (not partial/slumber state). after a bist fis is successfully completed, soft ware must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fiss or to return the pch to a normal op erational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p4bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully. 13 port 3 bist fis initiate (p3bfi) ? r/w. when a rising edge is detected on this bit field, the pch initiates a bist fis to the device on port 3, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 3 is present and read y (not partial/slumber state). after a bist fis is successfully completed, soft ware must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fiss or to return the pch to a normal op erational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p3bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully. note: bit may be reserved depending on if po rt is available in the given sku. see section 1.3 for details if port is available. 12 port 2 bist fis initiate (p2bfi) ? r/w. when a rising edge is detected on this bit field, the pch initiates a bist fis to the device on port 2, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 2 is present and read y (not partial/slumber state). after a bist fis is successfully completed, soft ware must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fises or to return the pch to a normal op erational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then software can clear then set the p2bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully. note: bit may be reserved depending on if po rt is available in the given sku. see section 1.3 for details if port is available.
sata controller registers (d31:f2) 578 datasheet 11 bist fis successful (bfs) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a bist fis transmitted by pch receives an r_ok completion status from the device. note: this bit must be cleared by softwa re prior to initiating a bist fis. 10 bist fis failed (bff) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a bist fis transmitted by pch receives an r_err completion status from the device. note: this bit must be cleared by softwa re prior to initiating a bist fis. 9 port 1 bist fis initiate (p1bfi) ? r/w. when a rising edge is detected on this bit field, the pch initiates a bist fis to the device on port 1, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 1 is present and read y (not partial/slumber state). after a bist fis is successfully completed, software must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fises or to return the pch to a normal op erational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, th en software can clear then set the p1bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully. 8 port 0 bist fis initiate (p0bfi) ? r/w. when a rising edge is detected on this bit field, the pch initiates a bist fis to the device on port 0, using the parameters specified in this register and the data sp ecified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 0 is present and read y (not partial/slumber state). after a bist fis is successfully completed, software must disable and re- enable the port using the pxe bits at offset 92h prior to attempting additional bist fises or to return the pch to a normal op erational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, th en software can clear then set the p0bfi bit to initiate another bist fis. this can be retried until the bist fis eventually completes successfully. 7:2 bist fis parameters (bfp) ? r/w. these 6 bits form the contents of the upper 6 bits of the bist fis pattern definition in any bist fis transmitted by the pch. this field is not port specific ? its contents will be used for any bist fis initiated on port 0, port 1, port 2, or port 3. the specific bit definitions are: bit 7: t ? far end transmit mode bit 6: a ? align bypass mode bit 5: s ? bypass scrambling bit 4: l ? far end retimed loopback bit 3: f ? far end analog loopback bit 2: p ? primitive bit for use with transmit mode 1:0 reserved bits description
datasheet 579 sata controller registers (d31:f2) 14.1.43 bftd1bist fis transmit data1 register (sataCd31:f2) address offset: e4h ? e7h attribute: r/w default value: 00000000h size: 32 bits 14.1.44 bftd2bist fis transmit data2 register (sataCd31:f2) address offset: e8h ? ebh attribute: r/w default value: 00000000h size: 32 bits bits description 31:0 bist fis transmit data 1 ? r/w. the data programmed into this register will form the contents of the second dword of any bist fis initiated by the pch. this register is not port specific?its contents will be used for bist fis in itiated on any port. although the 2nd and 3rd dws of the bist fis are only meaningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 2nd dw regardless of whether or not the ?t? bit is indicated in the bfcs register (d31:f2:e0h). bits description 31:0 bist fis transmit data 2 ? r/w. the data programmed into this register will form the contents of the third dword of any bist fis initiated by the pch. this register is not port specific?its contents will be used for bist fis initia ted on any port. although the 2nd and 3rd dws of the bist fis are only me aningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 3rd dw regardless of whether or not the ?t? bit is indicated in the bfcs register (d31:f2:e0h).
sata controller registers (d31:f2) 580 datasheet 14.2 bus master ide i/ o registers (d31:f2) the bus master ide function uses 16 bytes of i/o space, allocated using the bar register, located in device 31:function 2 configuration space, offset 20h. all bus master ide i/o space registers can be accessed as byte, word, or dword quantities. reading reserved bits returns an indetermin ate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). these registers are only used for legacy operation. software must not use these registers when running ahci. all i/o registers are reset by function level reset. the register address i/o map is shown in table 14-2 . table 14-2. bus master ide i/o register address map bar+ offset mnemonic register default attribute 00h bmicp command register primary 00h r/w 01h ? reserved ? ro 02h bmisp bus master ide status register primary 00h r/w, r/wc, ro 03h ? reserved ? ro 04h?07h bmidp bus master ide descriptor table pointer primary xxxxxxxxh r/w 08h bmics command register secondary 00h r/w 09h ? reserved ? ro 0ah bmiss bus master ide status register secondary 00h r/w, r/wc, ro 0bh ? reserved ? ro 0ch?0fh bmids bus master ide descriptor table pointer secondary xxxxxxxxh r/w 10h air ahci index register 00000000h r/w, ro 14h aidr ahci index data register xxxxxxxxh r/w
datasheet 581 sata controller registers (d31:f2) 14.2.1 bmic[p,s]bus master id e command register (d31:f2) address offset: primary: bar + 00h attribute: r/w secondary: bar + 08h default value: 00h size: 8 bits bit description 7:4 reserved. returns 0. 3 read / write control (r/wc) ? r/w. this bit sets the di rection of the bus master transfer. this bit must not be changed wh en the bus master function is active. 0 = memory reads 1 = memory writes 2:1 reserved. returns 0. 0 start/stop bus master (start) ? r/w. 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. if this bit is reset while bus master operation is still active (that is, the bus master ide active bit (d31:f2:bar + 02h, bit 0) of the bus master ide status register for that ide channel is set) and the drive has not yet finished its data transfer (the interrupt bi t in the bus master id e status register for that ide channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the controller. bus master operation does not actually start unless the bus master enable bit (d31:f2:04h, bit 2) in pci configuration space is also set. bus master operation begins when this bit is detected changing from 0 to 1. the controller will transfer data between the ide device and memory only when this bit is set. master operation can be halted by writing a 0 to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bu s master ide active bit being cleared or the interrupt bit of the bus master ide status register fo r that ide channel being set, or both. hardware does not clea r this bit automatically. if this bit is cleared to 0 prior to the dma data transfer being initiated by the drive in a device to memory data transfer, then th e pch will not send dmat to terminate the data transfer. sw intervention (such as, sending srst) is required to reset the interface in this condition.
sata controller registers (d31:f2) 582 datasheet 14.2.2 bmis[p,s]bus master id e status register (d31:f2) address offset: primary: bar + 02h attribute: r/w, r/wc, ro secondary: bar + 0ah default value: 00h size: 8 bits bit description 7 simplex only ? ro. 0 = both bus master channels (primary and secondary) can be op erated independently and can be used at the same time. 1 = only one channel may be used at the same time. 6 drive 1 dma capable ? r/w. 0 = not capable. 1 = capable. set by device dependent code (b ios or device driver ) to indicate that drive 1 for this channel is capable of dm a transfers, and that the controller has been initialized for optimum performance. the pch does not use this bit. it is intended for systems that do no t attach bmide to the pci bus. 5 drive 0 dma capable ? r/w. 0 = not capable 1 = capable. set by device dependent code (b ios or device driver ) to indicate that drive 0 for this channel is capable of dm a transfers, and that the controller has been initialized for optimum performance. the pch does not use this bit. it is intended for systems that do no t attach bmide to the pci bus. 4:3 reserved. returns 0. 2 interrupt ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set when a device fis is received with the ?i? bit set, provided that software has not disabled interrupts using the ien bit of th e device control regi ster (see chapter 5 of the serial ata specification , revision 1.0a). 1 error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the controller encoun ters a target abort or master abort when transferring data on pci. 0 bus master ide active (act) ? ro. 0 = this bit is cleared by the pch when the last transfer for a region is performed, where eot for that region is set in the regi on descriptor. it is also cleared by the pch when the start bus master bit (d31:f2:bar+ 00h, bit 0) is cleared in the command register. when this bit is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = set by the pch when the start bit is written to the command register.
datasheet 583 sata controller registers (d31:f2) 14.2.3 bmid[p,s]bus master id e descriptor table pointer register (d31:f2) address offset: primary: bar + 04h?07h attribute: r/w secondary: bar + 0ch ? 0fh default value: all bits undefined size: 32 bits 14.2.4 airahci index register (d31:f2) address offset: primary: bar + 10h attribute: r/w default value: 00000000h size: 32 bits this register is available only when scc is not 01h. 14.2.5 aidrahci index da ta register (d31:f2) address offset: primary: bar + 14h attribute: r/w default value: all bits undefined size: 32 bits this register is available only when scc is not 01h. bit description 31:2 address of descriptor table (addr) ? r/w. the bits in this field correspond to bits [31:2] of the memory location of the physic al region descriptor (prd). the descriptor table must be dword-aligned. the descriptor table must not cross a 64-k boundary in memory. 1:0 reserved bit description 31:11 reserved 10:2 index (index) ? r/w. this index register is used to select the dword offset of the memory mapped ahci register to be access ed. a dword, word or byte access is specified by the active byte enables of the i/o access to the data register. 1:0 reserved bit description 31:0 data (data) ? r/w : this data register is a ?window? through which data is read or written to the ahci memory mapped registers. a read or write to this data register triggers a corresponding read or write to the memory mapped register pointed to by the index register. the index re gister must be setup prior to the read or write to this data register. note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. since this is not a physical register, the ?default? value is the same as the default value of the register pointed to by index.
sata controller registers (d31:f2) 584 datasheet 14.3 serial ata index/data pair superset registers all of these i/o registers are in the core we ll. they are exposed only when scc is 01h (that is, ide programming interface). these are index/data pair registers that are used to access the serialata superset registers (serialata status (pxssts), seri alata control (pxsctl) and serialata error (pxserr)). the i/o space for these registers is allocated through sidpba. locations with offset from 08h to 0fh are reserved for future expansion. software-write operations to the reserved locations will have no effect while software-read operations to the reserved locations will return 0. 14.3.1 sindxserial ata in dex register (d31:f2) address offset: sidpba + 00h attribute: r/w default value: 00000000h size: 32 bits offset m nemonic register 00h?03h sindex serial ata index 04h?07h sdata serial ata data 08h?0ch ? reserved 0ch?0fh ? reserved bit description 31:16 reserved 15.8 port index (pidx) r/w. this index field is used to specify the port of the sata controller at which the po rt-specific ssts, sctl, and serr registers are located. 00h = primary master (port 0) 01h = primary slave (port 2) 02h = secondary master (port 1) 03h = secondary slave (port 3) all other values are reserved. 7:0 register index (ridx) r/w. this index field is used to specify one out of three registers currently bein g indexed into. these three regist ers are the serial ata superset sstatus, scontrol and serror memory regist ers and are port specific, hence for this sata controller, there are four se ts of these registers. refer to section 14.4.2.10 , section 14.4.2.11 , and section 14.4.2.12 for definitions of the sstatus, scontrol and serror registers. 00h = ssts 01h = sctl 02h = serr all other values are reserved.
datasheet 585 sata controller registers (d31:f2) 14.3.2 sdataserial ata data register (d31:f2) address offset: sidpba + 04h attribute: r/w default value: 00000000h size: 32 bits 14.3.2.1 pxsstsserial ata status register (d31:f2) address offset: attribute: ro default value: 00000000h size: 32 bits sdata when sindx.ridx is 00h. this is a 32-b it register that conveys the current state of the interface and host. th e pch updates it continuously and asynchronously. when the pch transmits a comreset to the device , this register is updated to its reset values. bit description 31:0 data (data) r/w. this data register is a ?windo w? through which data is read or written to from the register pointed to by the serial ata index (sindx) register above. note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. since this is not a physical register, the ?default? value is the same as the default value of the register pointed to by sindx.ridx field. bit description 31:12 reserved 11:8 interface power management (ipm) ? ro . indicates the current interface state: all other values reserved. 7:4 current interface speed (spd) ? ro. indicates the negotiated interface communication speed. all other values reserved the pch supports generation 1 communication rates (1.5 gb/s), gen 2 rates (3.0 gb/s) and gen 3 rates (6.0gb/s) 3:0 device detection (det) ? ro . indicates the interface de vice detection and phy state: all other values reserved. value description 0h device not present or communication not established 1h interface in active state 2h interface in partial power management state 6h interface in slumber power management state value description 0h device not present or communication not established 1h generation 1 communication rate negotiated 2h generation 2 communication rate negotiated 3h generation 3 communication rate negotiated value description 0h no device de tected and phy communication not established 1h device presence detected but phy communication not established 3h device presence detected and phy communication established 4h phy in offline mode as a result of the interface being disabled or running in a bist loopback mode
sata controller registers (d31:f2) 586 datasheet 14.3.2.2 pxsctlserial ata control register (d31:f2) address offset: attribute: r/w, ro default value: 00000000h size: 32 bits sdata when sindx.ridx is 01h. this is a 32-bit read-write register by which software controls sata capabilities. writes to the sc ontrol register result in an action being taken by the pch or the interface. reads from the register return the last value written to it. bit description 31:20 reserved 19:16 port multiplier port (pmp) ? r/w. this field is not used by ahci. 15:12 select power management (spm) ? r/w. this field is not used by ahci. 11:8 interface power management transitions allowed (ipm) ? r/w . indicates which power states the pch is allowed to transition to: all other values reserved 7:4 speed allowed (spd) ? r/w. indicates the highest al lowable speed of the interface. this speed is limited by the ca p.iss (abar+00h:bit 23:20) field. all other values reserved. the pch supports generation 1 communication rates (1.5 gb/s), gen 2 rates (3.0 gb/s) and gen 3 rates (6.0gb/s) 3:0 device detection initialization (det) ? r/w. controls the pc h?s device detection and interface initialization. all other values reserved. when this field is written to a 1h, the pch initiates comreset and starts the initialization process. when the initialization is complete, this field shall remain 1h until set to another value by software. this field may only be change d to 1h or 4h when pxcmd.st is 0. changing this field while the pch is running results in undefined behavior. value description 0h no interface restrictions 1h transitions to the partial state disabled 2h transitions to the slumber state disabled 3h transitions to both partial and slumber states disabled value description 0h no speed negotiation restrictions 1h limit speed negotiation to generation 1 communication rate 2h limit speed negotiation to generation 2 communication rate 3h limit speed negotiation to generation 3 communication rate value description 0h no device detection or initialization action requested 1h perform interface communication initialization sequence to establish communication. this is functionally equivalent to a hard reset and results in the interface bein g reset and communications re- initialized 4h disable the serial ata interface and put phy in offline mode
datasheet 587 sata controller registers (d31:f2) 14.3.2.3 pxserrserial ata error register (d31:f2) address offset: attribute: r/wc default value: 00000000h size: 32 bits sdata when sindx.ridx is 02h. bits 26:16 of this register contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. bits 11:0 contain error information used by host software in determining the appropriate response to the error condition. if one or more of bits 11:8 of this register are set, the controller will stop the current transfer. bit description 31:27 reserved 26 exchanged (x) . when set to one, this bit indicate s that a change in device presence has been detected since the last time this bit was cleared. this bit sh all always be set to 1 anytime a cominit signal is received. th is bit is reflected in the p0is.pcs bit. 25 unrecognized fis type (f) . indicates that one or more fiss were received by the transport layer with good crc, but had a type field that was not recognized. 24 transport state transition error (t) . indicates that an e rror has occurred in the transition from one state to another within the transport layer since the last time this bit was cleared. 23 link sequence error (s) . indicates that one or more link state machine error conditions was encountered. the link layer state machine defines the conditions under which the link layer detect s an erroneous transition. 22 handshake (h) . indicates that one or more r_err handshake response was received in response to frame transmission. such errors may be the result of a crc error detected by the recipient, a di sparity or 8b/10b decoding er ror, or other error condition leading to a negative handshake on a transmitted frame. 21 crc error (c) . indicates that one or more crc e rrors occurred with the link layer. 20 disparity error (d) . this field is not used by ahci. 19 10b to 8b decode error (b) . indicates that one or more 10b to 8b decoding errors occurred. 18 comm wake (w) . indicates that a comm wake si gnal was detected by the phy. 17 phy internal error (i) . indicates that the phy dete cted some internal error. 16 phyrdy change (n) . when set to 1, this bit indicates that the internal phyrdy signal changed state since the last time this bit was cleared. in the pch, this bit will be set when phyrdy changes from a 0 -> 1 or a 1 -> 0. the state of this bit is then reflected in the pxis.prcs interrupt status bit and an interrupt will be ge nerated if enabled. software clears this bi t by writing a 1 to it. 15:12 reserved 11 internal error (e) . the sata controller failed due to a master or target abort when attempting to access system memory. 10 protocol error (p) . a violation of the serial ata protocol was detected. note: the pch does not set this bit for all protocol violations that may occur on the sata link. 9 persistent communication or data integrity error (c) . a communication error that was not recovered occurred that is expected to be pers istent. persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes.
sata controller registers (d31:f2) 588 datasheet 14.4 ahci registers (d31:f2) note: these registers are ahci-specific and availa ble when the pch is properly configured. the serial ata status, control, and error re gisters are special exceptions and may be accessed on all pch components if properly configured; see section 14.3 for details. the memory mapped registers within the sata controller exist in non-cacheable memory space. additionally, locked accesses ar e not supported. if software attempts to perform locked transactions to the registers, indeterminate results may occur. register accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte alignment boundary. all memory registers are reset by function level reset unless specified otherwise. the registers are broken into two sections ? generic host control and port control. the port control registers are the same for all ports, and there are as many registers banks as there are ports. 8 transient data integrity error (t) : a data integrity error occurred that was not recovered by the interface. 7:2 reserved 1 recovered communications error (m) . communications betw een the device and host was temporarily lost but was re-established. this can arise from a device temporarily being removed, from a temporar y loss of phy synchronization, or from other causes and may be derived from the phynrdy signal between the phy and link layers. 0 recovered data integrity error (i) . a data integrity e rror occurred that was recovered by the interface through a retr y operation or other recovery action. bit description table 14-3. ahci register address map abar + offset mnemonic register 00?1fh ghc generic host control 20h?ffh ? reserved 100h?17fh p0pcr port 0 port control registers 180h?1ffh p1pcr port 1 port control registers 200h?27fh p2pcr port 2 port control registers note: registers may be reserved depending on if port is available in the given sku. see section 1.3 for details if port is available. 280h?2ffh p3pcr port 3 port control registers note: registers may be reserved depending on if port is available in the given sku. see section 1.3 for details if port is available. 300h?37fh p4pcr port 4 port control registers 380h?3ffh p5pcr port 5 port control registers
datasheet 589 sata controller registers (d31:f2) 14.4.1 ahci generic host co ntrol registers (d31:f2) table 14-4. generic host cont roller register address map abar + offset mnemonic register default attribute 00h?03h cap host capabilities ff22ffc2h (desktop) de127f03h (mobile) r/wo, ro 04h?07h ghc global pch control 00000000h r/w, ro 08h?0bh is interrupt status 00000000h r/wc 0ch?0fh pi ports implemented 00000000h r/wo, ro 10h?13h vs ahci version 00010300h ro 1ch?1fh em_loc enclosure management location 01600002h ro 20h?23h em_ctrl enclosure management control 07010000h r/w, r/wo, ro 24h?27h cap2 hba capabilities extended 00000004h ro a0h?a3h vsp vendor specific 00000001h ro, r/wo c8h?c9h rstf intel ? rst feature capabilities 003fh r/wo
sata controller registers (d31:f2) 590 datasheet 14.4.1.1 caphost capab ilities register (d31:f2) address offset: abar + 00h?03h attribute: r/wo, ro default value: ff22ffc2h (desktop) size: 32 bits de127f03h (mobile) function level reset: no all bits in this register that ar e r/wo are reset only by pltrst#. bit description 31 supports 64-bit addressing (s64a) ? ro. in dicates that the sata controller can access 64-bit data structures. the 32-bit u pper bits of the port dma descriptor, the prd base, and each prd entry are read/write. 30 supports command queue acceleration (scqa) ? r/wo. when set to 1, indicates that the sata controller suppo rts sata command queuing using the dma setup fis. the pch handles dma setup fises natively, and can handle auto- activate optimizatio n through that fis. 29 supports snotification register (ssntf) ? ro. the pch sata controller does not support the snotification register. 28 supports mechanical presence switch (smps) ? r/wo. when set to 1, indicates whether the sata controller supports mechanical presence switches on its ports for use in hot plug operations. this value is loaded by platform bios prior to os initialization. if this bit is set, bios must also map the satagp pins to the sata controller through gpio space. 27 supports staggered spin-up (sss) ? r/wo. indicates whether the sata controller supports staggered spin-up on its ports, for use in balancing power spikes. this value is loaded by plat form bios prior to os initialization. 0 = staggered spin-up not supported. 1 = staggered spin-up supported. 26 supports aggressive link power management (salp) ? r/wo. 0 = software shall treat the pxcmd.alpe and pxcmd.asp bits as reserved. 1 = the sata controller supports auto-gener ating link requests to the partial or slumber states when there are no commands to process. 25 supports activity led (sal) ? ro. indicates that the sata controller supports a single output pin (sataled#) which indicates activity. 24 supports command list override (sclo) ? r/wo. when set to 1, indicates that the controller supports the pxcmd.cl o bit and its associated function. when cleared to 0, the controller is not capabl e of clearing the bsy and drq bits in the status register in order to issue a software reset if th ese bits are still set from a previous operation. 23:20 interface speed support (iss) ? r/wo. indicates the maximum speed the sata controller can support on its ports. 1h = 1.5 gb/s; 2h =3 gb/s; 3h = 6 gb/s the default of this field is dependent upon the pch sku. if at least one pch sata port supports 6 gb/s, the default will be 3h. if no pch sata ports support 6 gb/s, then the default will be 2h and writes of 3h will be ignored by the pch. see section 1.3 for details on 6 gb/s port availability. 19 supports non-zero dma offsets (snzo) ? ro . reserved, as per the ahci revision 1.3 specification
datasheet 591 sata controller registers (d31:f2) 18 supports ahci mode only (sam) ? ro. the sata controller may optionally support ahci access mechanism only. 0 = sata controller supports both ide and ahci modes 1 = sata controller supports ahci mode only 17 supports port multiplier (pms) ? r/wo. the pch sata controller does not support port multipliers. bios must clea r this bit by writing a 0 to this field. 16 reserved 15 pio multiple drq block (pmd) ? ro. hardwired to 1. the sata controller supports pio multiple drq command block 14 slumber state capable (ssc) ? r/wo. when set to 1, the sata controller supports the slumber state. 13 partial state capable (psc) ? r/wo. when set to 1, the sata controller supports the partial state. 12:8 number of command slots (ncs) ? ro. hardwired to 1fh to indicate support for 32 slots. 7 command completion coales cing supported (cccs) ? r/wo. 0 = command completion coalescing not supported 1 = command completion coalescing supported 6 enclosure management supported (ems) ? r/wo. 0 = enclosure management not supported 1 = enclosure management supported 5 supports external sata (sxs) ? r/wo. 0 = external sata is not supported on any ports 1 = external sata is support ed on one or more ports when set, sw can examine each sata port?s command register (pxcmd) to determine which port is routed externally. 4:0 number of ports (nps) ? ro. indicates number of su pported ports. note that the number of ports indicated in this field may be more than the number of ports indicated in the pi (abar + 0ch) register. field value dependent on number of ports available in a given sku. see section 1.3 for details. bit description
sata controller registers (d31:f2) 592 datasheet 14.4.1.2 ghcglobal pch control register (d31:f2) address offset: abar + 04h?07h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 31 ahci enable (ae) ? r/w. when set, this bit indicate s that an ahci driver is loaded and the controller will be talked to using ahci mechanisms. this can be used by an pch that supports both legacy mechanisms (such as sff-8038i) and ahci to know when the controller will not be talked to as legacy. 0 = software will communicate with the pch using legacy mechanisms. 1 = software will communicate with the pch using ahci. the pch will not have to allow command processing using both ahci and legacy mechanisms. software shall set this bit to 1 be fore accessing other ahci registers. 30:3 reserved 2 msi revert to single message (mrsm) ? ro: when set to 1 by hardware, this bit indicates that the host controller requested more than one msi vector but has reverted to using the first vector only. when this bi t is cleared to 0, the controller has not reverted to single msi mode (that is, hardwa re is already in single msi mode, software has allocated the number of messages requ ested, or hardware is sharing interrupt vectors if mc.mme < mc.mmc). "mc.msie = 1 (msi is enabled) "mc.mmc > 0 (multiple messages requested) "mc.mme > 0 (more than one message allocated) "mc.mme!= mc.mmc (messages allocated not equal to number requested) when this bit is set to 1, single msi mo de operation is in use and software is responsible for clearing bits in th e is register to clear interrupts. this bit shall be cleared to 0 by hardware when any of the four conditions stated is false. this bit is also cleared to 0 when mc.msie = 1 and mc.mme = 0h. in this case, the hardware has been programmed to use single msi mode, and is not ?reverting? to that mode. for pch, the controller shall always revert to single msi mode when the number of vectors allocated by the host is less than the number requested. this bit is ignored when ghc.hr = 1. 1 interrupt enable (ie) ? r/w. this global bit enab les interrupts from the pch. 0 = all interrupt sources from all ports are disabled. 1 = interrupts are allowed from the ahci controller. 0 controller reset (hr) ? r/w. resets the pch ahci controller. 0 = no effect 1 = when set by software, this bit causes an internal reset of the pch ahci controller. all state machines that relate to data transfers and queuing return to an idle condition, and all ports are re-initialized using comreset. note: for further details, consult section 10. 4.3 of the serial ata advanced host controller interface specification revision 1.3.
datasheet 593 sata controller registers (d31:f2) 14.4.1.3 isinterrupt status register (d31:f2) address offset: abar + 08h ? 0bh attribute: r/wc default value: 00000000h size: 32 bits this register indicates which of the ports within the controller have an interrupt pending and require service. bit description 31:6 reserved. returns 0. 5 interrupt pending status port[5] (ips[5]) ? r/wc. 0 = no interrupt pending. 1 = port 5 has an interrupt pending. softwa re can use this information to determine which ports require serv ice after an interrupt. 4 interrupt pending status port[4] (ips[4]) ? r/wc. 0 = no interrupt pending. 1 = port 4 has an interrupt pending. softwa re can use this information to determine which ports require serv ice after an interrupt. 3 interrupt pending status port[3] (ips[3]) ? r/wc. 0 = no interrupt pending. 1 = port 3 has an interrupt pending. softwa re can use this information to determine which ports require serv ice after an interrupt. note: bit may be reserved depending on if po rt is available in the given sku. see section 1.3 for details if port is available. 2 interrupt pending status port[2] (ips[2]) ? r/wc. 0 = no interrupt pending. 1 = port 2 has an interrupt pending. softwa re can use this information to determine which ports require serv ice after an interrupt. note: bit may be reserved depending on if po rt is available in the given sku. see section 1.3 for details if port is available. 1 interrupt pending status port[1] (ips[1]) ? r/wc. 0 = no interrupt pending. 1 = port 1has an interrupt pe nding. software can use this information to determine which ports require serv ice after an interrupt. 0 interrupt pending status port[0] (ips[0]) ? r/wc. 0 = no interrupt pending. 1 = port 0 has an interrupt pending. softwa re can use this information to determine which ports require serv ice after an interrupt.
sata controller registers (d31:f2) 594 datasheet 14.4.1.4 piports implemented register (d31:f2) address offset: abar + 0ch?0fh attribute: r/wo, ro default value: 00000000h size: 32 bits function level reset: no this register indicates which ports are exposed to the pch. it is loaded by platform bios. it indicates which ports that the device supports are available for software to use. for ports that are not available, software must not read or write to registers within that port. after bios issues initial write to this register, bios is requested to issue two reads to this register. if bios accesses an y of the port specific ahci address range before setting pi bit, bios is required to read the pi register before the initial write to the pi register. bit description 31:6 reserved. returns 0. 5 ports implemented port 5 (pi5) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. this bit is read-only 0 if map.sc = 0 or scc = 01h. 4 ports implemented port 4 (pi4) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. this bit is read-only 0 if map.sc = 0 or scc = 01h. 3 ports implemented port 3 (pi3) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. note: bit may be reserved and ro ?0? depending on if port is available in the given sku. see section 1.3 for details if port is available. 2 ports implemented port 2 (pi2) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. note: bit may be reserved and ro ?0? depending on if port is available in the given sku. see section 1.3 for details if port is available. 1 ports implemented port 1 (pi1) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. 0 ports implemented port 0 (pi0) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented.
datasheet 595 sata controller registers (d31:f2) 14.4.1.5 vsahci version register (d31:f2) address offset: abar + 10h?13h attribute: ro default value: 00010300h size: 32 bits this register indicates the major and minor version of the ahci specification. it is bcd encoded. the upper two bytes represent th e major version number, and the lower two bytes represent the minor version number. example: version 3.12 would be represented as 00030102h. the current ve rsion of the specification is 1.30 (00010300h). 14.4.1.6 em_locenclosure management location register (d31:f2) address offset: abar + 1ch?1fh attribute: ro default value: 01600002h size: 32 bits this register identifies the location and size of the enclosure management message buffer. this register is reserved if enclosure management is not supported (that is, cap.ems = 0). bit description 31:16 major version number (mjr) ? ro. indicates the major version is 1 15:0 minor version number (mnr) ? ro. indicates the minor version is 30. bit description 31:16 offset (ofst) ? ro. the offset of the message buffer in dwords from the beginning of the abar. 15:0 buffer size (sz) ? ro. specifies the size of the transmit message buffer area in dwords. the pch sata controller only supports transmit buffer. a value of 0 is invalid.
sata controller registers (d31:f2) 596 datasheet 14.4.1.7 em_ctrlenclosure management control register (d31:f2) address offset: abar + 20h?23h attribute: r/w, r/wo, ro default value: 07010000h size: 32 bits this register is used to control and obtain status for the enclosure management interface. this register includes informatio n on the attributes of the implementation, enclosure management messages supported, the status of the interface, whether any message are pending, and is used to initiate sending messages. this register is reserved if enclosure management is not supported (cap_ems = 0). bit description 31:27 reserved 26 activity led hardware driven (attr.alhd) ? r/wo. 1 = the sata controller drives the activity led for the led message type in hardware and does not utilize software for this led. the host controller does not begin transmitti ng the hardware based activity signal until after software has written ctl. tm=1 after a reset condition. 25 transmit only (attr.xmt) ? ro. 0 = the sata controller supports tr ansmitting and re ceiving messages. 1 = the sata controller only supports transmitting messages and does not support receiving messages. 24 single message buffer (attr.smb) ? ro. 0 = there are separate receiv e and transmit buffers such that unsolicited messages could be supported. 1 = the sata controller has one message bu ffer that is shared for messages to transmit and messages received. unsolici ted receive messages are not supported and it is software?s responsibility to manage access to this buffer. 23:20 reserved 19 sgpio enclosure management messages (supp.sgpio) ? ro. 1 = the sata controller supports the sg pio register interface message type. 18 ses-2 enclosure management messages (supp.ses2) ? ro. 1 = the sata controller suppo rts the ses-2 message type. 17 saf-te enclosure management messages (supp.safte) ? ro. 1 = the sata controller suppo rts the saf-te message type. 16 led message types (supp.led) ? ro. 1 = the sata controller su pports the led message type. 15:10 reserved 9 reset (rst): ? r/w. 0 = a write of 0 to this bit by software will have no effect. 1 = when set by software, the sata controller resets all enclosure management message logic and takes all appropriate re set actions to ensure messages can be transmitted / received after the reset. after the sata contro ller completes the reset operation, the sata cont roller sets the value to 0. 8 transmit message (ctl.tm) ? r/w. 0 = a write of 0 to this bit by software will have no effect. 1 = when set by software, the sata controller transmits the message contained in the message buffer. when the me ssage is completely sent, the sata controller sets the value to 0. software must not chan ge the contents of the message buffer while ctl.tm is set to 1. 7:1 reserved 0 message received (sts.mr): ? ro. message received is not supported in the pch.
datasheet 597 sata controller registers (d31:f2) 14.4.1.8 cap2hba capabilities extended register address offset: abar + 24h?27h attribute: ro default value: 00000004h size: 32 bits function level reset: no 14.4.1.9 vspvendor spec ific register (d31:f2) address offset: abar + a0h?a3h attribute: ro, r/wo default value: 00000001h size: 32 bits bit description 31:3 reserved 2 automatic partial to slumber transitions (apst) 0= not supported 1= supported 1:0 reserved bit description 31:1 reserved 0 sata initalization field ? r/wo bios must clear this bit by writing a 0 to this field.
sata controller registers (d31:f2) 598 datasheet 14.4.1.10 rstf intel ? rst feature capabilities register address offset: abar + c8h?c9h attribute: r/wo default value: 003fh size: 16 bits function level reset: no no hardware action is taken on this regist er. this register is needed for the intel? rapid storage technology software. these bits are set by bios to request the feature from the appropriate intel rapid storage technology software. bit description 15:12 reserved 11:10 orom ui normal delay (oud) ? r/wo. the values of these bits specify the delay of the orom ui splash scre en in a normal status. 00 = 2 seconds (default) 01 = 4 seconds 10 = 6 seconds 11 = 8 seconds if bit 5 = 0b these valu es will be disregarded. 9 intel ? smart response technology enable request (sereq) r/wo. indicates the requested status of the intel smart response technology support. 0 = disabled 1 = enabled 8 intel ? rrt only on esata (roes) r/wo indicates the request that only intel ? rapid recovery technology (rrt) volumes can can span internal and external sata (esata). if not set, any raid volume can span internal and external sata. 0 = disabled 1 = enabled 7 led locate (ledl) r/wo indicates the request that the led/sgpio hardware is attached and ping to locate feature is enabled in the os. 0 = disabled 1 = enabled 6 hdd unlock (hddlk) ? r/wo indicates the requested status of hdd password unlock in the os. 0 = disabled 1 = enabled 5 intel rst orom ui (rstoromui) ? r/wo. indicates the requested status of the intel ? rst orom ui display. 0 = the intel rst orom ui and banner are no t displayed if all disks and raid volumes have a normal status. 1 = the intel rst orom ui is displayed during each boot. 4 intel ? rrt enable (rste) r/wo indicates the requested status of the intel ? rapid recovery technology support. 0 = disabled 1 = enabled 3 raid 5 enable (r5e) r/wo indicates the requested st atus of raid 5 support. 0 = disabled 1 = enabled
datasheet 599 sata controller registers (d31:f2) 14.4.2 port registers (d31:f2) ports not available will result in the corresponding port dma register space being reserved. the controller shall ignore writes to the reserved space on write cycles and shall return 0 on read cycle accesses to the reserved location. 2 raid 10 enable (r10e) r/wo indicates the requested stat us of raid 10 support. 0 = disabled 1 = enabled 1 raid 1 enable (r1e) r/wo indicates the requested st atus of raid 1 support. 0 = disabled 1 = enabled 0 raid 0 enable (r0e) r/wo indicates the requested st atus of raid 0 support. 0 = disabled 1 = enabled bit description table 14-5. port [5:0] dma register address map (sheet 1 of 3) abar + offset mnemonic register 100h?103h p0clb port 0 command list base address 104h?107h p0clbu port 0 command li st base address upper 32-bits 108h?10bh p0fb port 0 fis base address 10ch?10fh p0fbu port 0 fis base address upper 32-bits 110h?113h p0is port 0 interrupt status 114h?117h p0ie port 0 interrupt enable 118h?11bh p0cmd port 0 command 11ch?11fh ? reserved 120h?123h p0tfd port 0 task file data 124h?127h p0sig port 0 signature 128h?12bh p0ssts port 0 serial ata status 12ch?12fh p0sctl port 0 serial ata control 130h?133h p0serr port 0 serial ata error 134h?137h p0sact port 0 serial ata active 138h?13bh p0ci port 0 command issue 13ch?17fh ? reserved 180h?183h p1clb port 1 command list base address 184h?187h p1clbu port 1 command li st base address upper 32-bits 188h?18bh p1fb port 1 fis base address 18ch?18fh p1fbu port 1 fis base address upper 32-bits 190h?193h p1is port 1 interrupt status 194h?197h p1ie port 1 interrupt enable
sata controller registers (d31:f2) 600 datasheet 198h?19bh p1cmd port 1 command 19ch?19fh ? reserved 1a0h?1a3h p1tfd port 1 task file data 1a4h?1a7h p1sig por t 1 signature 1a8h?1abh p1ssts port 1 serial ata status 1ach?1afh p1sctl port 1 serial ata control 1b0h?1b3h p1serr port 1 serial ata error 1b4h?1b7h p1sact port 1 serial ata active 1b8h?1bbh p1ci port 1 command issue 1bch?1ffh ? reserved 200h?27fh ? registers may be reserved dependin g on if port is available in the given sku. see section 1.3 for details if port is available. 200h?203h p2clb port 2 command list base address 204h?207h p2clbu port 2 command list base address upper 32-bits 208h?20bh p2fb port 2 fis base address 20ch?20fh p2fbu port 2 fis ba se address upper 32-bits 210h?213h p2is port 2 interrupt status 214h?217h p2ie port 2 interrupt enable 218h?21bh p2cmd port 2 command 21ch?21fh ? reserved 220h?223h p2tfd port 2 task file data 224h?227h p2sig port 2 signature 228h?22bh p2ssts port 2 serial ata status 22ch?22fh p2sctl port 2 serial ata control 230h?233h p2serr port 2 serial ata error 234h?237h p2sact port 2 serial ata active 238h?23bh p2ci port 2 command issue 23ch?27fh ? reserved 280h?2ffh ? registers may be reserved dependin g on if port is available in the given sku. see section 1.3 for details if port is available. 280h?283h p3clb port 3 command list base address 284h?287h p3clbu port 3 command list base address upper 32-bits 288h?28bh p3fb port 3 fis base address 28ch?28fh p3fbu port 3 fis ba se address upper 32-bits 290h?293h p3is port 3 interrupt status 294h?297h p3ie port 3 interrupt enable 298h?29bh p3cmd port 3 command 29ch?29fh ? reserved 2a0h?2a3h p3tfd port 3 task file data 2a4h?2a7h p3sig por t 3 signature table 14-5. port [5:0] dma register address map (sheet 2 of 3) abar + offset mnemonic register
datasheet 601 sata controller registers (d31:f2) 2a8h?2abh p3ssts port 3 serial ata status 2ach?2afh p3sctl port 3 serial ata control 2b0h?2b3h p3serr port 3 serial ata error 2b4h?2b7h p3sact port 3 serial ata active 2b8h?2bbh p3ci port 3 command issue 2bch?2ffh ? reserved 300h?303h p4clb port 4 command list base address 304h?307h p4clbu port 4 command li st base address upper 32-bits 308h?30bh p4fb port 4 fis base address 30ch?30fh p4fbu port 4 fis base address upper 32-bits 310h?313h p4is port 4 interrupt status 314h?317h p4ie port 4 interrupt enable 318h?31bh p4cmd port 4 command 31ch?31fh ? reserved 320h?323h p4tfd port 4 task file data 324h?327h p4sig port 4 signature 328h?32bh p4ssts port 4 serial ata status 32ch?32fh p4sctl port 4 serial ata control 330h?333h p4serr port 4 serial ata error 334h?337h p4sact port 4 serial ata active 338h?33bh p4ci port 4 command issue 33ch?37fh ? reserved 380h?383h p5clb port 5 command list base address 384h?387h p5clbu port 5 command li st base address upper 32-bits 388h?38bh p5fb port 5 fis base address 38ch?38fh p5fbu port 5 fis base address upper 32-bits 390h?393h p5is port 5 interrupt status 394h?397h p5ie port 5 interrupt enable 398h?39bh p5cmd port 5 command 39ch?39fh ? reserved 3a0h?3a3h p5tfd port 5 task file data 3a4h?3a7h p5sig port 5 signature 3a8h?3abh p5ssts port 5 serial ata status 3ach?3afh p5sctl port 5 serial ata control 3b0h?3b3h p5serr port 5 serial ata error 3b4h?3b7h p5sact port 5 serial ata active 3b8h?3bbh p5ci port 5 command issue 3bch?fffh ? reserved table 14-5. port [5:0] dma register address map (sheet 3 of 3) abar + offset mnemonic register
sata controller registers (d31:f2) 602 datasheet 14.4.2.1 pxclbport [5:0] command list base address register (d31:f2) address offset: port 0: abar + 100h attribute: r/w port 1: abar + 180h port 2: abar + 200h (if port available; see section 1.3 ) port 3: abar + 280h (if port available; see section 1.3 ) port 4: abar + 300h port 5: abar + 380h default value: undefined size: 32 bits 14.4.2.2 pxclbuport [5:0] comm and list base address upper 32-bits register (d31:f2) address offset: port 0: abar + 104h attribute: r/w port 1: abar + 184h port 2: abar + 204h (if port available; see section 1.3 ) port 3: abar + 284h (if port available; see section 1.3 ) port 4: abar + 304h port 5: abar + 384h default value: undefined size: 32 bits 14.4.2.3 pxfbport [5:0] fis ba se address register (d31:f2) address offset: port 0: abar + 108h attribute: r/w port 1: abar + 188h port 2: abar + 208h (if port available; see section 1.3 ) port 3: abar + 288h (if port available; see section 1.3 ) port 4: abar + 308h port 5: abar + 388h default value: undefined size: 32 bits bit description 31:10 command list base address (clb) ? r/w. indicates the 32-bit base for the command list for this port. this base is used when fetching commands to execute. the structure pointed to by this address range is 1 kb in length. this address must be 1-kb aligned as indicated by bi ts 31:10 being read/write. note that these bits are not reset on a controller reset. 9:0 reserved bit description 31:0 command list base address upper (clbu) ? r/w. indicates the upper 32-bits for the command list base address for this po rt. this base is us ed when fetching commands to execute. note that these bits are not reset on a controller reset. bit description 31:8 fis base address (fb) ? r/w. indicates the 32-bit base for received fises. the structure pointed to by this address range is 256 bytes in length. this address must be 256-byte aligned, as indicated by bits 31:3 being read/write. note that these bits are not reset on a controller reset. 7:0 reserved
datasheet 603 sata controller registers (d31:f2) 14.4.2.4 pxfbuport [5:0] fis base address upper 32-bits register (d31:f2) address offset: port 0: abar + 10ch attribute: r/w port 1: abar + 18ch port 2: abar + 20ch (if port available; see section 1.3 ) port 3: abar + 28ch (if port available; see section 1.3 ) port 4: abar + 30ch port 5: abar + 38ch default value: undefined size: 32 bits 14.4.2.5 pxisport [5:0] interru pt status register (d31:f2) address offset: port 0: abar + 110h attribute: r/wc, ro port 1: abar + 190h port 2: abar + 210h (if port available; see section 1.3 ) port 3: abar + 290h (if port available; see section 1.3 ) port 4: abar + 310h port 5: abar + 390h default value: 00000000h size: 32 bits bit description 31:0 fis base address upper (fbu) ? r/w. indicates the upper 32-bi ts for the received fis base for this port. note that these bits are not reset on a controller reset. bit description 31 cold port detect status (cpds) ? ro. cold presence detect is not supported. 30 task file error status (tfes) ? r/wc. this bit is set whenever the status register is updated by the device and the er ror bit (pxtfd.bit 0) is set. 29 host bus fatal error status (hbfs) ? r/wc. indicates that the pch encountered an error that it cannot recover from due to a bad software pointer. in pci, such an indication would be a target or master abort. 28 host bus data error status (hbds) ? r/wc. indicates that the pch encountered a data error (uncorrectable ecc / parity) when reading from or writing to system memory. 27 interface fatal error status (ifs) ? r/wc. indicates that the pch encountered an error on the sata interface whic h caused the transfer to stop. 26 interface non-fatal error status (infs) ? r/wc. indicates that the pch encountered an error on the sata interfa ce but was able to continue operation. 25 reserved 24 overflow status (ofs) ? r/wc. indicates that the pch re ceived more bytes from a device than was specified in the prd table for the command. 23 incorrect port multiplier status (ipms) ? r/wc. indicates that the pch received a fis from a device whose port multiplier field did not match what was expected. note: fis based port multipliers ar e not supported by the pch.
sata controller registers (d31:f2) 604 datasheet 22 phyrdy change status (prcs) ? ro. when set to one, this bit indicates the internal phyrdy signal changed state. this bit reflects the state of pxserr.diag.n. unlike most of the other bits in the regist er, this bit is ro and is only cleared when pxserr.diag.n is cleared. note that the internal phyrdy signal also transitions when the port interface enters partial or slumber power management states . partial and slumber must be disabled when surprise removal notifi cation is desired, otherwis e the power management state transitions will appear as fals e insertion and removal events. 21:8 reserved 7 device interlock status (dis) ? r/wc. when set, this bit indicates that a platform mechanical presence switch has been opened or closed, which may lead to a change in the connection state of the device. this bit is only valid in systems that support an mechanical presence switch (cap.sis [abar+00:bit 28] set). for systems that do not support an mechanical presence switch, this bit will always be 0. 6 port connect change status (pcs) ? ro . this bit reflects the state of pxserr.diag.x. (abar+130h/1d0h/230h/2d0h, bit 26) unlike other bits in this register, this bit is only cleare d when pxserr.diag.x is cleared. 0 = no change in curre nt connect status. 1 = change in current connect status. 5 descriptor pr ocessed (dps) ? r/wc. a prd with the i bit set has transferred all its data. 4 unknown fis interrupt (ufs) ? ro. when set to 1, this bit indicates that an unknown fis was received and has been copied into system memory. this bit is cleared to 0 by software clearing the pxserr.diag.f bit to 0. note that this bit does not directly reflect the pxserr.diag.f bit. pxserr.diag.f is set immediately when an unknown fis is detected, whereas this bit is set when th e fis is posted to me mory. software should wait to act on an unknown fis until this bit is set to 1 or the two bits may become out of sync. 3 set device bits interrupt (sdbs) ? r/wc. a set device bits fis has been received with the i bit set and has been copied into system memory. 2 dma setup fis interrupt (dss) ? r/wc. a dma setup fis has been received with the i bit set and has been co pied into system memory. 1 pio setup fis interrupt (pss) ? r/wc. a pio setup fis has been received with the i bit set, it has been copied into system memory, and the data related to that fis has been transferred. 0 device to host register fis interrupt (dhrs) ? r/wc. a d2h register fis has been received with the i bit set, and has been copied into system memory. bit description
datasheet 605 sata controller registers (d31:f2) 14.4.2.6 pxieport [5:0] interru pt enable register (d31:f2) address offset: port 0: abar + 114h attribute: r/w, ro port 1: abar + 194h port 2: abar + 214h (if port available; see section 1.3 ) port 3: abar + 294h (if port available; see section 1.3 ) port 4: abar + 314h port 5: abar + 394h default value: 00000000h size: 32 bits this register enables and disables the re porting of the corresponding interrupt to system software. when a bit is set (1) an d the corresponding interrupt condition is active, then an interrupt is generated. inte rrupt sources that are disabled (0) are still reflected in the status registers. bit description 31 cold presence detect enable (cpde) ? ro. cold presence detect is not supported. 30 task file error enable (tfee) ? r/w. when set, and ghc.ie and pxtfd.sts.err (due to a reception of the e rror register from a received fis) are set, the pch will generate an interrupt. 29 host bus fatal error enable (hbfe) ? r/w. when set, and ghc.ie and pxs.hbfs are set, the pch will generate an interrupt. 28 host bus data error enable (hbde) ? r/w. when set, and ghc.ie and pxs.hbds are set, the pch will generate an interrupt. 27 host bus data error enable (hbde) ? r/w. when set, ghc.ie is set, and pxis.hbds is set, the pch wi ll generate an interrupt. 26 interface non-fatal error enable (infe) ? r/w. when set, ghc.ie is set, and pxis.infs is set, the pch will generate an interrupt. 25 reserved 24 overflow error enable (ofe) ? r/w . when set, and ghc.ie and pxs.ofs are set, the pch will generate an interrupt. 23 incorrect port multiplier enable (ipme) ? r/w. when set, and ghc.ie and pxis.ipms are set, the pch wi ll generate an interrupt. note: fis based port multipliers only supported on sata ports 4 and 5 by pch 22 phyrdy change interrupt enable (prce) ? r/w. when set, and ghc.ie is set, and pxis.prcs is set, the pch shall generate an interrupt. 21:8 reserved 7 device interlock enable (die) ? r/w. when set, and pxis.dis is set, the pch will generate an interrupt. for systems that do not support an mechanical presence switch, this bit shall be a read- only 0. 6 port change interrupt enable (pce) ? r/w. when set, and ghc.ie and pxs.pcs are set, the pch will generate an interrupt. 5 descriptor processed interrupt enable (dpe) ? r/w. when set, and ghc.ie and pxs.dps are set, the pch will generate an interrupt. 4 unknown fis interrupt enable (ufie) ? r/w. when set, and ghc.ie is set and an unknown fis is received, the pch will generate this interrupt. 3 set device bits fis interrupt enable (sdbe) ? r/w. when set, and ghc.ie and pxs.sdbs are set, the pch wi ll generate an interrupt. 2 dma setup fis interrupt enable (dse) ? r/w. when set, and ghc.ie and pxs.dss are set, the pch will generate an interrupt. 1 pio setup fis interrupt enable (pse) ? r/w. when set, and ghc.ie and pxs.pss are s e t, the pch will generate an interrupt. 0 device to host register fis interrupt enable (dhre) ? r/w. when set, and ghc.ie and pxs.dhrs are set, the pch will generate an interrupt.
sata controller registers (d31:f2) 606 datasheet 14.4.2.7 pxcmdport [5:0] command register (d31:f2) address offset: port 0: abar + 118h attribute: r/w, ro, r/wo port 1: abar + 198h port 2: abar + 218h (if port available; see section 1.3 ) port 3: abar + 298h (if port available; see section 1.3 ) port 4: abar + 318h port 5: abar + 398h default value: 0000w00wh size: 32 bits where w = 00?0b (for?, see bit description) function level reset: no (bit 21, 19 and 18 only) bit description 31:28 interface communication control (icc) ? r/w.this is a four bit field that can be used to control reset and power states of th e interface. writes to this field will cause actions on the interface, either as primitiv es or an oob sequen ce, and the resulting status of the interface will be reported in the pxssts re gister (address offset port 0:abar+124h, port 1: abar+1a4h, port 2: abar+224h, port 3: abar+2a4h, port 4: abar+224h, port 5: abar+2a4h). when system software writes a non-reserv ed value other than no-op (0h), the pch will perform the action and update this field back to idle (0h). if software writes to this fi eld to change the state to a state the link is already in (such as, interface is in the active state and a request is made to go to the active state), the pch will take no action and return this field to idle. note: when the alpe bit (bit 26) is set, then this register should not be set to 02h or 06h. 27 aggressive slumber / partial (asp) ? r/w. when set to 1, and the alpe bit (bit 26) is set, the pch shall aggressively enter the slumber state when it clears the pxci register and the pxsact register is cleared. when cleared, and the alpe bit is set, the pch will aggressively enter th e partial state when it clears the pxci register and the pxsact register is cleared. if cap.salp is cleared to 0, software shall treat this bit as reserved. 26 aggressive link power ma nagement enable (alpe) ? r/w. when set to 1, the pch will aggressively enter a lower link power state (partial or slumber) based upon the setting of the asp bit (bit 27). value definition fh?7h reserved 6h slumber: this will cause the pch to request a transition of the interface to the slumbe r state. the sata de vice may reject the request and the interface will remain in its current state 5h?3h reserved 2h partial: this will cause the pch to request a transition of the interface to the partial state. the sata device may reject the request and the interface will remain in its current state. 1h active: this will cause the pch to request a transition of the interface into the active 0h no-op / idle: when software reads this value, it indicates the pch is not in the process of changing the interface state or sending a device reset, and a new link command may be issued.
datasheet 607 sata controller registers (d31:f2) 25 drive led on atapi enable (dlae) ? r/w . when set to 1, the pch will drive the led pin active for atapi commands (pxclb[chz.a] set) in addition to ata commands. when cleared, th e pch will only drive the led pin active for ata commands. see section 5.16.11 for details on the activity led. 24 device is atapi (atapi) ? r/w. when set to 1, the connected device is an atapi device. this bit is used by the pch to control whether or not to generate the desktop led when commands are active. see section 5.16.11 for details on the activity led. 23 automatic partial slumber transitions enabled (apste) ? r/w. 0 = this port will not perform automa tic partial to slumber transitions. 1 = the hba may perform automatic partial to slumber transitions. note: software should only set this bit to ?1? if cap2.apst is set to ?1?. 22 sata initalization field ? r/wo bios must write a 0 to this field. this field is not reset by flr. 21 external sata port (esp) ? r/wo. 0 = this port supports inte rnal sata devices only. 1 = this port will be used with an extern al sata device and hot plug is supported. when set, cap.sxs must also be set. this bit is not reset by function level reset. 20 reserved 19 mechanical switch attached to port (mpsp) ? r/wo. if set to 1, the pch supports a mechanical presence sw itch attached to this port. the pch takes no action on the state of this bit ? it is for syst em software only. for example, if this bit is clea red, and an mechanical pres ence switch toggles, the pch still treats it as a proper me chanical presence switch event. note: this bit is not reset on a controller reset or by a function level reset. 18 hot plug capable port (hpcp) ? r/wo. 0 = port is not capable of hot-plug. 1 = port is hot-plug capable. this indicates whether the pl atform exposes this port to a device which can be hot- plugged. sata by definition is hot-pluggable, but not all platforms are constructed to allow the device to be removed (it may be screwed into the ch assis, for example). this bit can be used by system software to indicate a feature such as ?eject device? to the end-user. the pch takes no action on the state of this bit ? it is for system software only. for example, if this bit is cleared, and a hot-plug event occurs, the pch still treats it as a proper hot-plug event. note: this bit is not reset on a controller reset or by a function level reset. 17:16 reserved 15 controller running (cr) ? ro. when this bit is set, the dma engines for a port are running. 14 fis receive running (fr) ? ro. when set, the fis receive dma engine for the port is running. 13 mechanical presence switch state (mpss) ? ro. the mpss bit reports the state of a mechanical presence switch attached to this port. if cap.smps is set to 1 and the mechanical presence switch is closed then th is bit is cleared to 0. if cap.smps is set to 1 and the mechanical presence switch is open then this bit is set to 1. if cap.smps is set to '0' then this bit is cleared to 0. software should only use this bit if both cap.smps and pxcmd.mpsp are set to 1. bi t d escription
sata controller registers (d31:f2) 608 datasheet 12:8 current command slot (ccs) ? ro. indicates the current command slot the pch is processing. this field is vali d when the st bit is set in th is register, and is constantly updated by the pch. this field can be u pdated as soon as th e pch recognizes an active command slot, or at some point soon after when it begins processing the command. this field is used by softwa re to determine the current command issue location of the pch. in queued mode, softwa re shall not use this field, as its value does not represent the current command being execut ed. software shall only use pxci and pxsact when running queued commands. 7:5 reserved 4 fis receive enable (fre) ? r/w. when set, the pch may post received fises into the fis receive area pointed to by pxfb (abar+108h/188h/208h/288h) and pxfbu (abar+10ch/18ch/20ch/28ch). when cleared, received fises are not accepted by the pch, except for th e first d2h (device-to-host) regi ster fis after the initialization sequence. system software must not set this bit until pxfb (pxfbu) have been programmed with a valid pointer to the fis receive area, and if software wishes to move the base, this bit must first be cleared, and software must wait for the fr bit (bit 14) in this register to be cleared. 3 command list override (clo) ? r/w. setting this bit to 1 causes pxtfd.sts.bsy and pxtfd.sts.drq to be cleared to 0. this allows a software reset to be transmitted to the device regardless of whether th e bsy and drq bits are still set in the pxtfd.sts register. the controller sets this bit to 0 when pxtfd.sts.bsy and pxtfd.sts.drq have been cleared to 0. a write to this register with a value of 0 shall have no effect. this bit shall only be set to 1 immediately prior to setting the pxcmd.st bit to 1 from a previous value of 0. setting this bit to 1 at any other time is not supported and will result in indeterminate behavior. software mu st wait for clo to be cleared to 0 before setting pxcmd.st to 1. 2 power on device (pod) ? ro. cold presence detect not supported. defaults to 1. 1 spin-up device (sud) ? r/w / ro this bit is r/w and defaults to 0 for sy stems that support st aggered spin-up (r/w when cap.sss (abar+00h:bit 27) is 1). bit is ro 1 for systems that do not support staggered spin-up (when cap.sss is 0). 0 = no action. 1 = on an edge detect from 0 to 1, th e pch starts a comr eset initialization sequence to the device. clearing this bit to 0 does not cause any oo b signal to be sent on the interface. when this bit is cleared to 0 an d pxsctl.det=0h, the controller will enter listen mode. 0 start (st) ? r/w . when set, the pch may process the command list. when cleared, the pch may not process the command list. whenever this bit is changed from a 0 to a 1, the pch starts processing the command list at entry 0. whenever this bit is changed from a 1 to a 0, the pxci register is cleared by the pch upon the pch putting the controller into an idle state. refer to section 10.3 of the serial ata ahci specification for import ant restrictions on when st can be set to 1 and cleared to 0. bit description
datasheet 609 sata controller registers (d31:f2) 14.4.2.8 pxtfdport [5:0] task file data register (d31:f2) address offset: port 0: abar + 120h attribute: ro port 1: abar + 1a0h port 2: abar + 220h (if port available; see section 1.3 ) port 3: abar + 2a0h (if port available; see section 1.3 ) port 4: abar + 320h port 5: abar + 3a0h default value: 0000007fh size: 32 bits this is a 32-bit register that copies specif ic fields of the task file when fises are received. the fises that contain this information are: d2h register fis,pio setup fis and set device bits fis 14.4.2.9 pxsigport [5:0] signature register (d31:f2) address offset: port 0: abar + 124h attribute: ro port 1: abar + 1a4h port 2: abar + 224h (if port available; see section 1.3 ) port 3: abar + 2a4h (if port available; see section 1.3 ) port 4: abar + 324h port 5: abar + 3a4h default value: ffffffffh size: 32 bits this is a 32-bit register which contains the initial signature of an attached device when the first d2h register fis is received from th at device. it is updated once after a reset sequence. bit description 31:16 reserved 15:8 error (err) ? ro . contains the latest copy of the task file error register. 7:0 status (sts) ? ro. contains the latest copy of the task file status register. fields of note in this register that affect ahci. bit field definition 7 bsy indicates the interface is busy 6:4 n/a not applicable 3 drq indicates a data transfer is requested 2:1 n/a not applicable 0 err indicates an error during the transfer bit description 31:0 signature (sig) ? ro . contains the signature received from a device on the first d2h register fis. the bit order is as follows: bit field 31:24 lba high register 23:16 lba mid register 15:8 lba low register 7:0 sector count register
sata controller registers (d31:f2) 610 datasheet 14.4.2.10 pxsstsport [5:0] serial ata status register (d31:f2) address offset: port 0: abar + 128h attribute: ro port 1: abar + 1a8h port 2: abar + 228h (if port available; see section 1.3 ) port 3: abar + 2a8h (if port available; see section 1.3 ) port 4: abar + 328h port 5: abar + 3a8h default value: 00000000h size: 32 bits this is a 32-bit register that conveys the current state of the interface and host. the pch updates it continuously and asynchronously. when the pch transmits a comreset to the device, this register is updated to its reset values. bit description 31:12 reserved 11:8 interface power management (ipm) ? ro. indicates the current interface state: all other values reserved. 7:4 current interface speed (spd) ? ro. indicates the negotiated interface communication speed. all other values reserved. the pch supports gen 1 communication rates (1.5 gb/s), gen 2 rates (3.0 gb/s) and gen 3 rates (6.0 gb/s) (supported speeds are determined by sku; see section 1.3 ) 3:0 device detection (det) ? ro. indicates the interface device detection and phy state: all other values reserved. value description 0h device not present or communication not established 1h interface in active state 2h interface in partial power management state 6h interface in slumber power management state value description 0h device not present or communication not established 1h generation 1 communication rate negotiated 2h generation 2 communication rate negotiated 3h generation 3 communication rate negotiated value description 0h no device de tected and phy communication not established 1h device presence detected but phy communication not established 3h device presence detected and phy communication established 4h phy in offline mode as a result of the interface being disabled or running in a bist loopback mode
datasheet 611 sata controller registers (d31:f2) 14.4.2.11 pxsctl port [5:0] serial ata control register (d31:f2) address offset: port 0: abar + 12ch attribute: r/w, ro port 1: abar + 1ach port 2: abar + 22ch (if port available; see section 1.3 ) port 3: abar + 2ach (if port available; see section 1.3 ) port 4: abar + 32ch port 5: abar + 3ach default value: 00000004h size: 32 bits this is a 32-bit read-write register by which software controls sata capabilities. writes to the scontrol register result in an action being taken by the pch or the interface. reads from the register return the last value written to it. bit description 31:20 reserved 19:16 port multiplier port (pmp) ? r/w. this field is not used by ahci 15:12 select power management (spm) ? r/ w. this field is not used by ahci 11:8 interface power management transitions allowed (ipm) ? r/w . indicates which power states the pch is allowed to transition to: all other values reserved 7:4 speed allowed (spd) ? r/w. indicates the highest allowable speed of the interface. this speed is limited by the ca p.iss (abar+00h:bit 23:20) field. the pch supports gen 1 communication rates (1.5 gb/s), gen 2 rates (3.0 gb/s) and gen 3 rates (6.0 gb/s) (supported speeds are determined by sku; see section 1.3 ) if software changes spd after port has been enabled, software is required to perform a port reset using det=1h. this field shall remain 1h until set to another value by software. value description 0h no interface restrictions 1h transitions to the partial state disabled 2h transitions to the slumber state disabled 3h transitions to both partial and slumber states disabled value description 0h no speed negotiation restrictions 1h limit speed negotiation to generation 1 communication rate 2h limit speed negotiation to generation 2 communication rate 3h limit speed negotiation to generation 3 communication rate
sata controller registers (d31:f2) 612 datasheet 14.4.2.12 pxserrport [5:0] serial ata error register (d31:f2) address offset: port 0: abar + 130h attribute: r/wc port 1: abar + 1b0h port 2: abar + 230h (if port available; see section 1.3 ) port 3: abar + 2b0h (if port available; see section 1.3 ) port 4: abar + 330h port 5: abar + 3b0h default value: 00000000h size: 32 bits bits 26:16 of this register contain diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. bits 11:0 contain error information used by host software in determining the appropriate response to the error condition. if one or more of bits 11:8 of this register are set, the controller will stop the current transfer. 3:0 device detection initialization (det) ? r/w. controls the pch?s device detection and interface initialization. all other values reserved. when this field is written to a 1h, the pch initiates comreset and starts the initialization process. when the initialization is complete, this field shall remain 1h until set to another value by software. this field may only be change d to 1h or 4h when pxcmd.st is 0. changing this field while the pch is running results in undefined behavior. note: it is permissible to implement any of the serial ata de fined behaviors for transmission of comreset when det=1h. bit description value description 0h no device detection or initialization action requested 1h perform interface communication initialization sequence to establish communication. this is fu nctionally equivalent to a hard reset and results in the interface being reset and communications re-initialized 4h disable the serial ata interface and put phy in offline mode bit description 31:27 reserved 26 exchanged (x) ? r/wc. when set to 1, this bit indicates that a change in device presence has been detected since the last time this bit was cleared. this bit shall always be set to 1 an ytime a cominit signal is received. this bit is reflected in the p0is.pcs bit. 25 unrecognized fis type (f) ? r/wc. indicates that one or more fiss were received by the transport layer with good crc, but had a type field that was not recognized. 24 transport state transition error (t) ? r/wc. indicates that an error has occurred in the transition from one state to another within the transport layer since the last time this bit was cleared. 23 link sequence error (s): indicates that one or more link state machine error conditions was encountered. the link layer state machine defines the conditions under which the link layer detect s an erroneous transition.
datasheet 613 sata controller registers (d31:f2) 22 handshake (h) ? r/wc. indicates that one or more r_err handshake response was received in response to frame transmission . such errors may be the result of a crc error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. 21 crc error (c) ? r/wc. indicates that one or more crc errors occurred with the link layer. 20 disparity error (d) ? r/wc. this field is not used by ahci. 19 10b to 8b decode error (b) ? r/wc. indicates that one or more 10b to 8b decoding errors occurred. 18 comm wake (w) ? r/wc. indicates that a comm wa ke signal was detected by the phy. 17 phy internal error (i) ? r/wc. indicates that the phy detected some internal error. 16 phyrdy change (n) ? r/wc. when set to 1, this bit indicates that the internal phyrdy signal changed state sinc e the last time this bit was cleared. in the pch, this bit will be set when phyrdy changes from a 0 -> 1 or a 1 -> 0. the state of this bit is then reflected in the pxis.prcs inte rrupt status bit and an inte rrupt will be generated if enabled. software clears this bit by writing a 1 to it. 15:12 reserved 11 internal error (e) ? r/wc. the sata controller failed due to a master or target abort when attempting to access system memory. 10 protocol error (p) ? r/wc. a violation of the seri al ata protocol was detected. note: the pch does not set this bit for all prot ocol violations that may occur on the sata link. 9 persistent communication or data integrity error (c) ? r/wc. a communication error that was not recovered occurred that is expected to be persistent. persistent communications errors may arise from faulty interconnect with the device, from a device that has been removed or has failed, or a number of other causes. 8 transient data integrity error (t) ? r/wc. a data integrity error occurred that was not recovered by the interface. 7:2 reserved 1 recovered communications error (m) ? r/wc. communicat ions between the device and host was temporarily lost but was re-established. this can arise from a device temporarily being removed, from a te mporary loss of phy synchronization, or from other causes and may be derived from the phynrdy signal between the phy and link layers. 0 recovered data integrity error (i) ? r/wc. a data integrit y error occurred that was recovered by the interface through a re try operation or other recovery action. bit description
sata controller registers (d31:f2) 614 datasheet 14.4.2.13 pxsactport [5:0] serial ata active register (d31:f2) address offset: port 0: abar + 134h attribute: r/w port 1: abar + 1b4h port 2: abar + 234h (if port available; see section 1.3 ) port 3: abar + 2b4h (if port available; see section 1.3 ) port 4: abar + 334h port 5: abar + 3b4h default value: 00000000h size: 32 bits 14.4.2.14 pxciport [5:0] command issue register (d31:f2) address offset: port 0: abar + 138h attribute: r/w port 1: abar + 1b8h port 2: abar + 238h (if port available; see section 1.3 ) port 3: abar + 2b8h (if port available; see section 1.3 ) port 4: abar + 338h port 5: abar + 3b8h default value: 00000000h size: 32 bits bit description 31:0 device status (ds) ? r/w. system software sets this bi t for sata queuing operations prior to setting the pxci.ci bit in the same command slot entry. this field is cleared using the set device bits fis. this field is also cleared when pxcmd. st (abar+118h/198h/218h/298h:bit 0) is cleared by software, and as a result of a comreset or srst. bit description 31:0 commands issued (ci) ? r/w. this field is set by software to indicate to the pch that a command has been buil t-in system memory for a command slot and may be sent to the device. when the pch receives a fis which clears the bsy and drq bits for the command, it clears the correspon ding bit in this register for that command slot. bits in this field shall only be set to 1 by software when pxcmd.st is set to 1. this field is also cleared when pxcmd. st (abar+118h/198h/218h/298h:bit 0) is cleared by software.
datasheet 615 sata controller registers (d31:f5) 15 sata controller registers (d31:f5) 15.1 pci configuration registers (sataCd31:f5) note: address locations that are not shown should be treated as reserved. all of the sata registers are in the core well. none of the registers can be locked. table 15-1. sata controller pci register address map (sataCd31:f5) (sheet 1 of 2) offset mnemonic register name default attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 02b0h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface see register description see register description 0ah scc sub class code see register description see register description 0bh bcc base class code 01h ro 0dh pmlt primary master latency timer 00h ro 10h?13h pcmd_bar primary command block base address 00000001h r/w, ro 14h?17h pcnl_bar primary control block base address 00000001h r/w, ro 18h?1bh scmd_bar secondary command block base address 00000001h r/w, ro 1ch?1fh scnl_bar secondary control block base address 00000001h r/w, ro 20h?23h bar legacy bus master base address 00000001h r/w, ro 24h?27h sidpba serial ata index / data pair base address 00000000h see register description 2ch?2dh svid subsystem vendor identification 0000h r/wo 2eh?2fh sid subsystem identification 0000h r/wo 34h cap capabilities pointer 80h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description ro 40h?41h ide_tim primary ide timing register 0000h r/w 42h?43h ide_tim secondary ide timing registers 0000h r/w
sata controller registers (d31:f5) 616 datasheet note: the pch sata controller is not arbitrated as a pci device; therefore, it does not need a master latency timer. 15.1.1 vidvendor iden tification regist er (satad31:f5) offset address: 00h ? 01h attribute: ro default value: 8086h size: 16 bit lockable: no power well: core 15.1.2 diddevice identificati on register (satad31:f5) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16 bit lockable: no power well: core 70h?71h pid pci power management capability id see register description ro 72h?73h pc pci power management capabilities 4003h ro 74h?75h pmcs pci power management control and status 0008h r/w, ro, r/wc 90h?91h map address map 0000h r/w 92h?93h pcs port control and status 0000h r/w, ro, r/wc a8h?abh satacr0 sata capability register 0 0010b012h ro, r/wo ach?afh satacr1 sata capability register 1 00000048h ro b0h?b1h flrcid flr capability id 0009h ro b2h?b3h flrclv flr capability length and value 2006h ro b4h?b5h flrctrl flr control 0000h r/w, ro c0h atc apm trapping control 00h r/w c4h ats atm trapping status 00h r/wc table 15-1. sata controller pci register address map (sataCd31:f5) (sheet 2 of 2) offset mnemonic register name default attribute bit description 15:0 vendor id ? ro. this is a 16-bit value as signed to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the pch sata controller. note: the value of this field will change dependent upon the value of the map register. see section and section 15.1.25
datasheet 617 sata controller registers (d31:f5) 15.1.3 pcicmdpci command register (sataCd31:f5) address offset: 04h ? 05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. this disables pin-based intx# interrupts. this bit has no effect on msi operation. 0 = internal intx# messages are generated if there is an interrupt and msi is not enabled. 1 = internal intx# messages will not be generated. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? ro. hardwired to 0. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? r/w. 0 = disabled. sata controller will not gene rate perr# when a data parity error is detected. 1 = enabled. sata controller will generate pe rr# when a data parity error is detected. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle en able (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. this bit controls the pch ability to act as a pci master for ide bus master transfers. this bit does not impact the generation of completions for split transaction commands. 1 memory space enable (mse) ? ro. this controller does not support ahci; therefore, no memory space is required. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disables access to the legacy or native ide ports (both primary and secondary) as well as the bus mast er i/o registers. 1 = enable. note that the base address register for the bus master registers should be programmed before this bit is set.
sata controller registers (d31:f5) 618 datasheet 15.1.4 pcists pci status register (sataCd31:f5) address offset: 06h ? 07h attribute: r/wc, ro default value: 02b0h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 15.1.5 ridrevision identificati on register (satad31:f5) offset address: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected by sata controller. 1 = sata controller detects a parity error on its interface. 14 signaled system error (sse) ? ro. hardwired to 0. 13 received master abort (rma) ? r/wc. 0 = master abort not generated. 1 = sata controller, as a master , generated a master abort. 12 reserved 11 signaled target abort (sta) ? ro. hardwired to 0. 10:9 devsel# timing status (dev_sts) ? ro. 01 = hardwired; controls the devi ce select time for the sata controller?s pci interface. 8 data parity error detected (dped) ? r/wc. for pch, this bit can only be set on read completions received from sibu s where there is a parity error. 1 = sata controller, as a master, either detect s a parity error or sees the parity error line asserted, and the parity error response bit (bit 6 of the command register) is set. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (udf) ? ro. hardwired to 0. 5 66mhz capable (66mhz_cap) ? ro. hardwired to 1. 4 capabilities list (cap_list) ? ro. this bit indicates the presence of a capabilities list. the minimum requirement for the capabili ties list must be pci power management for the sata controller. 3 interrupt status (ints) ? ro. reflects the state of intx# messages, irq14 or irq15. 0 = interrupt is cleared (ind ependent of the state of in terrupt disabl e bit in the command register [offset 04h]). 1 = interrupt is to be asserted 2:0 reserved bit description 7:0 revision id ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register.
datasheet 619 sata controller registers (d31:f5) 15.1.6 piprogrammin g interface register (sataCd31:f5) address offset: 09h attribute: ro default value: 85h size: 8 bits when scc = 01h 15.1.7 sccsub class code register (sataCd31:f5) address offset: 0ah attribute: ro default value: 01h size: 8 bits 15.1.8 bccbase clas s code register (sataCd31:f5sataCd31:f5) address offset: 0bh attribute: ro default value: 01h size: 8 bits bit description 7 this read-only bit is a 1 to indicate that the pch supports bus master operation 6:4 reserved 3 secondary mode native capable (snc) ? ro. indicates whether or not the secondary channel has a fixed mode of operation. 0 = indicates the mode is fixed and is dete rmined by the (read-only) value of bit 2. this bit will always return 0. 2 secondary mode nati ve enable (sne) ? ro. determines the mode th at the secondary channel is operating in. 1 = secondary controller operating in native pci mode. this bit will always return 1. 1 primary mode native capable (pnc) ? ro. indicates whether or not the primary channel has a fixed mode of operation. 0 = indicates the mode is fixed and is dete rmined by the (read-only) value of bit 0. this bit will always return 0. 0 primary mode native enable (pne) ? ro. determines the mode that the primary channel is operating in. 1 = primary controller operating in native pci mode. this bit will always return 1. bit description 7:0 sub class code (scc) ? ro. the value of this field determines whethe r the controller supports legacy ide mode. bit description 7:0 base class code (bcc) ? ro. 01h = mass storage device
sata controller registers (d31:f5) 620 datasheet 15.1.9 pmltprimary master latency timer register (sataCd31:f5) address offset: 0dh attribute: ro default value: 00h size: 8 bits 15.1.10 pcmd_barprimary co mmand block base address register (sataCd31:f5) address offset: 10h ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits note: this 8-byte i/o space is used in native mo de for the primary cont roller?s command block. 15.1.11 pcnl_barprimary contro l block base address register (sataCd31:f5) address offset: 14h ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mo de for the primary cont roller?s command block. bit description 7:0 master latency timer count (mltc) ? ro. 00h = hardwired. the sata controller is im plemented internally, and is not arbitrated as a pci device, so it does no t need a master latency timer. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space.
datasheet 621 sata controller registers (d31:f5) 15.1.12 scmd_barsecondary co mmand block base address register (sata d31:f5) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 8-byte i/o space is used in native mode for the secondary controller?s command block. 15.1.13 scnl_barsecondary co ntrol block base address register (sata d31:f5) address offset: 1ch ? 1fh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space.
sata controller registers (d31:f5) 622 datasheet 15.1.14 barlegacy bus master base address register (sataCd31:f5) address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits the bus master ide interface function uses base address register 5 to request a 16- byte i/o space to provide a software inte rface to the bus master functions. only 12 bytes are actually used (6 bytes for prim ary, 6 bytes for secondary). only bits [15:4] are used to decode the address. 15.1.15 sidpbasata index/data pair base address register (sataCd31:f5) address offset: 24h ? 27h attribute: r/w, ro default value: 00000000h size: 32 bits when scc is 01h when the programming interface is ide, the register represents an i/o bar allocating 16b of i/o space for the i/o mapped registers defined in section 15.3 . note that although 16b of locations are allocated, some maybe reserved. bit description 31:16 reserved 15:5 base address ? r/w. this field provides the ba se address of the i/o space (16 consecutive i/o locations). 4 base address 4 (ba4) ? r/w. when scc is 01h, this bit will be r/w re sulting in requesting 16b of i/o space. 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:4 base address (ba) ? r/w. base address of register i/o space 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space.
datasheet 623 sata controller registers (d31:f5) 15.1.16 svidsubsystem vendor identification register (sataCd31:f5) address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core function level reset: no 15.1.17 sidsubsystem identification register (sataCd31:f5) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 15.1.18 capcapabilities poin ter register (sataCd31:f5) address offset: 34h attribute: ro default value: 70h size: 8 bits 15.1.19 int_lninterrupt line register (sataCd31:f5) address offset: 3ch attribute: r/w default value: 00h size: 8 bits function level reset: no 15.1.20 int_pninterrupt pi n register (sataCd31:f5) address offset: 3dh attribute: ro default value: see register description size: 8 bits bit description 15:0 subsystem vendor id (svid) ? r/wo. value is written by bios. no hardware action taken on this value. bit description 15:0 subsystem id (sid) ? r/wo. value is written by bios. no hardware action taken on this value. bit description 7:0 capabilities pointer (cap_ptr) ? ro. indicates that the first capability pointer offset is 70h if the sub cl ass code (scc) (dev 31:f2:0ah ) is configure as ide mode (value of 01). bit description 7:0 interrupt line ? r/w. this field is used to communicate to software the interrupt line that the interrupt pin is connected to. these bits are not reset by flr. bit description 7:0 interrupt pin ? ro. this reflects the value of d31ip.sip1 (chipset config registers:offset 3100h:bits 11:8).
sata controller registers (d31:f5) 624 datasheet 15.1.21 ide_timide timing register (sataCd31:f5) address offset: primary: 40h?41h attribute: r/w secondary: 42h?43h default value: 0000h size: 16 bits 15.1.22 pidpci power management capability identification register (sataCd31:f5) address offset: 70h ? 71h attribute: ro default value: b001h size: 16 bits 15.1.23 pcpci power manageme nt capabilities register (sataCd31:f5) address offset: 72h ? 73h attribute: ro default value: 4003h size: 16 bits bit description 15 ide decode enable (ide) ? r/w. individually enable /disable the primary or secondary decode. 0 = disable. 1 = enables the pch to decode the associat ed command blocks (1f0?1f7h for primary, 170?177h for secondary) and control block (3f6h for primary and 376h for secondary). this bit effects the ide decode ranges fo r both legacy and native-mode decoding. note: this bit affects sata operation in both combined and non-combined ata modes. see section 5.16 for more on ata modes of operation. 14:0 reserved bits description 15:8 next capability (next) ? ro. when scc is 01h, this fi eld will be b0h indicating the next item is flr capability pointer in the list. 7:0 capability id (cid) ? ro. indicates that this poin ter is a pci power management. bits description 15:11 pme support (pme_sup) ? ro. by default with scc = 01h, the default value of 00000 indicates no pme support in ide mode. 10 d2 support (d2_sup) ? ro. hardwired to 0. the d2 state is not supported 9 d1 support (d1_sup) ? ro. hardwired to 0. the d1 state is not supported 8:6 auxiliary current (aux_cur) ? ro. pme# from d3 cold state is not supported, therefore this field is 000b. 5 device specific initialization (dsi) ? ro. ha rdwired to 0 to indicate that no device- specific initialization is required. 4 reserved 3 pme clock (pme_clk) ? ro. hardwired to 0 to in dicate that pci clock is not required to generate pme#. 2:0 version (ver) ? ro. hardwired to 011 to indicates support for revision 1.2 of the pci power management specification.
datasheet 625 sata controller registers (d31:f5) 15.1.24 pmcspci power mana gement control and status register (sataCd31:f5) address offset: 74h ? 75h attribute: ro, r/w, r/wc default value: 0008h size: 16 bits function level reset: no (bits 8 and 15 only) bits description 15 pme status (pmes) ? r/wc. bit is set when a pme event is to be requested, and if this bit and pmee is set, a pme# will be generated from the sata controller. note: when scc=01h this bit will be ro 0. soft ware is advised to clear pmee together with pmes prior to changing scc through map.sms. this bit is not reset by function level reset. 14:9 reserved 8 pme enable (pmee) ? r/w. when scc is not 01h, th is bit r/w. when set, the sata controller generates pme# form d3 hot on a wake event. note: when scc=01h this bit will be ro 0. software is advised to clear pmee together with pmes prior to changing scc through map.sms. this bit is not reset by function level reset. 7:4 reserved 3 no soft reset (nsfrst) ? ro. these bits are used to indicate whether devices transitioning from d3 hot state to d0 state will perform an internal reset. 0 = device transitioning from d3 hot state to d0 state perfo rm an internal reset. 1 = device transitioning from d3 hot state to d0 state do not perform an internal reset. configuration content is preserved. upon transition from the d3 hot state to d0 state initialized state, no addition al operating system interventi on is required to preserve configuration context beyond writing to the powerstate bits. regardless of this bit, the controller transition from d3 hot state to d0 state by a system or bus segment reset will return to the state d0 uninitialized with only pme context preserved if pme is supported and enabled. 2reserved 1:0 power state (ps) ? r/w. these bits are used both to determine the current power state of the sata controller and to set a new power state. 00 = d0 state 11 = d3 hot state when in the d3 hot state, the controller?s configurat ion space is available, but the i/o and memory spaces are not. addi tionally, interrupts are blocked.
sata controller registers (d31:f5) 626 datasheet 15.1.25 mapaddress map re gister (sataCd31:f5) address offset: 90h?91h attribute: r/w, r/wo, ro default value: 0000h size: bits function level reset: no (bits 9:8 only) bits description 15:8 reserved 7:6 sata mode select (sms) ? r/w. software programs these bits to control the mode in which the sata controller should operate. 00b = ide mode all other combinations are reserved. 5:2 reserved 1:0 map value (mv) ? reserved
datasheet 627 sata controller registers (d31:f5) 15.1.26 pcsport control and st atus register (sataCd31:f5) address offset: 92h ? 93h attribute: r/w, ro default value: 0000h size: 16 bits function level reset: no by default, the sata ports are set to the di sabled state (bits [5:0] = 0). when enabled by software, the ports can transition between the on, partial, and slumber states and can detect devices. when disabled, the port is in the ?off? state and cannot detect any devices. if an ahci-aware or raid enabled operating system is being booted then system bios shall insure that all supported sata ports are enabled prior to passing control to the os. once the ahci aware os is booted it becomes the enabling/disabling policy owner for the individual sata ports. this is accomplished by manipulating a port?s pxsctl and pxcmd fields. because an ahci or raid awar e os will typically not have knowledge of the pxe bits and because the pxe bits act as master on/off switches for the ports, pre- boot software must insure that these bits are set to 1 prior to booting the os, regardless as to whether or not a device is currently on the port. bits description 15:10 reserved 9 port 5 present (p5p) ? ro. the status of this bit may change at any ti me. this bit is cleared when the port is disabled using p1 e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 1 has been detected. 8 port 4 present (p4p) ? ro. the status of this bit may change at any ti me. this bit is cleared when the port is disabled using p0 e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 0 has been detected. 7:2 reserved 1 port 5 enabled (p5e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition betwee n the on, partial, an d slumber states and can detect devices. this bit is read-only 0 when map.spd[1]= 1. 0 port 4 enabled (p4e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition betwee n the on, partial, an d slumber states and can detect devices. this bit is read-only 0 when map.spd[0]= 1.
sata controller registers (d31:f5) 628 datasheet 15.1.27 satacr0 sata capabilit y register 0 (sataCd31:f5) address offset: a8h?abh attribute: ro, r/wo default value: 0010b012h size: 32 bits function level reset: no (bits 15:8 only) note: when scc is 01h this register is read-only 0. 15.1.28 satacr1 sata capabilit y register 1 (sataCd31:f5) address offset: ach?afh attribute: ro default value: 00000048h size: 32 bits when scc is 01h this register is read-only 0. 15.1.29 flrcid flr capability id register (sataCd31:f5) address offset: b0h?b1h attribute: ro default value: 0009h size: 16 bits bit description 31:24 reserved 23:20 major revision (majrev) ? ro. major revision number of the sata capability pointer implemented. 19:16 minor revision (minrev) ? ro. minor revision number of the sata capability pointer implemented. 15:8 next capability pointer (next) ? r/wo. points to the ne xt capability structure. 7:0 capability id (cap) ? ro. the value of 12h has been assigned by the pci sig to designate the sata capability pointer. bit description 31:16 reserved 15:4 bar offset (barofst) ? ro. indicates the offset into the bar where the index/data pair are located (in dword granularity). the index and data i/o registers are located at offset 10h within the i/o space defined by lbar (bar4). a value of 004h indicates offset 10h. 3:0 bar location (barloc) ? ro. indicates the absolute pci configuration register address of the bar containing the index/da ta pair (in dword granularity). the index and data i/o registers reside within the sp ace defined by lbar (bar4) in the sata controller. a value of 8h indicates and offset of 20h, which is lbar (bar4). bit description 15:8 next capability pointer ? ro. a value of 00h indicates the final item in the capability list. 7:0 capability id ? ro. the value of this field depends on the flrcssecl bit. if flrcssel = 0, this field is 13h if flrcssel = 1, this fi eld is 09h, indicating vend or specific capability.
datasheet 629 sata controller registers (d31:f5) 15.1.30 flrclv flr ca pability length and value register (sataCd31:f5) address offset: b2h?b3h attribute: ro, r/wo default value: 2006h size: 16 bits function level reset: no (bits 9:8 only) when flrcssel = 0, this register is defined as follows: when flrcssel = 1, this register is defined as follows: 15.1.31 flrctrl flr control register (sataCd31:f5) address offset: b4h?b5h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:10 reserved 9 flr capability ? r/wo. this field indicates su pport for function level reset. 8 txp capability ? r/wo. this field indicates supp ort for the transactions pending (txp) bit. txp must be suppo rted if flr is supported. 7:0 capability length ? ro. this field indicates the number of bytes of the vendor specific capability as required by the pci specification. it has the value of 06h for flr capability. bit description 15:12 vendor specific capability id ? ro. a value of 02h identifies this capability as a function level reset. 11:8 capability version ? ro. this field indicates the version of the flr capability. 7:0 capability length ? ro. this field indicates the number of bytes of the vendor specific capability as required by the pci specification. it has the value of 06h for flr capability. bit description 15:9 reserved 8 transactions pending (txp) ? ro. 0 = completions for all non-po sted requests have been received by the controller. 1 = controller has issued non-posted request which has not been completed. 7:1 reserved 0 initiate flr ? r/w. used to initiate flr transition. a write of 1 indicates flr transition.
sata controller registers (d31:f5) 630 datasheet 15.1.32 atcapm trapping cont rol register (sataCd31:f5) address offset: c0h attribute: r/w default value: 00h size: 8 bits note: this sata controller does not support legacy i/o access. therefore, this register is reserved. software shall not ch ange the default values of the register; otherwise, the result will be undefined. 15.1.33 atcapm trapping cont rol register (sataCd31:f5) address offset: c4h attribute: r/wc default value: 00h size: 8 bits note: this sata controller does not support legacy i/o access. therefore, this register is reserved. software shall not change the default values of the register; otherwise the result will be undefined. bit description 7:0 reserved bit description 7:0 reserved
datasheet 631 sata controller registers (d31:f5) 15.2 bus master ide i/ o registers (d31:f5) the bus master ide function uses 16 byte s of i/o space, allocated using the bar register, located in device 31:function 2 configuration space, offset 20h. all bus master ide i/o space registers can be accessed as byte, word, or dword quantities. reading reserved bits returns an indetermin ate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). these registers are only used for legacy operation. software must not use these registers when running ahci. the description of the i/o registers is shown in ta b l e 1 5 - 2 . table 15-2. bus master ide i/o register address map bar+ offset mnemonic register default attribute 00 bmicp command register primary 00h r/w 01 ? reserved ? ro 02 bmisp bus master ide status register primary 00h r/w, r/wc, ro 03 ? reserved ? ro 04?07 bmidp bus master ide descriptor table pointer primary xxxxxxxxh r/w 08 bmics command register secondary 00h r/w 09 ? reserved ? ro 0ah bmiss bus master ide status register secondary 00h r/w, r/wc, ro 0bh ? reserved ? ro 0ch?0fh bmids bus master ide descriptor table pointer secondary xxxxxxxxh r/w
sata controller registers (d31:f5) 632 datasheet 15.2.1 bmic[p,s]bus master id e command register (d31:f5) address offset: primary: bar + 00h attribute: r/w secondary: bar + 08h default value: 00h size: 8 bits bit description 7:4 reserved 3 read / write control (r/wc) ? r/w. this bit sets the di rection of the bus master transfer: this bit must not be changed when the bus master function is active. 0 = memory reads 1 = memory writes 2:1 reserved 0 start/stop bus master (start) ? r/w. 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. if this bit is reset while bus master operation is still active (that is, the bus master ide active bit (d31:f5:bar + 02h, bit 0) of the bus master ide status register for that ide channel is set) and the drive has not yet finished its data transfer (the interrupt bit in the bus master ide status register for that ide channel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the co ntroller. bus master operation does not actually start unle ss the bus master enable bit (d31:f5:04h, bit 2) in pci configuration space is also set. bus master operation begins when this bit is detected changing from 0 to 1. the contro ller will transfer data between the ide device and memory only when this bit is set. master operation can be halted by writing a 0 to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bu s master ide active bit being cleared or the interrupt bit of the bus master ide status register for that ide channel being set, or both. hardware does not clea r this bit automatically. if this bit is cleared to 0 prior to the dma data transfer being initiated by the drive in a device to memory data transfer, then th e pch will not send dmat to terminate the data transfer. sw intervention (such as, sending srst) is required to reset the interface in this condition.
datasheet 633 sata controller registers (d31:f5) 15.2.2 bmis[p,s]bus master id e status register (d31:f5) address offset: primary: bar + 02h attribute: r/w, r/wc, ro secondary: bar + 0ah default value: 00h size: 8 bits 15.2.3 bmid[p,s]bus master id e descriptor table pointer register (d31:f5) address offset: primary: bar + 04h?07h attribute: r/w secondary: bar + 0ch ? 0fh default value: all bits undefined size: 32 bits bit description 7 prd interrupt status (prdis) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the host controller execution of a prd that has its prd_int bit set. 6 reserved 5 drive 0 dma capable ? r/w. 0 = not capable 1 = capable. set by device de pendent code (bios or device driver) to indicate that drive 0 for this channel is capable of dm a transfers, and that the controller has been initialized for optimum performance. the pch does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 4:3 reserved 2 interrupt ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set when a device fis is received with the ?i? bit set, provided that software has not disabled interrupts using the ien bit of the device control regi ster (see chapter 5 of the serial ata specification , revision 1.0a). 1 error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the controller encoun ters a target abort or master abort when transferring data on pci. 0 bus master ide active (act) ? ro. 0 = this bit is cleared by the pch when the last transfer for a region is performed, where eot for that region is set in the region descriptor. it is also cleared by the pch when the start bus master bit (d31:f 5:bar+ 00h, bit 0) is cleared in the command register. when this bit is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = set by the pch when the start bit is written to the command register. bit description 31:2 address of descriptor table (addr) ? r/w. the bits in this field correspond to bits [31:2] of the memory location of the physic al region descriptor (prd). the descriptor table must be dword-aligned. the descriptor ta ble must not cross a 64-k boundary in memory. 1:0 reserved
sata controller registers (d31:f5) 634 datasheet 15.3 serial ata index/data pair superset registers all of these i/o registers are in the core we ll. they are exposed only when scc is 01h (that is, ide programming interface) and the controller is not in combined mode. these are index/data pair registers that are used to access the serialata superset registers (serialata status, serialata control and serialata error). the i/o space for these registers is allocated through sidpba. loca tions with offset from 08h to 0fh are reserved for future expansion. software-write operations to the reserved locations shall have no effect while software-read operations to the reserved locations shall return 0. 15.3.1 sindxsata index register (d31:f5) address offset: sidpba + 00h attribute: r/w default value: 00000000h size: 32 bits note: these are index/data pair registers that are used to access the ssts, sctl, and serr. the i/o space for these registers is allocated through sidpba. 15.3.2 sdatasata index data register (d31:f5) address offset: sidpba + 04h attribute: r/w default value: all bits undefined size: 32 bits note: these are index/data pair registers that are used to access the ssts, sctl, and serr. the i/o space for these registers is allocated through sidpba. bit description 31:16 reserved 15:8 port index (pidx) ? r/w. this index field is used to specify the port of the sata controller at which the po rt-specific ssts, sctl, and serr registers are located. 00h = primary master (port 4) 02h = secondary master (port 5) all other values are reserved. 7:0 register index (ridx) ? r/w. this index field is used to specify one out of three registers currently being indexed into. 00h = ssts 01h = sctl 02h = serr all other values are reserved bit description 31:0 data (data) ? r/w. this data register is a ?win dow? through which data is read or written to the memory mapped registers. a read or write to this data register triggers a corresponding read or write to the memory mapped register pointed to by the index register. the index regi ster must be setup prior to th e read or write to this data register. note that a physical register is not actually implemented as the data is actually stored in the memory mapped registers. since this is not a physical register, the ?default? value is the same as the default value of the register po inted to by index.
datasheet 635 sata controller registers (d31:f5) 15.3.2.1 pxsstsserial ata status register (d31:f5) address offset: attribute: ro default value: 00000000h size: 32 bits sdata when sindx.ridx is 00h. this is a 32-b it register that conveys the current state of the interface and host. th e pch updates it continuously and asynchronously. when the pch transmits a comreset to the device , this register is updated to its reset values. bit description 31:12 reserved 11:8 interface power management (ipm) ? ro . indicates the current interface state: all other values reserved. 7:4 current interface speed (spd) ? ro. indicates the negotiated interface communication speed. all other values reserved. the pch supports gen 1 communication rates (1.5 gb/s), gen 2 rates (3.0 gb/s) 3:0 device detection (det) ? ro . indicates the interface de vice detection and phy state: all other values reserved. value description 0h device not present or communication not established 1h interface in active state 2h interface in partial power management state 6h interface in slumber power management state value description 0h device not present or communication not established 1h generation 1 communication rate negotiated 2h generation 2 communication rate negotiated value description 0h no device de tected and phy communication not established 1h device presence detected but phy communication not established 3h device presence detected and phy communication established 4h phy in offline mode as a result of the interface being disabled or running in a bist loopback mode
sata controller registers (d31:f5) 636 datasheet 15.3.2.2 pxsctlserial ata control register (d31:f5) address offset: attribute: r/w, ro default value: 00000004h size: 32 bits sdata when sindx.ridx is 01h. this is a 32-bit read-write register by which software controls sata capabilities. writes to the sc ontrol register result in an action being taken by the pch or the interface. reads from the register return the last value written to it. bit description 31:20 reserved 19:16 port multiplier port (pmp) ? ro . this field is not used by ahci. 15:12 select power management (spm) ? ro. this field is not used by ahci. 11:8 interface power management transitions allowed (ipm) ? r/w . indicates which power states the pch is allowed to transition to: all other values reserved 7:4 speed allowed (spd) ? r/w. indicates the highest al lowable speed of the interface. this speed is limited by the ca p.iss (abar+00h:bit 23:20) field. all other values reserved. the pch supports gen 1 communication rates (1.5 gb/s), gen 2 rates (3.0 gb/s) 3:0 device detection initialization (det) ? r/w . controls the pch?s device detection and interface initialization. all other values reserved. value description 0h no interface restrictions 1h transitions to the partial state disabled 2h transitions to the slumber state disabled 3h transitions to both partial and slumber states disabled value description 0h no speed negotiation restrictions 1h limit speed negotiation to generation 1 communication rate 2h limit speed negotiation to generation 2 communication rate value description 0h no device detection or initialization action requested 1h perform interface communication initialization sequence to establish communication. this is fu nctionally equivalent to a hard reset and results in the interface being reset and communications re-initialized 4h disable the serial ata interface and put phy in offline mode
datasheet 637 sata controller registers (d31:f5) 15.3.2.3 pxserrserial ata error register (d31:f5) address offset: attribute: r/wc default value: 00000000h size: 32 bits sdata when sindx.ridx is 02h. bits 26:16 of this register contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. bits 11:0 contain error information used by host software in determining the appropriate response to the error condition. if one or more of bits 11:8 of this register are set, the controller will stop the current transfer. bit description 31:27 reserved 26 exchanged (x) ? r/wc. when set to 1, this bit in dicates that a change in device presence has been detected since the last time this bit was cleared. this bit shall always be set to 1 anytime a cominit signal is received. th is bit is reflected in the p0is.pcs bit. 25 unrecognized fis type (f) ? r/wc. indicates that one or more fiss were received by the transport layer with good crc, but had a type field that was not recognized. 24 transport state transition error (t) ? r/wc. indicates that an error has occurred in the transition from one state to another within the transpor t layer since the last time this bit was cleared. 23 link sequence error (s) ? r/wc. indicates that one or more link state machine error conditions was encounte red. the link layer state ma chine defines the conditions under which the link layer dete cts an erroneous transition. 22 handshake (h) ? r/wc. indicates that one or more r_err handshake response was received in response to frame transmission . such errors may be the result of a crc error detected by the recipient, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. 21 crc error (c) ? r/wc. indicates that one or more crc errors occurred with the link layer. 20 disparity error (d) ? r/wc. this field is not used by ahci. 19 10b to 8b decode error (b) ? r/wc. indicates that one or more 10b to 8b decoding errors occurred. 18 comm wake (w) ? r/wc. indicates that a comm wa ke signal was detected by the phy. 17 phy internal error (i) ? r/wc. indicates that the phy detected some internal error. 16 phyrdy change (n) ? r/wc. when set to 1, this bit indicates that the internal phyrdy signal changed state sinc e the last time this bit was cleared. in the pch, this bit will be set when phyrdy changes from a 0 -> 1 or a 1 -> 0. the state of this bit is then reflected in the pxis.prcs inte rrupt status bit and an inte rrupt will be generated if enabled. software clears this bit by writing a 1 to it. 15:12 reserved 11 internal error (e) ? r/wc. the sata controller failed due to a master or target abort when attempting to access system memory. 10 protocol error (p) ? r/wc. a violation of the seri al ata protocol was detected. note: the pch does not set this bit for all prot ocol violations that may occur on the sata link.
sata controller registers (d31:f5) 638 datasheet 9 persistent communication or data integrity error (c) ? r/wc. a communication error that was not recovered occurred that is expected to be pe rsistent. persistent communications errors may arise from faulty interconne ct with the device, from a device that has been removed or has failed, or a number of other causes. 8 transient data integrity error (t) ? r/wc. a data integrity error occurred that was not recovered by the interface. 7:2 reserved 1 recovered communications error (m) ? r/wc. communications between the device and host was temporarily lost but was re-established. this can arise from a device temporarily be ing removed, from a temporary loss of phy synchronization, or from other causes and may be derived fro m the phynrdy signal between the phy and link layers. 0 recovered data integrity error (i) ? r/wc. a data integrity error occurred that was recovered by the interface through a re try operation or other recovery action. bit description
datasheet 639 ehci controller registers (d29:f0, d26:f0) 16 ehci controller registers (d29:f0, d26:f0) 16.1 usb ehci configuration registers (usb ehcid29:f0, d26:f0) note: prior to bios initialization of the pch usb subsystem, the ehci controllers will appear as function 7. after bios initialization, the ehci controllers will be function 0. note: register address locations that are not shown in table 16-1 should be treated as reserved (see section 9.2 for details). table 16-1. usb ehci pci register address ma p (usb ehcid29:f0, d26:f0) (sheet 1 of 2) offset m nemonic register name default value attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0290h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 20h ro 0ah scc sub class code 03h ro 0bh bcc base class code 0ch ro 0dh pmlt primary master latency timer 00h ro 0eh headtyp header type 80h ro 10h?13h mem_base memory base address 00000000h r/w, ro 2ch?2dh svid usb ehci subsystem vendor identification xxxxh r/w 2eh?2fh sid usb ehci subsystem identification xxxxh r/w 34h cap_ptr capabilities pointer 50h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description ro 50h pwr_capid pci power management capability id 01h ro 51h nxt_ptr1 next item pointer 58h r/w 52h?53h pwr_cap power manage ment capabilities c9c2h r/w 54h?55h pwr_cntl_sts power management control/status 0000h r/w, r/wc, ro 58h debug_capid debug port capability id 0ah ro
ehci controller registers (d29:f0, d26:f0) 640 datasheet note: all configuration registers in this section are in the core well and reset by a core well reset and the d3-to-d0 warm reset, except as noted. 59h nxt_ptr2 next item pointer #2 98h ro 5ah?5bh debug_base debug port base offset 20a0h ro 60h usb_relnum usb release number 20h ro 61h fl_adj frame length adjustment 20h r/w 62h?63h pwake_cap port wake capabilities 01ffh r/w 64h?67h ? reserved ? ? 68h?6bh leg_ext_cap usb ehci legacy support extended capability 00000001h r/w, ro 6ch?6fh leg_ext_cs usb ehci legacy extended support control/status 00000000h r/w, r/wc, ro 70h?73h special_smi intel specific usb 2.0 smi 00000000h r/w, r/wc 74h?7fh ? reserved ? ? 80h access_cntl access control 00h r/w 84h?87h ehciir1 ehci initialization register 1 83088e01h r/w 88h?8bh ehciir2 ehci initialization register 2 04000010h r/w 98h flr_cid flr capability id 09h ro 99h flr_next flr next ca pability pointer 00h ro 9ah?9bh flr_clv flr capability length and version 2006h ro, r/wo 9ch flr_ctrl flr control 00h r/w 9dh flr_stat flr status 00h ro f4h?f7h ehciir3 ehci initialization register 3 00408588h r/w fch?ffh ehciir4 ehci initialization register 4 20591708h r/w table 16-1. usb ehci pci register address ma p (usb ehcid29:f0, d26:f0) (sheet 2 of 2) offset mnemo nic register name default value attribute
datasheet 641 ehci controller registers (d29:f0, d26:f0) 16.1.1 vidvendor identi fication register (usb ehcid29:f0, d26:f0) offset address: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 16.1.2 diddevice identification register (usb ehcid29:f0, d26:f0) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16 bits 16.1.3 pcicmdpci co mmand register (usb ehcid29:f0, d26:f0) address offset: 04h ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. bit description 15:0 device id ? ro. this is a 16-bit value assigned to the pch usb ehci controller. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the did register. bit d escription 15:11 reserved 10 interrupt disable ? r/w. 0 = the function is capable of genera ting interrupts. 1 = the function can not generate its interrupt to the interrupt controller. note that the corresponding interrupt status bit (d29:f0, d26:f0:06h, bit 3) is not affected by the interrupt enable. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. 0 = disables ehc?s capability to generate an serr#. 1 = the enhanced host controller (ehc) is ca pable of generating (internally) serr# in the following cases: ? when it receive a completion status other th an ?successful? for on e of its dma initiated memory reads on dmi (and subsequently on its internal interface). ? when it detects an address or command parity error and the parity error response bit is set. ? when it detects a data parity error (when the data is going into the ehc) and the parity error response bit is set. 7 wait cycle control (wcc) ? ro. hardwired to 0.
ehci controller registers (d29:f0, d26:f0) 642 datasheet 6 parity error response (per) ? r/w. 0 = the ehc is not checking for correct parity (on its internal interface). 1 = the ehc is checking for correct parity (o n its internal interface) and halt operation when bad parity is detect ed during the data phase. note: if the ehc detects bad parity on the addr ess or command phases when the bit is set to 1, the host controller does not take the cycle. it halts the host controller (if currently not halted) and sets the host system error bit in the usbsts register. this applies to both requ ests and completions from the system interface. this bit must be set in order for th e parity errors to generate serr#. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle en able (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. 0 = disables this functionality. 1 = enables the pch to act as a master on the pci bus for usb transfers. 1 memory space enable (mse) ? r/w. this bit controls access to the usb 2.0 memory space registers. 0 = disables this functionality. 1 = enables accesses to the usb 2.0 registers. the base address register (d29:f0, d26:f0:10h) for usb 2.0 should be pr ogrammed before this bit is set. 0 i/o space enable (iose) ? ro. hardwired to 0. bit de scription
datasheet 643 ehci controller registers (d29:f0, d26:f0) 16.1.4 pcistspci status register (usb ehcid29:f0, d26:f0) address offset: 06h ? 07h attribute: r/wc, ro default value: 0290h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. bit d escription 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = this bit is set by the pch when a parity error is seen by the ehci controller, regardless of the setting of bit 6 or bi t 8 in the command register or any other conditions. 14 signaled system error (sse) ? r/wc. 0 = no serr# signaled by the pch. 1 = this bit is set by the pch when it signal s serr# (internally). the ser_en bit (bit 8 of the command register) must be 1 for this bit to be set. 13 received master abort (rma) ? r/wc. 0 = no master abort received by ehc on a memory access. 1 = this bit is set when ehc, as a master, re ceives a master abort status on a memory access. this is treated as a host error and halts the dm a engines. this event can optionally generate an serr# by setting the serr# enable bit . 12 received target abort (rta) ? r/wc. 0 = no target abort received by ehc on memory access. 1 = this bit is set when ehc, as a master, receives a target abort status on a memory access. this is treated as a host error and halts the dm a engines. this event can optionally generate an serr# by setting the serr# enable bit (d29:f0, d26:f0:04h, bit 8). 11 signaled target abort (sta) ? ro. this bit is used to indicate when the ehci function responds to a cycle with a target abort. there is no reason for this to happen, so this bit is hardwired to 0. 10:9 devsel# timing status (devt_sts) ? ro. this 2-bit field defines the timing for devsel# assertion. 8 master data parity error detected (dped) ? r/wc. 0 = no data parity error detected on usb2.0 read completion packet. 1 = this bit is set by the pch when a data pa rity error is detected on a usb 2.0 read completion packet on the internal interface to the ehci host controller and bit 6 of the command register is set to 1. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (u df) ? ro. hardwired to 0. 5 66 mhz capable (66 mhz _cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. hardwired to 1 indicating that offset 34h contains a valid capabilities pointer. 3 interrupt status ? ro. this bit reflects the state of this functi on?s interrupt at the input of the enable/disable logic. 0 = this bit will be 0 when the interrupt is deasserted. 1 = this bit is a 1 when th e interrupt is asserted. the value reported in this bit is independen t of the value in the interrupt enable bit. 2:0 reserved
ehci controller registers (d29:f0, d26:f0) 644 datasheet 16.1.5 ridrevision iden tification register (usb ehcid29:f0, d26:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 16.1.6 piprogramming interface register (usb ehcid29:f0, d26:f0) address offset: 09h attribute: ro default value: 20h size: 8 bits 16.1.7 sccsub class code register (usb ehcid29:f0, d26:f0) address offset: 0ah attribute: ro default value: 03h size: 8 bits 16.1.8 bccbase class code register (usb ehcid29:f0, d26:f0) address offset: 0bh attribute: ro default value: 0ch size: 8 bits bit description 7:0 revision id ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit de scription 7:0 programming interface ? ro. a value of 20h indica tes that this usb 2.0 host controller conforms to the ehci specification. bit de scription 7:0 sub class code (scc) ? ro. 03h = universal serial bus host controller. bit de scription 7:0 base class code (bcc) ? ro. 0ch = serial bus controller.
datasheet 645 ehci controller registers (d29:f0, d26:f0) 16.1.9 pmltprimary master latency timer register (usb ehcid29:f0, d26:f0) address offset: 0dh attribute: ro default value: 00h size: 8 bits 16.1.10 headtypheader type register (usb ehcid29:f0, d26:f0) address offset: 0eh attribute: ro default value: 80h size: 8 bits 16.1.11 mem_basememory base address register (usb ehcid29:f0, d26:f0) address offset: 10h ? 13h attribute: r/w, ro default value: 00000000h size: 32 bits bit d escription 7:0 master latency timer count (mltc) ? ro. hardwired to 00h. because the ehci controller is internally implemented with ar bitration on an interface (and not pci), it does not need a master latency timer. bit description 7 multi-function device ? ro. when set to ?1? indicates this is a multifunction device: 0 = single-func tion device 1 = multi-function device. 6:0 configuration layout. hardwired to 00h, whic h indicates the standard pci configuration layout. bit d escription 31:10 base address ? r/w. bits [31:10] correspond to memory address signals [31:10], respectively. this gives 1-kb of locatable memory space aligned to 1-kb boundaries. 9:4 reserved 3 prefetchable ? ro. hardwired to 0 indicating that this range should not be prefetched. 2:1 type ? ro. hardwired to 00b indicating th at this range can be mapped anywhere within 32-bit address space. 0 resource type indicator (rte) ? ro. hardwired to 0 indicating that the base address field in this regist er maps to memory space.
ehci controller registers (d29:f0, d26:f0) 646 datasheet 16.1.12 svidusb ehci subsys tem vendor id register (usb ehcid29:f0, d26:f0) address offset: 2ch ? 2dh attribute: r/w default value: xxxxh size: 16 bits reset: none 16.1.13 sidusb ehci subsystem id register (usb ehcid29:f0, d26:f0) address offset: 2eh ? 2fh attribute: r/w default value: xxxxh size: 16 bits reset: none 16.1.14 cap_ptrcapabiliti es pointer register (usb ehcid29:f0, d26:f0) address offset: 34h attribute: ro default value: 50h size: 8 bits 16.1.15 int_lninterrupt line register (usb ehcid29:f0, d26:f0) address offset: 3ch attribute: r/w default value: 00h size: 8 bits function level reset: no bit de scription 15:0 subsystem vendor id (svid) ? r/w. this register, in combination with the usb 2.0 subsystem id register, enable s the operating system to distinguish each subsystem from the others. note: writes to this register are enable d when the wrt_rdonly bit (d29:f0, d26:f0:80h, bit 0) is set to 1. bit de scription 15:0 subsystem id (sid) ? r/w. bios sets the value in this register to identify the subsystem id. this register, in combination with the subsystem vendor id register, enables the operating system to distinguish each subsystem from other(s). note: writes to this register are enable d when the wrt_rdonly bit (d29:f0, d26:f0:80h, bit 0) is set to 1. bit de scription 7:0 capabilities pointer (cap_ptr) ? ro. this register points to the starting offset of the usb 2.0 capabilities ranges. bit de scription 7:0 interrupt line (int_ln) ? r/w. this data is not used by the pch. it is used as a scratchpad register to communicate to software the interrupt line that the interrupt pin is connected to.
datasheet 647 ehci controller registers (d29:f0, d26:f0) 16.1.16 int_pninterrupt pin register (usb ehcid29:f0, d26:f0) address offset: 3dh attribute: ro default value: see description size: 8 bits 16.1.17 pwr_capidpci power management capability id register (usb ehcid29:f0, d26:f0) address offset: 50h attribute: ro default value: 01h size: 8 bits 16.1.18 nxt_ptr1next item pointer #1 register (usb ehcid29:f0, d26:f0) address offset: 51h attribute: r/w default value: 58h size: 8 bits bit d escription 7:0 interrupt pin ? ro. this reflects the value of d29ip.e1ip (chipset config registers:offset 3108:bits 3:0) or d26ip.e2ip (chipset config registers:offset 3114:bits 3:0). note: bits 7:4 are always 0h bit d escription 7:0 power management capability id ? ro. a value of 01h indicates that this is a pci power management ca pabilities field. bit d escription 7:0 next item pointer 1 value ? r/w (special). this regi ster defaults to 58h that indicates that the next capabi lity registers begin at configuration offset 58h. this register is writable when the wrt_rdonly bit (d29:f0, d26:f0:80h, bit 0) is set. this allows bios to effectively hide the debug port capability re gisters, if necessary. this register should only be written during sy stem initialization before the plug-and-play software has enabled any master -initiated traffic. only valu es of 58h (debug port and flr capabilities vi sible) and 98h (debug port invisibl e, next capability is flr) are expected to be programmed in this register. note: register not reset by d3-to-d0 warm reset.
ehci controller registers (d29:f0, d26:f0) 648 datasheet 16.1.19 pwr_cappower manageme nt capabilities register (usb ehcid29:f0, d26:f0) address offset: 52h ? 53h attribute: r/w, ro default value: c9c2h size: 16 bits notes: 1. normally, this register is read-only to re port capabilities to the power management software. to report different power management capa bilities, depe nding on the system in which the pch is used, bits 15:11 and 8:6 in this register are writable when the wrt_rdonly bit (d29:f0, d26:f0:80h, bit 0) is set. the value written to this register does not affect the hardware other than changing the va lue returned during a read. 2. reset: core well, but not d3-to-d0 warm reset. bit description 15:11 pme support (pme_sup) ? r/w. this 5-bit field in dicates the power states in which the function may assert pme#. the pch ehc do es not support the d1 or d2 states. for all other states, the pch ehc is capable of generating pme#. software should never need to modify this field. 10 d2 support (d2_sup) ? ro. 0 = d2 state is not supported 9 d1 support (d1_sup) ? ro. 0 = d1 state is not supported 8:6 auxiliary current (aux_cur) ? r/w . the pch ehc reports 375 ma maximum suspend well current re quired when in the d3 cold state. 5 device specific initialization (dsi )? ro. the pch reports 0, in dicating that no device-specific initialization is required. 4reserved 3 pme clock (pme_clk) ? ro. the pch reports 0, indicating that no pci clock is required to generate pme#. 2:0 version (ver) ? ro. the pch reports 010b, indicating that it complies with revision 1.1 of the pci power management specification.
datasheet 649 ehci controller registers (d29:f0, d26:f0) 16.1.20 pwr_cntl_stspower management control/ status register (usb ehcid29:f0, d26:f0) address offset: 54h ? 55h attribute: r/w, r/wc, ro default value: 0000h size: 16 bits function level reset: no (bits 8 and 15 only) note: reset (bits 15, 8): suspend well, and not d3 -to-d0 warm reset nor core well reset. bit description 15 pme status ? r/wc. 0 = writing a 1 to this bit will clear it and cause the internal pme to deassert (if enabled). 1 = this bit is set when the pch ehc wo uld normally assert the pme# signal independent of the state of the pme_en bit. note: this bit must be ex plicitly cleared by the operating system each time the operating system is loaded. this bit is not reset by function level reset. 14:13 data scale ? ro. hardwired to 00b indicating it does not support the associated data register. 12:9 data select ? ro. hardwired to 0000b indica ting it does not support the associated data register. 8 pme enable ? r/w. 0 = disable. 1 = enables the pch ehc to generate an inte rnal pme signal when pme_status is 1. note: this bit must be explicitly cleared by the operating system each time it is initially loaded. this bit is not reset by function level reset. 7:2 reserved 1:0 power state ? r/w. this 2-bit field is used both to determine the cu rrent power state of ehc function and to set a new power state. the definition of the field values are: 00 = d0 state 11 = d3 hot state if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. when in the d3 hot state, the pch must not accept accesses to the ehc memory range; but the configuration space must still be ac cessible. when not in the d0 state, the generation of the interrupt output is blocked. specifically, the pirqh is not asserted by the pch when not in the d0 state. when software changes this value from the d3 hot state to the d0 state, an internal warm (soft) reset is generated, and so ftware must re-initialize the function.
ehci controller registers (d29:f0, d26:f0) 650 datasheet 16.1.21 debug_capiddebug port capability id register (usb ehcid29:f0, d26:f0) address offset: 58h attribute: ro default value: 0ah size: 8 bits 16.1.22 nxt_ptr2next item pointer #2 register (usb ehcid29:f0, d26:f0) address offset: 59h attribute: ro default value: 98h size: 8 bits function level reset: no 16.1.23 debug_basedebug port base offset register (usb ehcid29:f0, d26:f0) address offset: 5ah ? 5bh attribute: ro default value: 20a0h size: 16 bits 16.1.24 usb_relnumusb release number register (usb ehcid29:f0, d26:f0) address offset: 60h attribute: ro default value: 20h size: 8 bits bit de scription 7:0 debug port capability id ? ro. hardwired to 0ah indicating that this is the start of a debug port capability structure. bit de scription 7:0 next item pointer 2 capability ? ro. this register points to the next capability in the function level reset capability structure. bit description 15:13 bar number ? ro. hardwired to 001b to indicate the memory bar begins at offset 10h in the ehci configuration space. 12:0 debug port offset ? ro. hardwired to 0a0h to indica te that the debu g port registers begin at offset a0h in the ehci memory range. bit de scription 7:0 usb release number ? ro. a value of 20h indicates that this controller follows universal serial bus (usb) specification, revision 2.0 .
datasheet 651 ehci controller registers (d29:f0, d26:f0) 16.1.25 fl_adjframe length adjustment register (usb ehcid29:f0, d26:f0) address offset: 61h attribute: r/w default value: 20h size: 8 bits function level reset: no this feature is used to adjust any offset from the clock source that generates the clock that drives the sof counter. when a new value is written into these six bits, the length of the frame is adjusted. its initial prog rammed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. this register should only be modified when the hcha lted bit (d29:f0, d26:f0:caplength + 24h, bit 12) in the usb2.0_sts register is a 1. ch anging value of this register while the host controller is operating yields undefined results. it should not be reprogrammed by usb system software unless the default or bios programmed values are incorrect, or the system is restoring the register wh ile returning from a suspended state. these bits in suspend well and not reset by a d3-to-d0 warm rest or a core well reset. bit d escription 7:6 reserved ? ro. these bits are reserved for future use and should read as 00b. 5:0 frame length timing value ? r/w. each decimal value change to this register corresponds to 16 high-speed bit times. the sof cycle ti me (number of sof counter clock periods to generate a sof micro-frame length) is equal to 59488 + value in this field. the default value is decimal 32 (2 0h) that gives a sof cycle time of 60000. frame length (# 480 mhz clocks) (decimal) frame length timing value (this register) (decimal) 59488 0 59504 1 59520 2 ?? 59984 31 60000 32 ?? 60480 62
ehci controller registers (d29:f0, d26:f0) 652 datasheet 16.1.26 pwake_capport wake capability register (usb ehcid29:f0, d26:f0) address offset: 62 ? 63h attribute: r/w default value: 01ffh size: 16 bits default value: 07ffh function level reset: no this register is in the suspend power well. the intended use of this register is to establish a policy about which ports are to be used for wake events. bit positions 1? 8(d29) or 1?6(d26) in the mask correspond to a physical port implemented on the current ehci controller. a 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect/ connect or overcurrent events as wake-up ev ents. this is an in formation-only mask register. the bits in this register do not affect the actual operation of the ehci host controller. the system-specific policy can be established by bios initializing this register to a system-specific value. system software uses the information in this register when enabling devices and ports for remote wake-up. these bits are not reset by a d3-to- d0 warm rest or a core well reset. bit d escription 15:9 (d29) 15:7 (d26) reserved. 8:1 (d29) 6:1 (d26) port wake up capability mask ? r/w. bit positions 1 through 8 (device 29) or 1 through 6(device 26) correspond to a ph ysical port implemen ted on this host controller. for example, bi t position 1 corresponds to port 1, bit position 2 corresponds to port 2, etc. 0 port wake implemented ? r/w. a 1 in this bit indica tes that this register is implemented to software.
datasheet 653 ehci controller registers (d29:f0, d26:f0) 16.1.27 leg_ext_capusb ehci legacy support extended capability register (u sb ehcid29:f0, d26:f0) address offset: 68 ? 6bh attribute: r/w, ro default value: 00000001h size: 32 bits power well: suspend function level reset: no note: these bits are not reset by a d3-to-d0 warm rest or a core well reset. bit d escription 31:25 reserved ? ro. hardwired to 00h 24 hc os owned semaphore ? r/w. system software sets this bit to request ownership of the ehci controller. ownership is obtained when this bit reads as 1 and the hc bios owned semaphore bit reads as clear. 23:17 reserved ? ro. hardwired to 00h 16 hc bios owned semaphore ? r/w. the bios sets this bit to establish ownership of the ehci controller. system bios will clea r this bit in response to a request for ownership of the ehci contro ller by system software. 15:8 next ehci capability pointer ? ro. hardwired to 00h to indicate that there are no ehci extended capability st ructures in this device. 7:0 capability id ? ro. hardwired to 01h to indicate th at this ehci extended capability is the legacy support capability.
ehci controller registers (d29:f0, d26:f0) 654 datasheet 16.1.28 leg_ext_csusb ehci legacy support extended control / status register (usb ehcid29:f0, d26:f0) address offset: 6c ? 6fh attribute: r/w, r/wc, ro default value: 00000000h size: 32 bits power well: suspend function level reset: no note: these bits are not reset by a d3-to- d0 warm rest or a core well reset. bit de scription 31 smi on bar ? r/wc. software clears this bit by writing a 1 to it. 0 = base address regist er (bar) not written. 1 = this bit is set to 1 when the base address register (bar) is written. 30 smi on pci command ? r/wc. software clears this bit by writing a 1 to it. 0 = pci command (pcicmd) register not written. 1 = this bit is set to 1 when the pci command (pcicmd) re gister is written. 29 smi on os ownership change ? r/wc. software clears this bit by writing a 1 to it. 0 = no hc os owned semaphore bit change. 1 = this bit is set to 1 when the hc os owned semaphore bit in the leg_ext_cap register (d29:f0, d26:f0:68h, bit 24) transitions from 1 to 0 or 0 to 1. 28:22 reserved. 21 smi on async advance ? ro. this bit is a shadow bit of the interrupt on async advance bit (d29:f0, d26:f0:caplength + 24 h, bit 5) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the interrupt on async advance bit in the usb2.0_sts register. 20 smi on host system error ? ro. this bit is a shadow bit of host system error bit in the usb2.0_sts register (d29:f0, d26:f0:caplength + 24h, bit 4). note: to clear this bit system so ftware must write a 1 to th e host system error bit in the usb2.0_sts register. 19 smi on frame list rollover ? ro. this bit is a shadow bit of frame list rollover bit (d29:f0, d26:f0:caplength + 24h, bi t 3) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the frame list rollover bit in the usb2.0_sts register. 18 smi on port change detect ? ro. this bit is a shadow bi t of port chan ge detect bit (d29:f0, d26:f0:caplength + 24h, bi t 2) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the port change detect bit in the usb2.0_sts register. 17 smi on usb error ? ro. this bit is a shadow bit of usb error interrupt (usberrint) bit (d29:f0, d26:f0:caplength + 24h, bit 1) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the usb error interrupt bit in the usb2.0_sts register. 16 smi on usb complete ? ro. this bit is a shadow bit of usb interrupt (usbint) bit (d29:f0, d26:f0:caplength + 24h, bi t 0) in the usb2.0_sts register. note: to clear this bit system so ftware must write a 1 to th e usb interrupt bit in the usb2.0_sts register.
datasheet 655 ehci controller registers (d29:f0, d26:f0) 15 smi on bar enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on bar (d29:f0, d26:f0:6ch, bit 31) is 1, then the host controller will issue an smi. 14 smi on pci command enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on pci command (d29:f0, d26:f0:6ch, bit 30) is 1, then the host cont roller will issue an smi. 13 smi on os ownership enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1 and the os ownership change bit (d29:f0, d26:f0:6ch, bit 29) is 1, the host controller will issue an smi. 12:6 reserved 5 smi on async advance enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on as ync advance bit (d29:f0, d26:f0:6ch, bit 21) is a 1, the host co ntroller will issue an smi immediately. 4 smi on host system error enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on host system error (d29:f0, d26:f0:6ch, bit 20) is a 1, the ho st controller will issue an smi. 3 smi on frame list rollover enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on frame list rollover bit (d29:f0, d26:f0:6ch, bit 19) is a 1, the ho st controller will issue an smi. 2 smi on port change enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on port change detect bit (d29:f0, d26:f0:6ch, bit 18) is a 1, the ho st controller will issue an smi. 1 smi on usb error enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on usb error bit (d29:f0, d26:f0:6ch, bit 17) is a 1, the host controller will issue an smi immediately. 0 smi on usb complete enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on usb complete bit (d29:f0, d26:f0:6ch, bit 16) is a 1, the host co ntroller will issue an smi immediately. bit d escription
ehci controller registers (d29:f0, d26:f0) 656 datasheet 16.1.29 special_smiintel spec ific usb 2.0 smi register (usb ehcid29:f0, d26:f0) address offset: 70h ? 73h attribute: r/w, r/wc default value: 00000000h size: 32 bits power well: suspend function level reset: no note: these bits are not reset by a d3-to- d0 warm rest or a core well reset. bit d escription 31:25 reserved. 24:22 smi on portowner ? r/wc. software clears these bits by writing a 1 to it. 0 = no port owner bit change. 1 = bits 24:22 correspond to the port owner bits for ports 0 (22) through 3 (24). these bits are set to 1 when the associated port owner bits transition from 0 to 1 or 1 to 0. 21 smi on pmcsr ? r/wc. software clears these bits by writing a 1 to it. 0 = power state bits not modified. 1 = software modified the power state bi ts in the power management control/ status (pmcsr) register (d29:f0, d26:f0:54h). 20 smi on async ? r/wc. software clears these bits by writing a 1 to it. 0 = no async schedule enable bit change 1 = async schedule enable bit tran sitioned from 1 to 0 or 0 to 1. 19 smi on periodic ? r/wc. software clears this bit by writing a 1 it. 0 = no periodic schedule enable bit change. 1 = periodic schedule enable bit tr ansitions from 1 to 0 or 0 to 1. 18 smi on cf ? r/wc. software clears this bit by writing a 1 it. 0 = no configure flag (cf) change. 1 = configure flag (cf) transitions from 1 to 0 or 0 to 1. 17 smi on hchalted ? r/wc. software clears this bit by writing a 1 it. 0 = hchalted did not transition to 1 (a s a result of the run/stop bit being cleared). 1 = hchalted transitions to 1 (as a result of the run/stop bit being cleared). 16 smi on hcreset ? r/wc. software clears th is bit by writing a 1 it. 0 = hcreset did not transitioned to 1. 1 = hcreset transitioned to 1. 15:14 reserved 13:6 smi on portowner enable ? r/w. 0 = disable. 1 = enable. when any of these bits are 1 and the corresponding smi on portowner bits are 1, then the host co ntroller will issue an smi. unused ports should have their corresponding bits cleared. 5 smi on pmscr enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on pmscr is 1, then the host controller will issue an smi. 4 smi on async enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on async is 1, then the host controller will issue an smi
datasheet 657 ehci controller registers (d29:f0, d26:f0) 16.1.30 access_cntlacce ss control register (usb ehcid29:f0, d26:f0) address offset: 80h attribute: r/w default value: 00h size: 8 bits function level reset: no 3 smi on periodic enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on periodic is 1, then the host controller will issue an smi. 2 smi on cf enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on cf is 1, then the host controller will issue an smi. 1 smi on hchalted enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1 and smi on hchalted is 1, then the host controller will issue an smi. 0 smi on hcreset enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1 and smi on hcreset is 1, then host controller will issue an smi. bit de scription bit d escription 7:1 reserved 0 wrt_rdonly ? r/w. when set to 1, this bit enables a select group of normally read-only registers in the ehc function to be written by soft ware. registers that may only be written when this mode is entered are noted in the summary tables and detailed description as ?read/write- special?. the registers fall into two categories: 1. system-configured parameters 2. status bits
ehci controller registers (d29:f0, d26:f0) 658 datasheet 16.1.31 ehciir1ehci init ialization register 1 (usb ehcid29:f0, d26:f0) address offset: 84h attribute: r/w default value: 01h size: 32 bits 16.1.32 ehciir2ehci initializa tion register 2 (usb ehci d29:f0, d26:f0) offset address: 88h?8bh attribute: r/w default value: 04000010h size: 32-bit bit de scription 31:29 reserved 28 ehci prefetch entry clear ? r/w. 0 = ehc will clear prefetched entries in dma. 1 = ehc will not clear prefetched entries in dma 27:19 reserved 18 ehci initialization register 1 field 2 ? r/w. bios must set this bit to 1. 17:11 reserved 10:9 ehci initialization register 1 field 1 ? r/w. bios must set this field to 11. 8:5 reserved 4 intel ? pre-fetch based pause enable ? r/w. 0 = intel pre-fetch based pause is disabled. 1 = intel pre-fetch based pause is enabled. 3:0 reserved bit de scription 31:30 reserved 29 ehci initialization register 2 field 6 ? r/w. bios must set this bit to 0. 28:20 reserved 19 ehci initialization register 2 field 5 ? r/w. bios must set this bit to 1. 18:12 reserved 11 ehci initialization register 2 field 4 ? r/w. bios must set this bit to 1. 10 ehci initialization register 2 field 3 ? r/w. bios must set this bit to 1. 9 reserved 8 ehci initialization register 2 field 2 ? r/w. bios must set this bit to 1.
datasheet 659 ehci controller registers (d29:f0, d26:f0) 16.1.33 flr_cidfunction level reset capability id register (usb ehcid29:f0, d26:f0) address offset: 98h attribute: ro default value: 09h size: 8 bits function level reset: no 16.1.34 flr_nextfunction le vel reset next capability pointer register (usb ehcid29:f0, d26:f0) address offset: 99h attribute: ro default value: 00h size: 8 bits function level reset: no 7:6 reserved 5 ehci initialization register 2 field 1 ? r/w. bios must set this bit to 1. 4:0 reserved bit d escription bit d escription 7:0 capability id ? ro. 13h = if flrcssel = 0 09h (vendor specific capability) = if flrcssel = 1 bit d escription 7:0 a value of 00h in this register indi cates this is the last capability field.
ehci controller registers (d29:f0, d26:f0) 660 datasheet 16.1.35 flr_clvfunction level reset capability length and version register (usb ehcid29:f0, d26:f0) address offset: 9ah?9bh attribute: r/wo, ro default value: 2006h size: 16 bits function level reset: no when flrcssel = 0, this register is defined as follows: when flrcssel = 1, this register is defined as follows: 16.1.36 flr_ctrlfunction le vel reset control register (usb ehcid29:f0, d26:f0) address offset: 9ch attribute: r/w default value: 00h size: 8 bits function level reset: no bit de scription 15:10 reserved 9 flr capability ? r/wo. 1 = support for function level reset (flr). 8 txp capability ? r/wo. 1 = support for transactions pending (txp) bit. txp must be supported if flr is supported. 7:0 capability length ? ro. this field indicates the # of bytes of this vendor specific capability as required by th e pci specification. it has the value of 06h for the flr capability. bit de scription 15:12 vendor specific capability id ? ro. a value of 2h in th is field identifies this capability as function level reset. 11:8 capability version ? ro. this field indicates the version of the flr capability. 7:0 capability length ? ro. this field indicates the # of bytes of this vendor specific capability as required by th e pci specification. it has the value of 06h for the flr capability. bit de scription 7:1 reserved 0 initiate flr ? r/w. this bit is used to initiate flr transition. a writ e of 1 initiates flr transition. since hardware must not respond to any cycles until flr completion, the value read by software from this bit is always 0.
datasheet 661 ehci controller registers (d29:f0, d26:f0) 16.1.37 flr_stsfunction le vel reset status register (usb ehcid29:f0, d26:f0) address offset: 9dh attribute: ro default value: 00h size: 8 bits function level reset: no 16.1.38 ehciir3ehci initializat ion register 3 (usb ehci d29:f0, d26:f0) offset address: f4h?f7h attribute: r/w default value: 00408588h size: 32-bit 16.1.39 ehciir4ehci initializat ion register 4 (usb ehci d29:f0, d26:f0) offset address: fch?ffh attribute: r/w default value: 20591708h size: 32-bit bit d escription 7:1 reserved 0 transactions pending (txp) ? ro. 0 = completions for all non-posted requests have been received. 1 = controller has issued non-posted re quests which have no bee completed. bit d escription 31 ehciir3 write enable ? r/w. 0 = writes to the ehciir3 register are disabled 1 = if set, the values of the ehciir3 register may be modified 30:24 reserved 23:22 ehci initialization register 3 field 1 ? r/w. bios must program this field to 10b. 21:0 reserved bit d escription 31:18 reserved 17 ehci initialization register 4 field 2 ? r/w. bios must set this bit to 1. 16 reserved 15 ehci initialization register 4 field 1 ? r/w. bios must set this bit to 1. 14:0 reserved
ehci controller registers (d29:f0, d26:f0) 662 datasheet 16.2 memory-mapped i/o registers the ehci memory-mapped i/o space is compos ed of two sets of registers?capability registers and operational registers. note: the pch ehci controller will not accept memory transactions (neither reads nor writes) as a target that are locked transactions. the locked transactions should not be forwarded to pci as the address space is known to be allocated to usb. note: when the ehci function is in the d3 pci power state, accesses to the usb 2.0 memory range are ignored and result a master abort. similarly, if the memory space enable (mse) bit (d29:f0, d26:f0:04h, bit 1) is not set in the command register in configuration space, the memory range will not be decoded by the pch enhanced host controller (ehc). if the mse bit is not se t, the pch must default to allowing any memory accesses for the range specified in th e bar to go to pci. this is because the range may not be valid and, therefore, the cycle must be made available to any other targets that may be currently using that range. 16.2.1 host controller capability registers these registers specify the limits, restrictions and capabilities of the host controller implementation. within the host controller capability registers, only the structural parameters register is writable. these registers are implemented in the suspend well and is only reset by the standard suspend- well hardware reset, not by hcreset or the d3-to-d0 reset. note: note that the ehci controller does not support as a target memory transactions that are locked transactions. attempting to access the ehci controller memory-mapped i/o space using locked memory transactions will result in undefined behavior. note: note that when the usb2 function is in th e d3 pci power state, accesses to the usb2 memory range are ignored and will result in a master abort. similarly, if the memory space enable (mse) bit is not set in the co mmand register in configuration space, the memory range will not be decoded by the e nhanced host controller (ehc). if the mse bit is not set, the ehc will not claim any memory accesses for the range specified in the bar. note: ?read/write special? means that the register is normally read-only, but may be written when the wrt_rdonly bit is set. because these registers are expected to be programmed by bios during initialization, their contents must not get modified by hcreset or d3-to- d0 internal reset. table 16-2. enhanced host cont roller capability registers mem_base + offset mnemonic register de fault attribute 00h caplength capabilities registers length 20h ro 02h?03h hciversion host controller interface version number 0100h ro 04h?07h hcsparams host controller structural parameters 00204208h (d29:f0) 00203206 (d26:f0) r/w (special), ro 08h?0bh hccparams host controller capability parameters 00006881h ro
datasheet 663 ehci controller registers (d29:f0, d26:f0) 16.2.1.1 caplengthcapability registers length register offset: mem_base + 00h attribute: ro default value: 20h size: 8 bits 16.2.1.2 hciversionhost contro ller interface version number register offset: mem_base + 02h ? 03h attribute: ro default value: 0100h size: 16 bits 16.2.1.3 hcsparamshost controller structural parameters register offset: mem_base + 04h ? 07h attribute: r/w, ro default value: 00204208h (d29:f0) size: 32 bits 00203206h (d26:f0) function level reset: no note: this register is reset by a suspend well reset and not a d3-to-d0 reset or hcreset. note: this register is writable when the wrt_rdonly bit is set. bit d escription 7:0 capability register length value ? ro. this register is used as an offset to add to the memory base register (d29:f0, d26: f0:10h) to find the beginning of the operational register space. this field is ha rdwired to 20h indicating that the operation registers begin at offset 20h. bit d escription 15:0 host controller interface version number ? ro. this is a two-byte register containing a bcd encoding of the version numbe r of interface that th is host controller interface conforms. bit d escription 31:24 reserved 23:20 debug port number (dp_n) ? ro. hardwired to 2h indicating that the debug port is on the second lowest numb ered port on the ehci. ehci#1: port 1 ehci#2: port 9 19:16 reserved 15:12 number of companion controllers (n_cc) ? r/w. this field indicates the number of companion controllers associated with this usb ehci host controller. bios must program this field to 0b to in dicate companion host controllers are not supported. port-ownership hand-off is not supported. only high-speed devices are supported on the host controller root ports. 11:8 number of ports per comp anion controller (n_pcc) ? ro. this field indicates the number of ports supported per companion host co ntroller. this field is 0h indication no other companion controller support. 7:4 reserved. these bits are reserved and default to 0. 3:0 n_ports ? r/w. this field specifies the number of physical downstream ports implemented on this host controller. the valu e of this field determines how many port registers are addressable in the operational register space. valid values are in the range of 1h to fh. a 0 in this field is undefined. for integrated usb 2.0 rate matching hub enabled: each ehci reports 2 ports by default. port 0 assigned to the rmh and po rt 1 assigned as the debug port. when the kvm/usb-r feature is enabled it will show up as port2 on the ehci, and bios would need to update this field to 3h.
ehci controller registers (d29:f0, d26:f0) 664 datasheet 16.2.1.4 hccparamshost controller capability parameters register offset: mem_base + 08h ? 0bh attribute: ro default value: 00006881h size: 32 bits bit de scription 31:18 reserved 17 asynchronous schedule update capability (asuc) ? r/w. there is no functionality associated with this bit. 16 periodic schedule update capability (psuc) ? ro. this field is hardwired to 0b to indicate that the ehc hardware supports the pe riodic schedule update event flag in the usb2.0_cmd register. 15:8 ehci extended capabili ties pointer (eecp) ? ro. this field is hardwired to 68h, indicating that the ehci capa bilities list exists and begins at offset 68h in the pci configuration space. 7:4 isochronous scheduling threshold ? ro. this field indicates, relative to the current position of the executing host contro ller, where software can reliably update the isochronous schedule. wh en bit 7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller hold a set of isochronous data structures (one or more) before fl ushing the state. when bit 7 is a 1, then host software assumes the host controller may cache an isochronous data structure for an entire frame. refer to the ehci specification for details on how software uses this information for scheduling isochronous transfers. this field is hardwired to 8h. 3 reserved 2 asynchronous schedule park capability ? ro. this bit is hardwired to 0 indicating that the host controller does no t support this optional feature 1 programmable frame list flag ? ro. 0 = system software must use a frame list length of 1024 elements with this host controller. the usb2.0_cmd register (d 29:f0, d26:f0:caplength + 20h, bits 3:2) frame list size field is a read-only regist er and must be set to 0. 1 = system software can specify and use a sm aller frame list and configure the host controller using the usb2.0_cmd register frame list size field. the frame list must always be aligned on a 4k page boundary . this requirement en sures that the frame list is always physically contiguous. 0 64-bit addressing capability ? ro. this field documents the addressing range capability of this implementation. the value of this field determin es whether software should use the 32-bit or 64-bit data structures. this bit is hardwired to 1. note: the pch supports 64 bit addressing only.
datasheet 665 ehci controller registers (d29:f0, d26:f0) 16.2.2 host controller operational registers this section defines the enhanced host controller operational registers. these registers are located after the capabilities registers. the operational register base must be dword-aligned and is calculated by adding the value in the first capabilities register (caplength) to the base address of the enhanced host controller register address space (mem_base). since caplength is always 20h, table 16-3 already accounts for this offset. all registers are 32 bits in length. note: software must read and write these registers using only dword accesses.these registers are divided into two sets. the fi rst set at offsets mem_base + 00:3bh are implemented in the core powe r well. unless otherwise noted, the core well registers are reset by the assertion of any of the following: ? core well hardware reset ? hcreset ? d3-to-d0 reset table 16-3. enhanced host controlle r operational register address map mem_base + offset mnemonic register name default special notes attribute 20h?23h usb2.0_cmd usb 2.0 command 00080000h r/w, ro 24h?27h usb2.0_sts usb 2.0 status 00001000h r/wc, ro 28h?2bh usb2.0_intr usb 2.0 in terrupt enable 00000000h r/w 2ch?2fh frindex usb 2.0 frame index 00000000h r/w 30h?33h ctrldssegment control data structure segment 00000000h r/w, ro 34h?37h perodiclistbase period frame list base address 00000000h r/w 38h?3bh asynclistaddr curre nt asynchronous list address 00000000h r/w 3ch?5fh ? reserved 0h ro 60h?63h configflag configure flag 00000000h suspend r/w 64h?67h port0sc port 0 status and control 00003000h suspend r/w, r/wc, ro 68h?6bh port1sc port 1 status and control 00003000h suspend r/w, r/wc, ro 6ch?6fh port2sc port 2 status and control 00003000h suspend r/w, r/wc, ro 70h?73h port3sc port 3 status and control 00003000h suspend r/w, r/wc, ro 74h?77h port4sc port 4 status and control 00003000h suspend r/w, r/wc, ro 78h?7bh port5sc port 5 status and control 00003000h suspend r/w, r/wc, ro 74h?77h (d29 only) port6sc port 6 status and control 00003000h suspend r/w, r/wc, ro 78h?7bh (d29 only) port7sc port 7 status and control 00003000h suspend r/w, r/wc, ro 7ch?9fh ? reserved undefined ro a0h?b3h ? debug port registers undefined see register description b4h?3ffh ? reserved undefined ro
ehci controller registers (d29:f0, d26:f0) 666 datasheet the second set at offsets mem_base + 60h to the end of the implemented register space are implemented in the suspend po wer well. unless otherwise noted, the suspend well registers are reset by the assertion of either of the following: ? suspend well hardware reset ? hcreset 16.2.2.1 usb2.0_cmdusb 2.0 command register offset: mem_base + 20?23h attribute: r/w, ro default value: 00080000h size: 32 bits bit de scription 31:24 reserved 23:16 interrupt threshold control ? r/w. system software uses this field to select the maximum rate at which the host controller wi ll issue interrupts. the only valid values are defined below. if software writes an in valid value to this re gister, the results are undefined. 15:14 reserved 13 asynch schedule update (asc) ? r/w. there is no function ality associated with this bit. 12 periodic schedule prefetch enable ? r/w. this bit is used by software to enable the host controller to prefetch the periodic schedule even in c0. 0 = pre-fetch based pause enab led only when not in c0. 1 = pre-fetch based pa use enable in c0. once software has written a 1b to this bit to enable periodic schedule prefetching, it must disable prefec thing by writing a 0b to this bit whenever periodic schedule updates are about to begin. software should contin ue to dynamically disa ble and re-e nable the prefetcher surrounding any updates to the periodic scheduler (that is, until the host controller has been reset using a hcreset). 11:8 unimplemented asynchronous park mode bits ? ro. hardwired to 000b indicating the host controller does not su pport this optional feature. 7 light host controller reset ? ro. hardwire d to 0. the pch does not implement this optional reset. value maximum interrupt interval 00h reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms)
datasheet 667 ehci controller registers (d29:f0, d26:f0) 6 interrupt on async advance doorbell ? r/w. this bit is used as a doorbell by software to tell the host controller to is sue an interrupt the ne xt time it advances asynchronous schedule. 0 = the host controller sets this bit to a 0 after it has set the interrupt on async advance status bit (d29:f0, d26:f0:caplength + 24h, bit 5) in the usb2.0_sts register to a 1. 1 = software must write a 1 to this bit to ri ng the doorbell. when the host controller has evicted all appropriate cached schedule state, it sets the interrupt on async advance status bit in the usb2.0_sts register. if the interrupt on async advance enable bit in the usb2.0_intr register (d29:f0, d26:f0:caplength + 28h, bit 5) is a 1 then the host controller will as sert an interrupt at the next interrupt threshold. see the ehci specif ication for operational details. note: software should not write a 1 to this bit when the asynchronous schedule is inactive. doing so will yield undefined results. 5 asynchronous schedule enable ? r/w. this bit controls whether the host controller skips processing the asynchronous schedule. 0 = do not process the asynchronous schedule 1 = use the asynclistaddr register to access the asynchronous schedule. 4 periodic schedule enable ? r/w. this bit controls whet her the host controller skips processing the periodic schedule. 0 = do not process the periodic schedule 1 = use the periodiclistbase register to access the periodic schedule. 3:2 frame list size ? ro. the pch hardwires this fiel d to 00b because it only supports the 1024-element frame list size. 1 host controller reset (hcreset) ? r/w. this control bit used by software to reset the host controller. the effects of this on root hub registers are similar to a chip hardware reset (that is, rs mrst# assertion and pwrok deassertion on the pch). when software writes a 1 to th is bit, the host controller re sets its internal pipelines, timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediat ely terminated. a usb reset is not driven on downstream ports. note: pci configuration registers and host controller capability registers are not effected by this reset. all operational registers, including port registers and port state machines are set to their initial values. port ownership reverts to the companion host controller(s), with the side effects described in the ehci specification. software must re-initialize the host controller in order to return the host controller to an operational state. this bit is set to 0 by the host controller when the reset process is complete. software cannot terminate the reset process earl y by writing a 0 to this register. software should not set this bit to a 1 when the hchalted bit (d29:f0, d26:f0:caplength + 24h, bit 12) in the usb2.0_sts register is a 0. attempting to reset an actively running host controller will result in undefined behavior. this reset me be used to leave eh ci port test modes. bit d escription
ehci controller registers (d29:f0, d26:f0) 668 datasheet note: the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. 0 run/stop (rs) ? r/w. 0 = stop (default) 1 = run. when set to a 1, the host controller proceeds with execution of the schedule. the host controller continues execution as lo ng as this bit is set. when this bit is set to 0, the host controller completes the current transaction on the usb and then halts. the hchalted bit in the usb2.0_s ts register indicates when the host controller has finished the transaction and has entered the stopped state. software should not write a 1 to this field un less the host controller is in the halted state (that is, hchalted in the usbsts register is a 1). the halted bit is cleared immediately when the run bit is set. the following table explains how the different combinations of run and halted should be interpreted: memory read cycles initiated by the ehc that receive any status ot her than successful will result in this bit being cleared. bit de scription run/stop halted interpretation 0b 0b in the process of halting 0b 1b halted 1b 0b running 1b 1b invalid ? the hchalted bit clears immediately
datasheet 669 ehci controller registers (d29:f0, d26:f0) 16.2.2.2 usb2.0_stsusb 2.0 status register offset: mem_base + 24h?27h attribute: r/wc, ro default value: 00001000h size: 32 bits this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. see the interrupts description in section 4 of the ehci specification for additional information concerning usb 2.0 interrupt conditions. note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 has no effect. bit description 31:16 reserved 15 asynchronous schedule status ?? ro. this bit reports the cu rrent real status of the asynchronous schedule. 0 = disabled. (default) 1 = enabled. note: the host controller is not required to immediately disable or enable the asynchronous schedule when software transitions the asynchronous schedule enable bit (d29:f0, d26:f0:caplength + 20h, bit 5) in the usb2.0_cmd register. when this bit and the asynchronous schedule enable bit are the same value, the asynchronous schedule is either enabled (1) or disabled (0). 14 periodic schedule status ?? ro. this bit reports the current re al status of the periodic schedule. 0 = disabled. (default) 1 = enabled. note: the host controller is not required to immediately disable or enable the periodic schedule when softwa re transitions the periodic schedule enable bit (d29:f0, d26:f0:caplength + 20h, bit 4) in the us b2.0_cmd register. when this bit and the periodic schedule enable bit are the same value, the periodic schedule is either enabled (1) or disabled (0). 13 reclamation ?? ro. this read-only status bit is used to detect an empty asynchronous schedule. the operational mode l and valid transitions for this bit are described in section 4 of the ehci specification. 12 hchalted ?? ro. 0 = this bit is a 0 when the run/stop bit is a 1. 1 = the host controller sets this bit to 1 afte r it has stopped executin g as a result of the run/stop bit being set to 0, either by soft ware or by the host controller hardware (such as, internal error). (default) 11:6 reserved 5 interrupt on async advance ? r/wc. system software can forc e the host controller to issue an interrupt the ne xt time the host controller advances the asynchronous schedule by writing a 1 to the interrupt on async advance doorbell bit (d29:f0, d26:f0:caplength + 20h, bit 6) in the usb2.0_cmd register. this bit indicates the assertion of that interrupt source.
ehci controller registers (d29:f0, d26:f0) 670 datasheet 4 host system error ? r/wc. 0 = no serious error occurred during a host sy stem access involving the host controller module 1 = the host controller sets this bit to 1 when a serious error oc curs during a host system access involving the host contro ller module. a hardware interrupt is generated to the system. memory read cycles initiated by the ehc that receive any status other than successful will result in this bit being set. when this error occurs, th e host controller clears the run/stop bit in the usb2.0_cmdregister (d29:f0, d26:f0:caplength + 20h, bit 0) to prevent further execution of the scheduled tds. a hardware interrupt is generate d to the system (if enabled in the interrupt enable register). 3 frame list rollover ? r/wc. 0 = no frame list index rollover from its maximum value to 0. 1 = the host controller sets this bit to a 1 when the frame list index rolls over from its maximum value to 0. since the pch only supports the 1024-entry frame list size, the frame list index rolls over every time frnum13 toggles. 2 port change detect ? r/wc. this bit is allowed to be maintained in the auxiliary power well. alternatively, it is also acceptable that on a d3 to d0 transition of the ehci hc device, this bit is loaded with the or of all of the portsc change bits (including: force port resume, overcurre nt change, enable/disable change and connect status change). regardless of the implementation, when this bit is readable (that is, in the d0 state), it must provide a valid vi ew of the port status registers. 0 = no change bit transition from a 0 to 1 or no force port resume bit transition from 0 to 1 as a result of a j-k transiti on detected on a suspended port. 1 = the host controller sets this bi t to 1 when any port for which the port owner bit is set to 0 has a change bit transition fro m a 0 to 1 or a force port resume bit transition from 0 to 1 as a result of a j- k transition detected on a suspended port. 1 usb error interrupt (usberrint) ? r/wc. 0 = no error condition. 1 = the host controller sets this bit to 1 when completion of a usb transaction results in an error condition (such as, error counter underflow). if the td on which the error interrupt occurred also had its ioc bit set, both this bit and bit 0 are set. see the ehci specification for a list of the usb errors that will result in this interrupt being asserted. 0 usb interrupt (usbint) ? r/wc. 0 = no completion of a usb transaction whose transfer descriptor had its ioc bit set. no short packet is detected. 1 = the host controller sets this bit to 1 when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. the host controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less th an the expected number of bytes). bit description
datasheet 671 ehci controller registers (d29:f0, d26:f0) 16.2.2.3 usb2.0_intrusb 2.0 interrupt enable register offset: mem_base + 28h?2bh attribute: r/w default value: 00000000h size: 32 bits this register enables and disables report ing of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. interrupt sources that ar e disabled in this register still appear in the usb2.0_sts register to allow the software to poll for events. each interrupt enable bit description indicates whether it is depe ndent on the interrupt threshold mechanism (see section 4 of the ehci specification), or not. bit d escription 31:6 reserved 5 interrupt on async advance enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and th e interrupt on async advance bit (d29:f0, d26:f0:caplength + 24h, bit 5) in the usb2.0_sts register is a 1, the host controller will issue an interrupt at the next interrupt threshol d. the interrupt is acknowledged by software clearing the interrupt on async advance bit. 4 host system error enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and th e host system error status bit (d29:f0, d26:f0:caplength + 24h, bit 4) in the usb2.0_sts register is a 1, the host controller will issue an interrupt. the inte rrupt is acknowledged by software clearing the host system error bit. 3 frame list rollover enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the frame list rollover bit (d29:f0, d26:f0:caplength + 24h, bit 3) in the usb2.0_sts register is a 1, the host controller will issue an interrupt. the inte rrupt is acknowledged by software clearing the frame list rollover bit. 2 port change interrupt enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the port chan ge detect bit (d29:f0, d26:f0:caplength + 24h, bit 2) in the usb2.0_sts register is a 1, the host controller will issue an interrupt. the inte rrupt is acknowledged by software clearing the port change detect bit. 1 usb error interrupt enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and th e usberrint bit (d29:f0, d26:f0:caplength + 24h, bit 1) in the usb2.0_s ts register is a 1, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software by clearing the usberrint bit in the usb2.0_sts register. 0 usb interrupt enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and th e usbint bit (d29:f0, d26:f0:caplength + 24h, bit 0) in the usb2.0_sts register is a 1, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software by clearing the usbint bit in the usb2.0_sts register.
ehci controller registers (d29:f0, d26:f0) 672 datasheet 16.2.2.4 frindexframe index register offset: mem_base + 2ch?2fh attribute: r/w default value: 00000000h size: 32 bits the sof frame number value for the bus sof token is derived or alternatively managed from this register. refer to section 4 of the ehci specification for a detailed explanation of the sof value management requirements on the host controller. the value of frindex must be within 125 s (1 micro-fr ame) ahead of the sof token value. the sof value may be implemented as an 11-bit shadow register. for this discussion, this shadow register is 11 bits and is named sofv. sofv updates every 8 micro-frames (1 millisecond). an example implementation to achieve this behavior is to increment sofv each time the frindex[2:0] increments from 0 to 1. software must use the value of frindex to derive the current micro-frame number, both for high-speed isochronous sche duling purposes and to provide the get micro- frame number function required to client dr ivers. therefore, the value of frindex and the value of sofv must be kept consistent if chip is reset or software writes to frindex. writes to frindex must also write-through frindex[13:3] to sofv[10:0]. in order to keep the update as simple as possible, software should never write a frindex value where the three least significant bits are 111b or 000b. note: this register is used by the host controller to index into the periodic frame list. the register updates every 125 microseconds (once each micro-frame). bits [12:3] are used to select a particular entry in the pe riodic frame list during periodic schedule execution. the number of bits used for the index is fixed at 10 for the pch since it only supports 1024-entry frame lists. this register must be written as a dword. word and byte writes produce undefined results. this register cannot be written unless the host controller is in the halted state as indicated by the hchalted bit (d29:f0, d26:f0:caplength + 24h, bit 12). a write to this register while the run/stop bit (d29:f0, d26:f0:caplength + 20h, bit 0) is set to a 1 (usb2.0_cmd register) produces undefined results. writes to this register also effect the sof value. see section 4 of the ehci specification for details. bit de scription 31:14 reserved 13:0 frame list current index/frame number ? r/w. the value in this register increments at the end of each time frame (such as, micro-frame). bits [12:3] are used for the fr ame list current inde x. this means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index.
datasheet 673 ehci controller registers (d29:f0, d26:f0) 16.2.2.5 ctrldssegmentcontro l data structure segment register offset: mem_base + 30h?33h attribute: r/w, ro default value: 00000000h size: 32 bits this 32-bit register corresponds to the most significant address bits [63:32] for all ehci data structures. since the pch hardwire s the 64-bit addressing capability field in hccparams to 1, this register is used with the link pointers to construct 64-bit addresses to ehci control data structures. this register is concatenated with the link pointer from either the periodiclistb ase, asynclistaddr, or any control data structure link field to construct a 64-bit address. this register allows the host software to locate all control data structures within the same 4 gb memory segment. 16.2.2.6 periodiclistbaseperio dic frame list base address register offset: mem_base + 34h?37h attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains the beginning address of the periodic frame list in the system memory. since the pch host controller operates in 64-bit mode (as indicated by the 1 in the 64-bit addressing capability fi eld in the hccsparams register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register. hcd load s this register prior to starting the schedule execution by the host controller. the memory structure referenced by this physical memory pointer is assumed to be 4-kbyte aligned. the contents of this register are combined with the frame inde x register (frindex) to enable the host controller to step through the periodic frame list in sequence. bit d escription 31:12 upper address[63:44] ? ro. hardwired to 0s. the pch ehc is only capable of generating addresses up to 16 terabytes (44 bits of address). 11:0 upper address[43:32] ? r/w. this 12-bit field corr esponds to address bits 43:32 when forming a control data structure address. bit description 31:12 base address (low) ? r/w. these bits correspon d to memory address signals [31:12], respectively. 11:0 reserved
ehci controller registers (d29:f0, d26:f0) 674 datasheet 16.2.2.7 asynclistaddrcurrent asynchronous list address register offset: mem_base + 38h?3bh attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains the address of the next asynchronous queue head to be executed. since the pch host controller operat es in 64-bit mode (as indicated by a 1 in 64-bit addressing capability field in the hccparams register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register (offset 08h). bits [4:0] of this register cannot be modified by system software and will always return 0s when read. the memory structure referenced by this physical memory poin ter is assumed to be 32-byte aligned. 16.2.2.8 configflagconfigure flag register offset: mem_base + 60h?63h attribute: r/w default value: 00000000h size: 32 bits this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. bit description 31:5 link pointer low (lpl) ? r/w. these bits correspond to memory address signals [31:5], respectively. this field may only reference a queue head (qh). 4:0 reserved bit de scription 31:1 reserved 0 configure flag (cf) ? r/w. host software sets this bit as the last action in its process of configuring the host controller. this bit co ntrols the default port-routing control logic. bit values and side-effects are listed below. see chapter 4 of the ehci specification for operation details. 0 = compatibility debug only (default). 1 = port routing control logic default-rout es all ports to this host controller.
datasheet 675 ehci controller registers (d29:f0, d26:f0) 16.2.2.9 portscport n status and control register offset: port 0 rmh: mem_base + 64h ? 67h port 1 debug port: mem_base + 68 ? 6bh port 2 usb redirect (if enabled): mem_base + 6c ? 6fh attribute: r/w, r/wc, ro default value: 00003000h size: 32 bits note: this register is associated with the upstre am ports of the ehci controller and does not represent downstream hub ports. usb hub cl ass commands must be used to determine rmh port status and enable test modes. see chapter 11 of the usb specification, revision 2.0 for more details. rate matching hub wake capabilities can be configured by the rmhwkctl register (rcba+35b0h) located in the chipset configuration chapter. a host controller must implement one or more port registers. software uses the n_port information from the structural parameters register to determine how many ports need to be serviced. all ports have the structure defined below. software must not write to unreported port status and control registers. this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in resp onse to a host controller reset. the initial conditions of a port are: ? no device connected ?port disabled. when a device is attached, the port state transitions to the attached state and system software will process this as with any status change notification. refer to section 4 of the ehci specification for operational requirem ents for how change events interact with port suspend mode. bit d escription 31:23 reserved 22 wake on overcurrent enable (wkoc_e) ? r/w. 0 = disable. (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the overcurrent active bit (bit 4 of this register) is set. 21 wake on disconnect enable (wkdscnnt_e) ? r/w. 0 = disable. (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15 ) when the current connect status changes from connecte d to disconnected (that is , bit 0 of this register changes from 1 to 0). 20 wake on connect enable (wkcnnt_e) ? r/w. 0 = disable. (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15 ) when the current connect status changes from disconnected to connected (that is, bit 0 of this register changes from 0 to 1).
ehci controller registers (d29:f0, d26:f0) 676 datasheet 19:16 port test control ? r/w. when this field is 0s, the port is not operating in a test mode. a non-zero value indicates that it is op erating in test mode and the specific test mode is indicated by the specific value. the encoding of the test mode bits are (0110b ? 1111b are reserved): refer to the usb specification revision 2.0, chapter 7 for details on each test mode. 15:14 reserved 13 port owner ? r/w. this bit unconditionally goes to a 0 when the configured flag bit in the usb2.0_cmd register makes a 0 to 1 transition. system software uses this fi eld to release ownership of the port to a selected host controller (in the event that the attached de vice is not a high-spe ed device). software writes a 1 to this bit when the attached device is not a high-speed de vice. a 1 in this bit means that a companion host co ntroller owns and controls the port. see section 4 of the ehci specification for operational details. 12 port power (pp) ? ro. read-only with a value of 1. this indicates that the port does have power. 11:10 line status ? ro.these bits reflect the current logical levels of the d+ (bit 11) and d? (bit 10) signal lines. these bits are used fo r detection of low-speed usb devices prior to the port reset and enable sequen ce. this field is valid only wh en the port enable bit is 0 and the current connect status bit is set to a 1. 00 = se0 10 = j-state 01 = k-state 11 = undefined 9 reserved bit de scription value maximum interrupt interval 0000b test mode not enabled (default) 0001b test j_state 0010b test k_state 0011b test se0_nak 0100b test packet 0101b force_enable
datasheet 677 ehci controller registers (d29:f0, d26:f0) 19:16 port test control ? r/w. when this field is 0s, the port is not operating in a test mode. a non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. the encoding of the test mode bits are (0110b ? 1111b are reserved): refer to the usb specification revision 2.0, chapter 7 for details on each test mode. 15:14 reserved 13 port owner ? r/w. this bit unconditionally goes to a 0 when the configured flag bit in the usb2.0_cmd register makes a 0 to 1 transition. system software uses this field to release ownership of the port to a selected host controller (in the event that the attached de vice is not a high-speed device). software writes a 1 to this bit when the attached device is not a high-speed de vice. a 1 in this bit means that a companion host controller owns and controls the port. see section 4 of the ehci specification for operational details. 12 port power (pp) ? ro. read-only with a value of 1. this indicates that the port does have power. 11:10 line status ? ro.these bits reflect the current logical levels of the d+ (bit 11) and d? (bit 10) signal lines. these bits are used fo r detection of low-spee d usb devices prior to the port reset and enable sequence. this field is valid only when the port enable bit is 0 and the current connect stat us bit is set to a 1. 00 = se0 10 = j-state 01 = k-state 11 = undefined 9 reserved bit d escription value maximum interrupt interval 0000b test mode not enabled (default) 0001b test j_state 0010b test k_state 0011b test se0_nak 0100b test packet 0101b force_enable
ehci controller registers (d29:f0, d26:f0) 678 datasheet 8 port reset ? r/w. when software writes a 1 to this bit (from a 0), the bus reset sequence as defined in the usb specification, revision 2.0 is started. software writes a 0 to this bit to terminate the bus reset sequence. software must keep this bit at a 1 long enough to ensure the reset sequence completes as specified in the usb specification, revision 2.0. 1 = port is in reset. 0 = port is not in reset. note: when software writes a 0 to this bit, there may be a delay before the bit status changes to a 0. the bit status will no t read as a 0 until after the reset has completed. if the port is in high-speed mode after re set is complete, the host controller will automatically enable this port (such as, set the port enable bit to a 1). a host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from 0 to 1. for example: if the port de tects that the attached device is high-speed during reset, then the host controller must ha ve the port in the enabled state within 2 ms of software writing this bit to a 0. the hchalted bit (d29:f0, d26:f0:caplength + 24h, bit 12) in the usb2.0_sts register should be a 0 before software attempts to use this bit. the host controller may hold port reset asserted to a 1 when the hchalted bit is a 1. this bit is 0 if port power is 0 note: system software should not attempt to reset a port if the hchalted bit in the usb2.0_sts register is a 1. doing so will result in undefined behavior. 7 suspend ? r/w. 0 = port not in suspend state.(default) 1 = port in suspend state. port enabled bit and suspend bit of this re gister define the port states as follows: when in suspend state, downst ream propagation of data is blocked on this port, except for port reset. note that the bit status does not change unt il the port is suspended and that there may be a delay in suspending a po rt depending on the ac tivity on the port. the host controller will unconditionally se t this bit to a 0 when software sets the force port resume bit to a 0 (from a 1). a write of 0 to this bit is ignored by the host controller. if host software sets this bit to a 1 when the port is not enabled (that is, port enabled bit is a 0), the result s are undefined. bit de scription port enabled suspend port state 0xd i s a b l e d 10e n a b l e d 11s u s p e n d
datasheet 679 ehci controller registers (d29:f0, d26:f0) 6 force port resume ? r/w. 0 = no resume (k-state) detected/driven on port. (default) 1 = resume detected/driven on port. software sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected while the port is in the suspend state. wh en this bit transitions to a 1 because a j-to-k transition is detected, the port change detect bit (d29:f0, d26:f0:caplength + 24h, bit 2) in the usb2.0_sts register is also set to a 1. if software sets this bit to a 1, the host controller must not set the port change detect bit. note: when the ehci controller owns the port, the resume sequence follows the defined sequence documented in the us b specification, revision 2.0. the resume signaling (full-speed 'k ') is driven on the port as long as this bit remains a 1. software must appropriately time th e resume and set this bit to a 0 when the appropriate amount of ti me has elapsed. writing a 0 (from 1) causes the port to return to high-speed mo de (forcing the bus below th e port into a high-speed idle). this bit will remain a 1 until the port has switched to the high-speed idle. 5 overcurrent change ? r/wc. the functionality of this bit is not dependent upon the port owner. software clears th is bit by writing a 1 to it. 0 = no change. (default) 1 = there is a change to overcurrent active. 4 overcurrent active ? ro. 0 = this port does not have an overcurrent condition. (default) 1 = this port currently has an overcurrent condition. this bit will automatically transition from 1 to 0 when the over current condition is removed. the pch automatically disables the port when the overcurrent active bit is 1. 3 port enable/disable change ? r/wc. for the root hub, this bit gets set to a 1 only when a port is disabled due to the appropriat e conditions existing at the eof2 point (see chapter 11 of the usb specification for the defi nition of a port error). this bit is not set due to the disabled-to-enabled transition, nor due to a disconn ect. software clears this bit by writing a 1 to it. 0 = no change in status. (default). 1 = port enabled/disabled status has changed. 2 port enabled/disabled ? r/w. ports can only be enabled by the host controller as a part of the reset and enable. so ftware cannot enable a port by writing a 1 to this bit. ports can be disabled by ei ther a fault condition (disconnect event or other fault condition) or by host software. note that th e bit status does not change until the port state actually changes. there may be a delay in disabling or enabling a port due to other host controller and bus events. 0 = disable 1 = enable (default) 1 connect status change ? r/wc. this bit indicates a ch ange has occurred in the port?s current connect status. soft ware sets this bit to 0 by writing a 1 to it. 0 = no change (default). 1 = change in current connect status. the host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. for example, the insertion status ch anges twice before system software has cleared the changed co ndition, hub hardware will be ?setting? an already-set bit (that is, the bit will remain set). 0 current connect status ? ro. this value reflects the current state of the port, and may not correspond directly to the event that caused the connect st atus change bit (bit 1) to be set. 0 = no device is present. (default) 1 = device is present on port. bit d escription
ehci controller registers (d29:f0, d26:f0) 680 datasheet 16.2.3 usb 2.0-based de bug port registers the debug port?s registers are located in the same memory area, defined by the base address register (mem_base), as the standard ehci registers. the base offset for the debug port registers (a0h) is declared in the debug port base offset capability register at configuration offset 5ah (d 29:f0, d26:f0:offset 5ah). the specific ehci port that supports this debug capability (port 1 for d29: f0 and port 9 for d26:f0) is indicated by a 4-bit field (bits 20?23) in the hcsparams register of the ehci controller. the address map of the debug port registers is shown in table 16-4 . notes: 1. all of these registers are implemented in the core well and reset by pltrst#, ehc hcreset, and a ehc d3-to-d0 transition. 2. the hardware associated with this register provides no chec ks to ensure that software programs the interface correctly. how the hardware behaves when programmed improperly is undefined. table 16-4. debug port register address map mem_base + offset mnemonic register name default attribute a0?a3h cntl_sts control/status 00000000h r/w, r/wc, ro a4?a7h usbpid usb pids 00000000h r/w, ro a8?afh databuf[7:0] data buffer (bytes 7:0) 00000000 00000000h r/w b0?b3h config configuration 00007f01h r/w
datasheet 681 ehci controller registers (d29:f0, d26:f0) 16.2.3.1 cntl_stscontrol/status register offset: mem_base + a0h attribute: r/w, r/wc, ro default value: 00000000h size: 32 bits bit description 31 reserved 30 owner_cnt r/w. 0 = ownership of the debug port is not fo rced to the ehci controller (default) 1 = ownership of the debug port is forced to the ehci controller (that is, immediately taken away from the companion classic usb host controller) if the port was already owned by the ehci controller, then setting this bit has no effect. this bit overrides all of the ownership-related bits in the standard ehci registers. 29 reserved 28 enabled_cnt r/w. 0 = software can clear this by writing a 0 to it. the hardware clears this bit for the same conditions where the port enable/disable change bit (in the portsc register) is set. (default) 1 = debug port is enabled for operation. softwa re can directly set this bit if the port is already enabled in the associated portsc register (this is enforced by the hardware). 27:17 reserved 16 done_sts r/wc. software can clear this by writing a 1 to it. 0 = request not complete 1 = set by hardware to indicate that the request is complete. 15:12 link_id_sts ro. this field identifi es the link interface. 0h = hardwired. indicates th at it is a usb debug port. 11 reserved 10 in_use_cnt r/w. set by software to indicate that the port is in use. cleared by software to indicate that th e port is free and may be used by other software. this bit is cleared after reset. (this bi t has no affect on hardware.) 9:7 exception_sts ro. this field indicates the exception when the error_good#_sts bit is set. this field should be ignored if the error_good#_sts bit is 0. 000 =no error. (default) note: this should not be seen since this field should only be checked if there is an error. 001 =transaction error: indicates the us b 2.0 transaction had an error (crc, bad pid, timeout, etc.) 010 =hardware error. request was attemp ted (or in progress) when port was suspended or reset. all other combinations are reserved 6 error_good#_sts ro. 0 = hardware clears this bit to 0 after the proper comp letion of a read or write. (default) 1 = error has occurred. details on the natu re of the error are provided in the exception field.
ehci controller registers (d29:f0, d26:f0) 682 datasheet notes: 1. software should do read-modify-write operations to this register to preserve the contents of bits not being modified. this include reserved bits. 2. to preserve the usage of reserved bits in the future, software should always write the same value read from th e bit until it is define d. reserved bits will always return 0 when read. 5 go_cnt ? r/w. 0 = hardware clears this bit when hardwa re sets the done_sts bit. (default) 1 = causes hardware to perform a read or write request. note: writing a 1 to this bit when it is alre ady set may result in undefined behavior. 4 write_read#_cnt r/w. software clears this bit to indicate that the current request is a read. software sets this bit to indicate that the current request is a write. 0 = read (default) 1 = write 3:0 data_len_cnt r/w. this field is used to indica te the size of the data to be transferred. default = 0h. for write operations, this field is set by software to indicate to the hardware how many bytes of data in data buffer are to be transferred to the console. a value of 0h indicates that a zero-length packet should be sent. a value of 1?8 indicates 1?8 bytes are to be transferred. values 9?fh are inva lid and how hardware behaves if used is undefined. for read operations, this field is set by ha rdware to indicate to software how many bytes in data buffer are valid in response to a read operation. a value of 0h indicates that a zero length packet wa s returned and the state of da ta buffer is not defined. a value of 1?8 indicates 1?8 bytes were received. hardware is not allowed to return values 9?fh. the transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the transfer size is reached. bit description
datasheet 683 ehci controller registers (d29:f0, d26:f0) 16.2.3.2 usbpidusb pids register offset: mem_base + a4h?a7h attribute: r/w, ro default value: 00000000h size: 32 bits this dword register is used to communicate pid information between the usb debug driver and the usb debug port. the debug port uses some of these fields to generate usb packets, and uses other fields to return pid information to the usb debug driver. 16.2.3.3 databuf[7:0]data buffer bytes[7:0] register offset: mem_base + a8h?afh attribute: r/w default value: 0000000000000000h size: 64 bits this register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register. 16.2.3.4 configconfiguration register offset: mem_base + b0?b3h attribute: r/w default value: 00007f01h size: 32 bits bit description 31:24 reserved 23:16 received_pid_sts[23:16] ? ro. hardware updates this field with the received pid for transactions in either direction. when the controller is writing data, this field is updated with the handshake pid that is received from the devi ce. when the host controller is reading data, this field is updated with the da ta packet pid (if the device sent data), or the handshake pid (if the devi ce naks the request). this field is valid when the hardware clears the go_done#_cnt bit. 15:8 send_pid_cnt[15:8] ? r/w. hardware sends this pid to begin the data packet when sending data to usb (that is, wr ite_read#_cnt is asserted). software typically sets this field to either data0 or data1 pid values. 7:0 token_pid_cnt[7:0] ? r/w. hardware sends this pid as the token pid for each usb transaction. software typically sets this field to either in, out, or setup pid values. bit description 63:0 databuffer[63:0] ? r/w. this field is the 8 byte s of the data buffer. bits 7:0 correspond to least significant byte (byt e 0). bits 63:56 correspond to the most significant byte (byte 7). the bytes in the data buffer mu st be written with data before software initiates a write request. for a read request, the data buffer contains va lid data when done_sts bit (offset a0, bit 16) is cleared by the hardwa re, error_good#_sts (offset a0, bit 6) is cleared by the hardware, and the data_l ength_cnt field (offset a0, bits 3:0) indicates the number of bytes that are valid. bit description 31:15 reserved 14:8 usb_address_cnf ? r/w. this 7-bit field identifies the usb device address used by the controller for all token pid generation. (default = 7fh) 7:4 reserved 3:0 usb_endpoint_cnf ? r/w. this 4-bit field identi fies the endpoint used by the controller for all token pid generation. (default = 1h)
ehci controller registers (d29:f0, d26:f0) 684 datasheet
datasheet 685 integrated intel ? high definition audio controller registers 17 integrated intel ? high definition audio controller registers 17.1 intel ? high definition audi o controller registers (d27:f0) the intel ? high definition audio controller resides in pci device 27, function 0 on bus 0. this function contains a set of dma engines that are used to move samples of digitally encoded data between system memory and external codecs. note: all registers in this function (including me mory-mapped registers) must be addressable in byte, word, and dword quantities. the software must always make register accesses on natural boundaries (that is, dword accesses must be on dword boundaries; word accesses on word boundaries, and so on). register access crossing the dword boundary are ignored. in addition, the me mory-mapped register space must not be accessed with the lock semantic exclusive-access mechanism. if software attempts exclusive-access mechanisms to the intel ? high definition audio memory-mapped space, the results are undefined. note: users interested in providing feedback on the intel ? high definition audio specification or planning to implement the intel ? high definition audio specification into a future product will need to execute the intel ? high definition audio specification developer?s agreement . for more information, contact nextgenaudio@intel.com. 17.1.1 intel ? high definition audio pci configuration space (intel ? high definition audio d27:f0) note: address locations that are not shown should be treated as reserved. table 17-1. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 1 of 3) offset mnemonic register name default attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 03h ro 0bh bcc base class code 04h ro 0ch cls cache line size 00h r/w 0dh lt latency timer 00h ro 0eh headtyp header type 00h ro
integrated intel ? high definition audio controller registers 686 datasheet 10h?13h hdbarl intel ? high definition audio lower base address (memory) 00000004h r/w, ro 14h?17h hdbaru intel ? high definition audio upper base address (memory) 00000000h r/w 2ch?2dh svid subsystem vendor identification 0000h r/wo 2eh?2fh sid subsystem identification 0000h r/wo 34h capptr capability list pointer 50h ro 3ch intln interrupt line 00h r/w 3dh intpn interrupt pin see register description ro 40h hdctl intel ? high definition audio control 01h r/w, ro 43h hdinit1 intel ? high definition audio initialization register 1 07h ro 4ch dckctl docking control (mobile only) 00h r/w, ro 4dh dcksts docking status (mobile only) 80h r/wo, ro 50h?51h pid pci power management capability id 6001h r/wo, ro 52h?53h pc power management capabilities c842h ro 54h?57h pcs power management control and status 00000000h r/w, ro, r/wc 60h?61h mid msi capability id 7005h ro 62h?63h mmc msi message control 0080h r/w, ro 64h?67h mmla msi message lower address 00000000h r/w, ro 68h?6bh mmua msi message upper address 00000000h r/w 6ch?6dh mmd msi message data 0000h r/w 70h?71h pxid pci express* capability identifiers 0010h ro 72h?73h pxc pci express capabilities 0091h ro 74h?77h devcap device capabilities 10000000h ro, r/wo 78h?79h devc device control 0800h r/w, ro 7ah?7bh devs device status 0010h ro 100h?103h vccap virtual channel enhanced capability header 13010002h r/wo 104h?107h pvccap1 port vc capability register 1 00000001h ro 108h?10bh pvccap2 port vc capability register 2 00000000h ro 10ch?10d pvcctl port vc control 0000h ro 10eh?10fh pvcsts port vc status 0000h ro 110h?113h vc0cap vc0 resource capability 00000000h ro 114h?117h vc0ctl vc0 resource control 800000ffh r/w, ro 11ah?11bh vc0sts vc0 resource status 0000h ro 11ch?11fh vcicap vci resource capability 00000000h ro table 17-1. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 2 of 3) offset mnemonic register name default attribute
datasheet 687 integrated intel ? high definition audio controller registers 17.1.1.1 vidvendor identification register (intel ? high definition au dio controllerd27:f0) offset: 00h?01h attribute: ro default value: 8086h size: 16 bits 17.1.1.2 diddevice identification register (intel ? high definition audi o controllerd27:f0) offset address: 02h ? 03h attribute: ro default value: see bit description size: 16 bits 120h?123h vcictl vci resource control 00000000h r/w, ro 126h?127h vcists vci resource status 0000h ro 130h?133h rccap root complex link declaration enhanced capability header 00010005h ro 134h?137h esd element self description 0f000100h ro 140h?143h l1desc link 1 description 00000001h ro 148h?14bh l1addl link 1 lower address see register description ro 14ch?14fh l1addu link 1 upper address 00000000h ro table 17-1. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 3 of 3) offset mnemonic register name default attribute bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the pch?s intel ? high definition audio controller. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the did register.
integrated intel ? high definition audio controller registers 688 datasheet 17.1.1.3 pcicmdpci command register (intel ? high definition audio controllerd27:f0) offset address: 04h?05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable (id) ? r/w. 0= the intx# signals may be asserted. 1= the intel ? high definition audio controller?s intx# signal will be deasserted. note: this bit does not affect the generation of msis. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. serr# is not generated by the pch intel ? high definition audio controller. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? r/w. per function ality not implemented. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 memory write and invalidate enable (mwie) ? ro. hardwired to 0. 3 special cycle en able (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. controls standard pci express* bus mastering capabilities for memory and i/o, reads and wr ites. note that this bit also controls msi generation since msi?s are essentially memory writes. 0 = disable 1 = enable 1 memory space enable (mse) ? r/w. enables memory space addresses to the intel ? high definition audio controller. 0 = disable 1 = enable 0 i/o space enable (iose)?ro. ha rdwired to 0 si nce the intel ? high definition audio controller does not implement i/o space.
datasheet 689 integrated intel ? high definition audio controller registers 17.1.1.4 pcistspci status register (intel ? high definition audi o controllerd27:f0) offset address: 06h?07h attribute: ro, r/wc default value: 0010h size: 16 bits 17.1.1.5 ridrevision identification register (intel ? high definition audi o controllerd27:f0) offset: 08h attribute: ro default value: see bit description size: 8 bits 17.1.1.6 piprogramming interface register (intel ? high definition audi o controllerd27:f0) offset: 09h attribute: ro default value: 00h size: 8 bits bit description 15 detected parity error (dpe) ? ro. hardwired to 0. 14 serr# status (serrs) ? ro. hardwired to 0. 13 received master abort (rma) ? r/wc. software clears this bit by writing a 1 to it. 0 = no master abort received. 1 = the intel ? high definition audio controller sets this bit when, as a bus master, it receives a master abort. when set, the intel ? high definition audio controller clears the run bit for the chan nel that received the abort. 12 received target abort (rta) ? ro. hardwired to 0. 11 signaled target abort (sta) ? ro. hardwired to 0. 10:9 devsel# timing status (dev_sts) ? ro. hardwired to 0. 8 data parity error detected (dped) ? ro. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 0. 6 reserved 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. hardwired to 1. indicates that the controller contains a capabilities poin ter list. the first item is pointed to by looking at configuration offset 34h. 3 interrupt status (is) ? ro. 0 = this bit is 0 after th e interrupt is cleared. 1 = this bit is 1 when the intx# is asserted. note that this bit is not set by an msi. 2:0 reserved bit description 7:0 revision id ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit description 7:0 programming interface ? ro.
integrated intel ? high definition audio controller registers 690 datasheet 17.1.1.7 sccsub class code register (intel ? high definition audio controllerd27:f0) address offset: 0ah attribute: ro default value: 03h size: 8 bits 17.1.1.8 bccbase cl ass code register (intel ? high definition audio controllerd27:f0) address offset: 0bh attribute: ro default value: 04h size: 8 bits 17.1.1.9 clscache line size register (intel ? high definition audio controllerd27:f0) address offset: 0ch attribute: r/w default value: 00h size: 8 bits 17.1.1.10 ltlatency timer register (intel ? high definition audio controllerd27:f0) address offset: 0dh attribute: ro default value: 00h size: 8 bits 17.1.1.11 headtypheader type register (intel ? high definition audio controllerd27:f0) address offset: 0eh attribute: ro default value: 00h size: 8 bits bit description 7:0 sub class code (scc) ? ro. 03h = audio device bit description 7:0 base class code (bcc) ? ro. 04h = multimedia device bit description 7:0 cache line size ? r/w. implemented as r/w register, but has no functional impact to the pch bit description 7:0 latency timer ? ro. hardwired to 00 bit description 7:0 header type ? ro. hardwired to 00.
datasheet 691 integrated intel ? high definition audio controller registers 17.1.1.12 hdbarlintel ? high definition audio lower base address register (intel ? high definition audiod27:f0) address offset: 10h?13h attribute: r/w, ro default value: 00000004h size: 32 bits 17.1.1.13 hdbaruintel ? high definition audio upper base address register (intel ? high definition audio controllerd27:f0) address offset: 14h?17h attribute: r/w default value: 00000000h size: 32 bits 17.1.1.14 svidsubsystem vendor identification register (intel ? high definition audi o controllerd27:f0) address offset: 2ch?2dh attribute: r/wo default value: 0000h size: 16 bits function level reset: no the svid register, in combination with the subsystem id register (d27:f0:2eh), enable the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value can be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. bit description 31:14 lower base address (lba) ? r/w. base address for the intel ? high definition audio controller?s memory mapped configuration registers. 16 kbytes are requested by hardwiring bits 13:4 to 0s. 13:4 reserved 3 prefetchable (pref) ? ro. hardwired to 0 to indi cate that this bar is not prefetchable 2:1 address range (addrng) ? ro. hardwired to 10b, indicating that this bar can be located anywhere in 64-bit address space. 0 space type (sptyp) ? ro. hardwired to 0. indicates this bar is located in memory space. bit description 31:0 upper base address (uba) ? r/w. upper 32 bits of th e base address for the intel ? high definition audio controller?s memory mapped configuration registers. bit description 15:0 subsystem vendor id ? r/wo.
integrated intel ? high definition audio controller registers 692 datasheet 17.1.1.15 sidsubsystem id entification register (intel ? high definition audio controllerd27:f0) address offset: 2eh?2fh attribute: r/wo default value: 0000h size: 16 bits function level reset: no the sid register, in combination with the subsystem vendor id register (d27:f0:2ch) make it possible for the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value can be read back. any subseq uent writes will have no effect. this register is not affected by the d3 hot to d0 transition. 17.1.1.16 capptrcapabilit ies pointer register (intel ? high definition audio controllerd27:f0) address offset: 34h attribute: ro default value: 50h size: 8 bits this register indicates the offset for the capability pointer. 17.1.1.17 intlninterrupt line register (intel ? high definition audio controllerd27:f0) address offset: 3ch attribute: r/w default value: 00h size: 8 bits function level reset: no 17.1.1.18 intpninterrupt pin register (intel ? high definition audio controllerd27:f0) address offset: 3dh attribute: ro default value: see description size: 8 bits bit description 15:0 subsystem id ? r/wo. bit description 7:0 capabilities pointer (cap_ptr) ? ro. this field indicates that the first capability pointer offset is offset 50h (power management capability). bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the pch. it is used to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:4 reserved 3:0 interrupt pin (ip) ? ro. this reflects the value of d27ip.zip (chipset config registers:offset 3110h:bits 3:0).
datasheet 693 integrated intel ? high definition audio controller registers 17.1.1.19 hdctlintel ? high definition audio control register (intel ? high definition audi o controllerd27:f0) address offset: 40h attribute: ro default value: 01h size: 8 bits 17.1.1.20 hdinit1intel? high definiti on audio initialization register 1 (intel ? high definition au dio controllerd27:f0) address offset: 43h attribute: ro default value: 07h size: 8 bits 17.1.1.21 dckctldocking cont rol register (mobile only) (intel ? high definition audi o controllerd27:f0) address offset: 4ch attribute: r/w, ro default value: 00h size: 8 bits function level reset: no bit description 7:1 reserved 0 intel ? high definition signal mode ? ro. this bit is hardwired to 1 (high definition audio mode). bit description 7:3 reserved 2:0 hdinit1 field 1 ? r/w. bios must program this field to 101b. bit description 7:1 reserved 0 dock attach (da) ? r/w / ro. software writes a 1 to this bit to initiate the docking sequence on the hda_dock_en# and hda_ dock_rst# signals. when the docking sequence is complete, hardware will set th e dock mated (gsts.dm) status bit to 1. software writes a 0 to this bit to in itiate the undocking sequence on the hda_dock_en# and hda_dock_rst# signal s. when the undocking sequence is complete, hardware will set the dock mated (gsts.dm) status bit to 0. note that software must check the state of the dock mated (gsts.dm) bit prior to writing to the dock attach bit. software shall only change the da bit from 0 to 1 when dm=0. likewise, software shal l only change the da bit from 1 to 0 when dm=1. if these rules are violated, the results are undefined. note that this bit is read on ly when the dcksts.ds bit = 0.
integrated intel ? high definition audio controller registers 694 datasheet 17.1.1.22 dckstsdocking stat us register (mobile only) (intel ? high definition audio controllerd27:f0) address offset: 4dh attribute: r/wo, ro default value: 80h size: 8 bits function level reset: no 17.1.1.23 pidpci power management capability id register (intel ? high definition audio controllerd27:f0) address offset: 50h?51h attribute: r/wo, ro default value: 6001h size: 16 bits function level reset: no (bits 7:0 only) bit description 7 docking supported (ds) ? r/wo: a 1 indicates th at pch supports hd audio docking. the dckctl.da bit is only writable when this ds bit is 1. acpi bios software should only branch to the docking routine when this ds bit is 1. bios may clear this bit to 0 to prohibit the acpi bios software from attempting to run the docking routines. note that this bit is reset to its default value only on a pltrst#, but not on a crst# or d3hot-to-d0 transition. 6:1 reserved 0 dock mated (dm) ? ro: this bit effectively communicates to software that an intel ? hd audio docked codec is physic ally and electrically attached. controller hardware sets this bit to 1 afte r the docking sequence triggered by writing a 1 to the dock attach (gctl.da) bit is co mpleted (hda_dock_rst# deassertion). this bit indicates to software that the dock ed codec(s) may be discovered using the statests register and then enumerated. controller hardware se ts this bit to 0 after the undock ing sequence tri ggered by writing a 0 to the dock attach (gctl.da) bit is completed (hda_dock_en# deasserted). this bit indicates to software that the docked codec(s) may be physically undocked. bit description 15:8 next capability (next) ? r/wo. points to the next capability structure (msi). 7:0 cap id (cap) ? ro. hardwired to 01h. indicates that this pointer is a pci power management capability. th ese bits are not reset by function level reset.
datasheet 695 integrated intel ? high definition audio controller registers 17.1.1.24 pcpower manageme nt capabilities register (intel ? high definition audi o controllerd27:f0) address offset: 52h?53h attribute: ro default value: c842h size: 16 bits 17.1.1.25 pcspower management control and status register (intel ? high definition audi o controllerd27:f0) address offset: 54h?57h attribute: ro, r/w, r/wc default value: 00000000h size: 32 bits function level reset: no bit description 15:11 pme support ? ro. hardwired to 11001b. indicate s pme# can be generated from d3 and d0 states. 10 d2 support ? ro. hardwired to 0. indi cates that d2 state is not supported. 9 d1 support ?ro. hardwired to 0. indi cates that d1 state is not supported. 8:6 aux current ? ro. hardwired to 001b. reports 55 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi) ? ro. hardwired to 0. indicates that no device specific initialization is required. 4 reserved 3 pme clock (pmec) ? ro. does not apply. hardwired to 0. 2:0 version ? ro. hardwired to 010b. indicates su pport for version 1.1 of the pci power management specification. bit description 31:24 data ? ro. does not apply. hardwired to 0. 23 bus power/clock control enable ? ro . does not apply. hardwired to 0. 22 b2/b3 support ? ro. does not apply. hardwired to 0. 21:16 reserved 15 pme status (pmes) ? r/wc. 0 = software clears the bit by writing a 1 to it. 1 = this bit is set when the intel ? high definition audio controller would normally assert the pme# signal independent of the state of the pme_en bit (bit 8 in this register). this bit is in the resume well and is clea red by a power-on reset. software must not make assumptions about the reset state of this bit and must se t it appropriately. 14:9 reserved 8 pme enable (pmee) ? r/w. 0 = disable 1 = when set and if corresponding pmes also set, the intel ? high definition audio controller sets the pme_b0_sts bit in the gpe0_sts register (pmbase +28h). this bit is in the resume well and is clea red on a power-on rese t. software must not make assumptions about the reset state of this bit and must se t it appropriately. 7:2 reserved
integrated intel ? high definition audio controller registers 696 datasheet 17.1.1.26 midmsi capability id register (intel ? high definition audio controllerd27:f0) address offset: 60h?61h attribute: ro default value: 7005h size: 16 bits 17.1.1.27 mmcmsi message control register (intel ? high definition audio controllerd27:f0) address offset: 62h?63h attribute: ro, r/w default value: 0080h size: 16 bits 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the intel ? high definition audio controll er and to set a new power state. 00 = d0 state 11 = d3 hot state others = reserved notes: 1. if software attempts to write a value of 01b or 10b in to this field, the write operation must complete normally; howeve r, the data is discarded and no state change occurs. 2. when in the d3 hot states, the intel ? high definition audio controller?s configuration space is available, but the io and memory space are not. additi onally, interrupts are blocked. 3. when software chan ges this value from d3 hot state to the d0 state, an internal warm (soft) reset is generated, and so ftware must re-initialize the function. bit description bit description 15:8 next capability (next) ? ro. hardwired to 70h. points to the pci express* capability structure. 7:0 cap id (cap) ? ro. hardwired to 05h. indicates that this pointer is a msi capability. bit description 15:8 reserved 7 64b address capability (64add) ? ro. hardwired to 1. indicates the ability to generate a 64-bit message address. 6:4 multiple message enable (mme) ? ro. normally this is a r/w register. however since only 1 message is supported, these bits are hardwired to 000 = 1 message. 3:1 multiple message capable (mmc) ? ro. ha rdwired to 0 indicating request for 1 message. 0 msi enable (me) ? r/w. 0 = an msi may not be generated 1 = an msi will be generated instead of an intx signal.
datasheet 697 integrated intel ? high definition audio controller registers 17.1.1.28 mmlamsi message lower address register (intel ? high definition audi o controllerd27:f0) address offset: 64h?67h attribute: ro, r/w default value: 00000000h size: 32 bits 17.1.1.29 mmuamsi message upper address register (intel ? high definition audi o controllerd27:f0) address offset: 68h?6bh attribute: r/w default value: 00000000h size: 32 bits 17.1.1.30 mmdmsi message data register (intel ? high definition audi o controllerd27:f0) address offset: 6ch?6dh attribute: r/w default value: 0000h size: 16 bits 17.1.1.31 pxidpci express* capability id register (intel ? high definition audi o controllerd27:f0) address offset: 70h?71h attribute: ro default value: 0010h size: 16 bits bit description 31:2 message lower address (mla) ? r/w. lower address used for msi message. 1:0 reserved bit description 31:0 message upper address (mua) ? r/w. upper 32-bits of address used for msi message. bit description 15:0 message data (md) ? r/w. data used for msi message. bit description 15:8 next capability (next) ? ro. hardwired to 0. indicates that this is the last capability structure in the list. 7:0 cap id (cap) ? ro. hardwired to 10h. indicates th at this pointer is a pci express* capability structure.
integrated intel ? high definition audio controller registers 698 datasheet 17.1.1.32 pxcpci express* capabilities register (intel ? high definition audio controllerd27:f0) address offset: 72h?73h attribute: ro default value: 0091h size: 16 bits 17.1.1.33 devcapdevice capabilities register (intel ? high definition audio controllerd27:f0) address offset: 74h?77h attribute: r/wo, ro default value: 10000000h size: 32 bits function level reset: no bit description 15:14 reserved 13:9 interrupt message number (imn) ? ro. hardwired to 0. 8 slot implemented (si) ? ro. hardwired to 0. 7:4 device/port type (dpt) ? ro. hardwired to 1001b. indi cates that this is a root complex integrated endpoint device. 3:0 capability version (cv) ? ro. hardwired to 0001b. indicates version #1 pci express capability bit description 31:29 reserved 28 function level reset (flr) ? r/wo. a 1 indicates that the pch hd audio controller supports the function level reset capability. 27:26 captured slot power limit sc ale (spls) ? ro. hardwired to 0. 25:18 captured slot power limit value (splv) ? ro. hardwired to 0. 17:15 reserved 14 power indicator present ? ro. hardwired to 0. 13 attention indicator present ? ro. hardwired to 0. 12 attention button present ? ro. hardwired to 0. 11:9 endpoint l1 acceptable latency ? r/wo. 8:6 endpoint l0s acceptable latency ? r/wo. 5 extended tag field support ? ro. hardwired to 0. indicates 5-bit tag field support 4:3 phantom functions supported ? ro. hardwired to 0. indicates that phantom functions not supported. 2:0 max payload size supported ? ro. hardwired to 0. indicates 128-b maximum payload size capability.
datasheet 699 integrated intel ? high definition audio controller registers 17.1.1.34 devcdevice control register (intel ? high definition audi o controllerd27:f0) address offset: 78h?79h attribute: r/w, ro default value: 0800h size: 16 bits function level reset: no (bit 11 only) bit description 15 initiate flr (if) ? r/w. this bit is used to initiate flr transition. 1 = a write of 1 initiates flr transition. since hardware does not respond to any cycles until flr completion, the read valu e by software from this bit is 0. 14:12 max read request size ? ro. hardwired to 0 enabling 128b maximum read request size. 11 no snoop enable (nsnpen) ? r/w. 0 = the intel ? high definition audio controller will not set the no snoop bit. in this case, isochronous transfers will not use vc1 (vci) even if it is enabled since vc1 is never snooped. isochronous transfers will use vc0. 1 = the intel ? high definition audio controller is permitted to set the no snoop bit in the requester attributes of a bus master transaction. in this case, vc0 or vc1 may be used for isochronous transfers. note: this bit is not reset on d3 hot to d0 transition; however, it is reset by pltrst#. this bit is not reset by function level reset. 10 auxiliary power enable ? ro. hardwi red to 0, indicating that intel ? high definition audio device does not draw aux power 9 phantom function enable ? ro. hardwi red to 0 disabling phantom functions. 8 extended tag field enable ? ro. hardwired to 0 enabling 5-bit tag. 7:5 max payload size ? ro. hardwired to 0 indicating 128b. 4 enable relaxed ordering ? ro. hardwi red to 0 disabling relaxed ordering. 3 unsupported request reporting enable ? r/w. not implemented. 2 fatal error reporting enable ? r/w. not implemented. 1 non-fatal error reporting en able ? r/w. not implemented. 0 correctable error reporting en able ? r/w. not implemented.
integrated intel ? high definition audio controller registers 700 datasheet 17.1.1.35 devsdevice status register (intel ? high definition audio controllerd27:f0) address offset: 7ah?7bh attribute: ro default value: 0010h size: 16 bits 17.1.1.36 vccapvirtual channel enhanced capability header (intel ? high definition audio controllerd27:f0) address offset: 100h?103h attribute: r/wo default value: 13010002h size: 32 bits bit description 15:6 reserved 5 transactions pending ? ro. 0 = indicates that completions for all no n-posted requests have been received 1 = indicates that intel ? high definition audio contro ller has issued non-posted requests which have not been completed. 4 aux power detected ? ro. hardwired to 1 indicating the device is connected to resume power 3 unsupported request detected ? ro . not implemented. hardwired to 0. 2 fatal error detected ? ro. no t implemented. hardwired to 0. 1 non-fatal error detected ? ro. not implemented. hardwired to 0. 0 correctable error detected ? ro. not implemented. hardwired to 0. bit description 31:20 next capability offset ? r/wo. points to the next capability header. 130h = root complex link declar ation enhanced capability header 000h = root complex link declaration enha nced capability header is not supported. 19:16 capability version ? r/wo. 0h =pci express virtual chan nel capability and the root complex topology capability structure are not supported. 1h =pci express virtual chan nel capability and the root complex topology capability structure are supported. 15:0 pci express* extended capability ? r/wo. 0000h =pci express virtual channel capa bility and the root complex topology capability structure are not supported. 0002h =pci express virtual channel capa bility and the root complex topology capability structure are supported.
datasheet 701 integrated intel ? high definition audio controller registers 17.1.1.37 pvccap1port vc capability register 1 (intel ? high definition audi o controllerd27:f0) address offset: 104h?107h attribute: ro default value: 00000001h size: 32 bits 17.1.1.38 pvccap2 port vc capability register 2 (intel ? high definition audi o controllerd27:f0) address offset: 108h?10bh attribute: ro default value: 00000000h size: 32 bits 17.1.1.39 pvcctl port vc control register (intel ? high definition audi o controllerd27:f0) address offset: 10ch?10dh attribute: ro default value: 0000h size: 16 bits bit description 31:12 reserved 11:10 port arbitration table entry size ? ro. hard wired to 0 since this is an endpoint device. 9:8 reference clock ? ro. hardwired to 0 since this is an endpoint device. 7 reserved 6:4 low priority extended vc count ? ro. hardwired to 0. indicates that only vc0 belongs to the low priority vc group. 3 reserved 2:0 extended vc count ? ro. hardwired to 001b. indicates that 1 extended vc (in addition to vc0) is supported by the intel ? high definition audio controller. bit description 31:24 vc arbitration table offset ? ro. hardwired to 0 indicating that a vc arbitration table is not present. 23:8 reserved 7:0 vc arbitration capability ? ro. hardwired to 0. these bits are not applicable since the intel ? high definition audio controller report s a 0 in the low priority extended vc count bits in the pvccap1 register. bit description 15:4 reserved 3:1 vc arbitration select ? ro. hardwired to 0. normally these bits are r/w. however, these bits are not applicable since the intel ? high definition audio controller reports a 0 in the low priority extended vc count bits in the pvccap1 register. 0 load vc arbitration table ? ro. hardwired to 0 since an arbitration table is not present.
integrated intel ? high definition audio controller registers 702 datasheet 17.1.1.40 pvcstsport vc status register (intel ? high definition audio controllerd27:f0) address offset: 10eh?10fh attribute: ro default value: 0000h size: 16 bits 17.1.1.41 vc0capvc0 resource capability register (intel ? high definition audio controllerd27:f0) address offset: 110h?113h attribute: ro default value: 00000000h size: 32 bits bit description 15:1 reserved 0 vc arbitration table status ? ro. hardwire d to 0 since an arbitration table is not present. bit description 31:24 port arbitration table offset ? ro. hardwire d to 0 since this field is not valid for endpoint devices 23 reserved 22:16 maximum time slots ? ro. hardwired to 0 si nce this field is not valid for endpoint devices. 15 reject snoop transactions ? ro. hardwired to 0 since this field is not valid for endpoint devices. 14 advanced packet switching ? ro. hardwired to 0 since this field is not valid for endpoint devices. 13:8 reserved 7:0 port arbitration capability ? ro. hardwired to 0 since this field is not valid for endpoint devices.
datasheet 703 integrated intel ? high definition audio controller registers 17.1.1.42 vc0ctlvc0 resource control register (intel ? high definition audi o controllerd27:f0) address offset: 114h?117h attribute: r/w, ro default value: 800000ffh size: 32 bits function level reset: no 17.1.1.43 vc0stsvc0 resource status register (intel ? high definition audi o controllerd27:f0) address offset: 11ah?11bh attribute: ro default value: 0000h size: 16 bits bit description 31 vc0 enable ? ro. hardwired to 1 for vc0. 30:27 reserved 26:24 vc0 id ? ro. hardwired to 0 since th e first vc is always assigned as vc0. 23:20 reserved 19:17 port arbitration select ? ro. hardwired to 0 since this field is not valid for endpoint devices. 16 load port arbitration table ? ro. hardwired to 0 since this field is not valid for endpoint devices. 15:8 reserved 7:0 tc/vc0 map ? r/w, ro. bit 0 is hardwired to 1 si nce tc0 is always mapped vc0. bits [7:1] are implemented as r/w bits. bit description 15:2 reserved 1 vc0 negotiation pending ? ro. hardwired to 0 since this bit does not apply to the integrated intel ? high definition audio device. 0 port arbitration table status ? ro. hardwire d to 0 since this field is not valid for endpoint devices.
integrated intel ? high definition audio controller registers 704 datasheet 17.1.1.44 vcicapvci resource capability register (intel ? high definition audio controllerd27:f0) address offset: 11ch?11fh attribute: ro default value: 00000000h size: 32 bits 17.1.1.45 vcictlvci resource control register (intel ? high definition audio controllerd27:f0) address offset: 120h?123h attribute: r/w, ro default value: 00000000h size: 32 bits function level reset: no bit description 31:24 port arbitration table offset ? ro. hardwire d to 0 since this field is not valid for endpoint devices. 23 reserved 22:16 maximum time slots ? ro. hardwired to 0 si nce this field is not valid for endpoint devices. 15 reject snoop transactions ? ro. hardwired to 0 since this field is not valid for endpoint devices. 14 advanced packet switching ? ro. hardwired to 0 since this field is not valid for endpoint devices. 13:8 reserved 7:0 port arbitration capability ? ro. hardwired to 0 since this field is not valid for endpoint devices. bit description 31 vci enable ? r/w. 0 = vci is disabled 1 = vci is enabled note: this bit is not reset on d3 hot to d0 transition; however, it is reset by pltrst#. 30:27 reserved 26:24 vci id ? r/w. this field assigns a vc id to th e vci resource. this field is not used by the pch hardware, but it is r/w to avoid confusing software. 23:20 reserved 19:17 port arbitration select ? ro. hardwired to 0 since this field is not valid for endpoint devices. 16 load port arbitration table ? ro. hardwired to 0 since this field is not valid for endpoint devices. 15:8 reserved 7:0 tc/vci map ? r/w, ro. this field indicates the tcs that are mapped to the vci resource. bit 0 is hardwired to 0 indicating th at it cannot be mapped to vci. bits [7:1] are implemented as r/w bits. th is field is not used by the pch hardware, but it is r/w to avoid confusing software.
datasheet 705 integrated intel ? high definition audio controller registers 17.1.1.46 vcistsvci resource status register (intel ? high definition audi o controllerd27:f0) address offset: 126h?127h attribute: ro default value: 0000h size: 16 bits 17.1.1.47 rccaproot complex link declaration enhanced capability header register (intel ? high definition audi o controllerd27:f0) address offset: 130h?133h attribute: ro default value: 00010005h size: 32 bits 17.1.1.48 esdelement self description register (intel ? high definition audi o controllerd27:f0) address offset: 134h?137h attribute: ro default value: 0f000100h size: 32 bits bit description 15:2 reserved 1 vci negotiation pending ? ro. does not apply. hardwired to 0. 0 port arbitration table status ? ro. hardwire d to 0 since this field is not valid for endpoint devices. bit description 31:20 next capability offset ? ro. hardwired to 0 indicating this is the last capability. 19:16 capability version ? ro. hardwired to 1h. 15:0 pci express* extended capability id ? ro. hardwired to 0005h. bit description 31:24 port number ? ro. hardwired to 0fh indicating that the intel ? high definition audio controller is assigned as port #15d. 23:16 component id ? ro. this field returns the value of the esd.cid field of the chip configuration section. esd.cid is programmed by bios. 15:8 number of link entries ? ro. the intel ? high definition audio only connects to one device, the pch egress port. therefore, this field reports a value of 1h. 7:4 reserved 3:0 element type (eltyp ) ? ro. the intel ? high definition audio controller is an integrated root complex de vice. therefore, the fiel d reports a value of 0h.
integrated intel ? high definition audio controller registers 706 datasheet 17.1.1.49 l1desclink 1 description register (intel ? high definition audio controllerd27:f0) address offset: 140h?143h attribute: ro default value: 00000001h size: 32 bits 17.1.1.50 l1addllink 1 lower address register (intel ? high definition audio controllerd27:f0) address offset: 148h?14bh attribute: ro default value: see register description size: 32 bits 17.1.1.51 l1addulink 1 upper address register (intel ? high definition audio controllerd27:f0) address offset: 14ch?14fh attribute: ro default value: 00000000h size: 32 bits bit description 31:24 target port number ? ro. the intel ? high definition audio controller targets the pch?s port 0. 23:16 target component id ? ro. this field returns the value of the esd.cid field of the chip configuration section. esd.cid is programmed by bios. 15:2 reserved 1 link type ? ro. hardwired to 0 indicating type 0. 0 link valid ? ro. hardwired to 1. bit description 31:14 link 1 lower address ? ro. hardwired to match the rcba register value in the pci- lpc bridge (d31:f0:f0h). 13:0 reserved bit description 31:0 link 1 upper address ? ro. hardwired to 00000000h.
datasheet 707 integrated intel ? high definition audio controller registers 17.1.2 intel ? high definition au dio memory mapped configuration registers (intel ? high definition audio d27:f0) the base memory location for these memory mapped configuration registers is specified in the hdbar register (d27:f0:offset 10h and d27:f0:offset 14h). the individual registers are then accessible at hdbar + offset as indicated in ta b l e 1 7 - 2 . these memory mapped registers must be accessed in byte, word, or dword quantities. note: address locations that are not shown should be treated as reserved. table 17-2. intel ? high definition audio memory mapped configuration registers address map (intel ? high definition audio d27:f0) (sheet 1 of 4) hdbar + offset mnemonic register name default attribute 00h?01h gcap global capabilities 4401h ro, r/wo 02h vmin minor version 00h ro 03h vmaj major version 01h ro 04h?05h outpay output payload capability 003ch ro 06h?07h inpay input payload capability 001dh ro 08h?0bh gctl global control 00000000h r/w 0ch?0dh wakeen wake enable 0000h r/w 0eh?0fh statests state change status 0000h r/wc 10h?11h gsts global status 0000h r/wc 18h?19h outstrmpay output stream payload capability 0030h ro 1ah?1bh instrmpay input stream payload capability 0018h ro 1ch?1fh ? reserved 00000000h ro 20h?23h intctl interrupt control 00000000h r/w 24h?27h intsts interrupt status 00000000h ro 30h?33h walclk wall clock counter 00000000h ro 38h?3bh ssync stream synchronization 00000000h r/w 40h?43h corblbase corb lower base address 00000000h r/w, ro 44h?47h corbubase corb upper base address 00000000h r/w 48h?49h corbwp corb write pointer 0000h r/w 4ah?4bh corbrp corb read pointer 0000h r/w, ro 4ch corbctl corb control 00h r/w 4dh corbst corb status 00h r/wc 4eh corbsize corb size 42h ro 50h?53h rirblbase rirb lower base address 00000000h r/w, ro 54h?57h rirbubase rirb upper base address 00000000h r/w 58h?59h rirbwp rirb write pointer 0000h r/w, ro 5ah?5bh rintcnt response interrupt count 0000h r/w 5ch rirbctl rirb control 00h r/w
integrated intel ? high definition audio controller registers 708 datasheet 5dh rirbsts rirb status 00h r/wc 5eh rirbsize rirb size 42h ro 60h?63h ic immediate command 00000000h r/w 64h?67h ir immediate response 00000000h ro 68h?69h ics immediate command status 0000h r/w, r/wc 70h?73h dplbase dma position lower base address 00000000h r/w, ro 74h?77h dpubase dma position upper base address 00000000h r/w 80h?82h isd0ctl input stream descriptor control 040000h r/w, ro 83h isd0sts isd0 status 00h r/wc, ro 84h?87h isd0lpib isd0 link position in buffer 00000000h ro 88h?8bh isd0cbl isd0 cyclic buffer length 00000000h r/w 8ch?8dh isd0lvi isd0 last valid index 0000h r/w 8eh?8f isd0fifow isd0 fifo watermark 0004h r/w 90h?91h isd0fifos isd0 fifo size 0000h r/w 92h?93h isd0fmt isd0 format 0000h r/w 98h?9bh isd0bdpl isd0 buffer descript or list pointer ? lower base address 00000000h r/w, ro 9ch?9fh isd0bdpu isd0 buffer descript ion list pointer ? upper base address 00000000h r/w a0h?a2h isd1ctl input stream descriptor 1(isd1) control 040000h r/w, ro a3h isd1sts isd1 status 00h r/wc, ro a4h?a7h isd1lpib isd1 link position in buffer 00000000h ro a8h?abh isd1cbl isd1 cyclic buffer length 00000000h r/w ach?adh isd1lvi isd1 last valid index 0000h r/w aeh?afh isd1fifow isd1 fifo watermark 0004h r/w b0h?b1h isd1fifos isd1 fifo size 0000h r/w b2h?b3h isd1fmt isd1 format 0000h r/w b8h?bbh isd1bdpl isd1 buffer descript or list pointer ? lower base address 00000000h r/w, ro bch?bfh isd1bdpu isd1 buffer descript ion list pointer ? upper base address 00000000h r/w c0h?c2h isd2ctl input stream descriptor 2 (isd2) control 040000h r/w, ro c3h isd2sts isd2 status 00h r/wc, ro c4h?c7h isd2lpib isd2 link position in buffer 00000000h ro c8h?cbh isd2cbl isd2 cyclic buffer length 00000000h r/w cch?cdh isd2lvi isd2 last valid index 0000h r/w table 17-2. intel ? high definition audio memory mapped configuration registers address map (intel ? high definition audio d27:f0) (sheet 2 of 4) hdbar + offset mnemonic register name default attribute
datasheet 709 integrated intel ? high definition audio controller registers ceh?cfh isd1fifow isd1 fifo watermark 0004h r/w d0h?d1h isd2fifos isd2 fifo size 0000h r/w d2h?d3h isd2fmt isd2 format 0000h r/w d8h?dbh isd2bdpl isd2 buffer descriptor list pointer ? lower base address 00000000h r/w, ro dch?dfh isd2bdpu isd2 buffer descripti on list pointer ? upper base address 00000000h r/w e0h?e2h isd3ctl input stream descriptor 3 (isd3) control 040000h r/w, ro e3h isd3sts isd3 status 00h r/wc, ro e4h?e7h isd3lpib isd3 link position in buffer 00000000h ro e8h?ebh isd3cbl isd3 cyclic buffer length 00000000h r/w ech?edh isd3lvi isd3 last valid index 0000h r/w eeh?efh isd3fifow isd3 fifo watermark 0004h r/w f0h?f1h isd3fifos isd3 fifo size 0000h r/w f2h?f3h isd3fmt isd3 format 0000h r/w f8h?fbh isd3bdpl isd3 buffer descriptor list pointer ? lower base address 00000000h r/w, ro fch?ffh isd3bdpu isd3 buffer descripti on list pointer ? upper base address 00000000h r/w 100h?102h osd0ctl output stream desc riptor 0 (osd0) control 040000h r/w, ro 103h osd0sts osd0 status 00h r/wc, ro 104h?107h osd0lpib osd0 link position in buffer 00000000h ro 108h?10bh osd0cbl osd0 cyclic buffer length 00000000h r/w 10ch?10dh osd0lvi osd0 last valid index 0000h r/w 10eh?10fh osd0fifow osd0 fifo watermark 0004h r/w 110h?111h osd0fifos osd0 fifo size 0000h r/w 112?113h osd0fmt osd0 format 0000h r/w 118h?11bh osd0bdpl osd0 buffer descript or list pointer ? lower base address 00000000h r/w, ro 11ch?11fh osd0bdpu osd0 buffer descript ion list pointer ? upper base address 00000000h r/w 120h?122h osd1ctl output stream desc riptor 1 (osd1) control 040000h r/w, ro 123h osd1sts osd1 status 00h r/wc, ro 124h?127h osd1lpib osd1 link position in buffer 00000000h ro 128h?12bh osd1cbl osd1 cyclic buffer length 00000000h r/w 12ch?12dh osd1lvi osd1 last valid index 0000h r/w table 17-2. intel ? high definition audio memory mapped configuration registers address map (intel ? high definition audio d27:f0) (sheet 3 of 4) hdbar + offset mnemonic register name default attribute
integrated intel ? high definition audio controller registers 710 datasheet 12eh?12fh osd1fifow osd1 fifo watermark 0004h r/w 130h?131h osd1fifos osd1 fifo size 0000h r/w 132h?133h osd1fmt osd1 format 0000h r/w 138h?13bh osd1bdpl osd1 buffer descriptor list pointer ? lower base address 00000000h r/w, ro 13ch?13fh osd1bdpu osd1 buffer description list pointer ? upper base address 00000000h r/w 140h?142h osd2ctl output stream descriptor 2 (osd2) control 040000h r/w, ro 143h osd2sts osd2 status 00h r/wc, ro 144h?147h osd2lpib osd2 link position in buffer 00000000h ro 148h?14bh osd2cbl osd2 cyclic buffer length 00000000h r/w 14ch?14dh osd2lvi osd2 last valid index 0000h r/w 14eh?14fh osd2fifow osd2 fifo watermark 0004h r/w 150h?151h osd2fifos osd2 fifo size 0000h r/w 152h?153h osd2fmt osd2 format 0000h r/w 158h?15bh osd2bdpl osd2 buffer descriptor list pointer ? lower base address 00000000h r/w, ro 15ch?15fh osd2bdpu osd2 buffer description list pointer ? upper base address 00000000h r/w 160h?162h osd3ctl output stream descriptor 3 (osd3) control 040000h r/w, ro 163h osd3sts osd3 status 00h r/wc, ro 164h?167h osd3lpib osd3 link position in buffer 00000000h ro 168h?16bh osd3cbl osd3 cyclic buffer length 00000000h r/w 16ch?16dh osd3lvi osd3 last valid index 0000h r/w 16eh?16fh osd3fifow osd3 fifo watermark 0004h r/w 170h?171h osd3fifos osd3 fifo size 0000h r/w 172h?173h osd3fmt osd3 format 0000h r/w 178h?17bh osd3bdpl osd3 buffer descriptor list pointer ? lower base address 00000000h r/w, ro 17ch?17fh osd3bdpu osd3 buffer description list pointer ? upper base address 00000000h r/w table 17-2. intel ? high definition audio memory mapped configuration registers address map (intel ? high definition audio d27:f0) (sheet 4 of 4) hdbar + offset mnemonic register name default attribute
datasheet 711 integrated intel ? high definition audio controller registers 17.1.2.1 gcapglobal capabilities register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 00h attribute: ro, r/wo default value: 4401h size: 16 bits 17.1.2.2 vminminor version register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 02h attribute: ro default value: 00h size: 8 bits 17.1.2.3 vmajmajor version register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 03h attribute: ro default value: 01h size: 8 bits bit description 15:12 number of output stream supported ? r/wo. 0100b indicates that the pch?s intel ? high definition audio controller supports 4 output streams. 11:8 number of input stream supported ? r/wo. 0100b indicates that the pch?s intel ? high definition audio controller supports 4 input streams. 7:3 number of bidirectional stream supported ? ro. hardwired to 0 indicating that the pch?s intel? high definition audio co ntroller supports 0 bidirectional stream. 2:1 number of serial data out signals ? ro. hardwired to 0 indicating that the pch?s intel ? high definition audio controller su pports 1 serial data output signal. 0 64-bit address supported ? r/wo. 1b indicates that the pch?s intel ? high definition audio controller supports 64-bit addressing for bdl a ddresses, data buffer addressees, and comm and buffer addresses. bit description 7:0 minor version ? ro. hardwired to 0 indicating that the pch supports minor revision number 00h of the intel ? high definition audio specification. bit description 7:0 major version ? ro. hardwired to 01h indicating that the pch supports major revision number 1 of the intel ? high definition audio specification.
integrated intel ? high definition audio controller registers 712 datasheet 17.1.2.4 outpayoutput payload capability register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 04h attribute: ro default value: 003ch size: 16 bits 17.1.2.5 inpayinput payl oad capability register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 06h attribute: ro default value: 001dh size: 16 bits bit description 15:7 reserved 6:0 output payload capability ? ro. hardwired to 3ch indicating 60 word payload. this field indicates the total output payload available on the link. this does not include bandwidth used for command and control. this measurement is in 16-bit word quantities per 48 mhz fr ame. the default link clock of 24.000 mhz (the data is double pumped) provides 1000 bits pe r frame, or 62.5 words in total. 40 bits are used for command and control, leaving 60 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... ffh = 256 word payload. bit description 15:7 reserved 6:0 input payload capability ? ro. hardwired to 1dh indicating 29 word payload. this field indicates the total output payload available on the link. this does not include bandwidth used for response. this measurement is in 16-bit word quantities per 48 mhz frame. the default link clock of 24.000 mhz provides 500 bits per frame, or 31.25 words in total. 36 bits are used for response, leaving 29 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... ffh = 256 word payload.
datasheet 713 integrated intel ? high definition audio controller registers 17.1.2.6 gctlglobal control register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 08h attribute: r/w default value: 00000000h size: 32 bits bit de scription 31:9 reserved 8 accept unsolicited response enable ? r/w. 0 = unsolicited responses from the codecs are not accepted. 1 = unsolicited response from the codecs ar e accepted by the controller and placed into the response input ring buffer. 7:2 reserved 1 flush control ? r/w. writing a 1 to this bit initiates a flush. when the flush completion is received by the controller, ha rdware sets the flush status bit and clears this flush control bit. before a flush cycle is initiated, the dma po sition buffer must be programmed with a valid memory address by software, but the dm a position buffer bit 0 needs not be set to enable the position reporting mechanism. also, all streams must be stopped (the associat ed run bit must be 0). when the flush is initiated, the controller wi ll flush the pipelines to memory to ensure that the hardware is ready to transition to a d3 state. setting this bit is not a critical step in the power state transition if the content of the fifos is not critical. 0 controller reset # ? r/w. 0 = writing a 0 causes the intel ? high definition audio contro ller to be reset. all state machines, fifos, and non-resume well memory mapped configuration registers (not pci configuration registers) in th e controller will be reset. the intel ? high definition audio link reset# signal will be asserted, and all other link signals will be driven to their default values. after the hardware has completed sequencing into the reset state, it will report a 0 in this bit. soft ware must read a 0 from this bit to verify the controller is in reset. 1 = writing a 1 causes the controller to ex it its reset state and deassert the intel ? high definition audio link reset# sign al. software is responsible for setting/ clearing this bit such that the minimum intel ? high definition audio link reset# signal assertion pulse width specification is met. when the cont roller hardware is ready to begin operation, it will report a 1 in this bit. software must read a 1 from this bit before accessing any controller re gisters. this bit defaults to a 0 after hardware reset, therefore, software needs to write a 1 to this bit to begin operation. notes: 1. the corb/rirb run bits and all stream ru n bits must be verified cleared to 0 before writing a 0 to this bit in order to assure a clean re-start. 2. when setting or clearing this bit, softwa re must ensure that minimum link timing requirements (minimum reset# assertion time, etc.) are met. 3. when this bit is 0 indicating that the controller is in re set, writes to all intel high definition audio memory ma pped registers are ignored as if the device is not present. the only exception is this register itself. the global control register is write-able as a dword, word, or byte even when crst# (this bit) is 0 if the byte enable for the byte containi ng the crst# bit (byte enable 0) is active. if byte enable 0 is not active, writes to the glob al control register will be ignored when crst# is 0. when crst# is 0, reads to intel high definition audio memory mapped registers will return their default value except for registers that are not reset with pltrst# or on a d3 hot to d0 transition.
integrated intel ? high definition audio controller registers 714 datasheet 17.1.2.7 wakeenwake enable register (intel ? high definition audio controllerd27:f0) memory address: hdbar + 0ch attribute: r/w default value: 0000h size: 16 bits function level reset: no 17.1.2.8 statestsstate ch ange status register (intel ? high definition audio controllerd27:f0) memory address: hdbar + 0eh attribute: r/wc default value: 0000h size: 16 bits function level reset: no bit description 15:4 reserved 3:0 sdin wake enable flags ? r/w. these bits control which sdi signal(s) may generate a wake event. a 1b in the bit mask indicates that the associ ated sdin signal is enabled to generate a wake. bit 0 is used for sdi[0] bit 1 is used for sdi[1] bit 2 is used for sdi[2] bit 3 is used for sdi[3] note: these bits are in the resume well an d only cleared on a power on reset. software must not make assumptions ab out the reset state of these bits and must set them appropriately. bit description 15:4 reserved 3:0 sdin state change status flags ? r/wc. flag bits that in dicate which sdi signal(s) received a state change event. the bits are cleared by writing 1s to them. bit 0 = sdi[0] bit 1 = sdi[1] bit 2 = sdi[2] bit 3 = sdi[3] these bits are in the resume well and only cleared on a power on reset. software must not make assumptions about the reset state of these bits and must set them appropriately.
datasheet 715 integrated intel ? high definition audio controller registers 17.1.2.9 gstsglobal status register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 10h attribute: r/wc default value: 0000h size: 16 bits 17.1.2.10 outstrmpayoutput stream payload capability (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 18h attribute: ro default value: 0030h size: 16 bits 17.1.2.11 instrmpayinput stream payload capability (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 1ah attribute: ro default value: 0018h size: 16 bits bit description 15:2 reserved 1 flush status ? r/wc. this bit is set to 1 by hardware to indicate that the flush cycle initiated when the flush control bit (hdb ar + 08h, bit 1) was set has completed. software must write a 1 to clear this bit be fore the next time th e flush control bit is set to clear the bit. 0 reserved bit description 15:8 reserved 7:0 output stream payload capability (outstrmpay) ? ro : indicates maximum number of words per frame for any single outp ut stream. this measur ement is in 16 bit word quantities per 48 khz frame. 48 words (96b) is the maximum supported, therefore a value of 30h is reported in this register. software must ensure that a format which would cause more words per frame than indicated is not programmed into the output stream descriptor register. 00h = 0 words 01h = 1 word payload ? ffh = 255h word payload bit description 15:8 reserved 7:0 input stream payload capability (instrmpay) ? ro. indicates maximum number of words per frame for any single input stre am. this measurement is in 16 bit word quantities per 48 khz frame. 24 words (48b ) is the maximum supported, therefore a value of 18h is reported in this register. softwa re must ensure th at a format which would cause more words per fr ame than indicated is not programmed into the input stream descriptor register. 00h = 0 words 01h = 1 word payload ? ffh = 255h word payload
integrated intel ? high definition audio controller registers 716 datasheet 17.1.2.12 intctlinterrupt control register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 20h attribute: r/w default value: 00000000h size: 32 bits bit description 31 global interrupt enable (gie) ? r/w. global bit to enable device interrupt generation. 1 = when set to 1, the intel high definition audio function is enabled to generate an interrupt. this control is in addition to any bits in the bus specific address space, such as the inte rrupt enable bit in the pci configuration space. note: this bit is not affected by the d3 hot to d0 transition. 30 controller interrupt enable (cie) ? r/w. enables the general interrupt for controller functions. 1 = when set to 1, the controller generates an interrupt when the corresponding status bit gets set due to a response interrupt , a response buffer overrun, and state change events. note: this bit is not affected by the d3 hot to d0 transition. 29:8 reserved 7:0 stream interrupt enable (sie) ? r/w. when set to 1, th e individual streams are enabled to generate an in terrupt when the correspond ing status bits get set. a stream interrupt will be caused as a resu lt of a buffer with ioc = 1in the bdl entry being completed, or as a result of a fifo e rror (underrun or overrun) occurring. control over the generation of each of these sources is in the associated stream descriptor. the streams are numbered and the sie bits a ssigned sequentially, based on their order in the register set. bit 0 = input stream 1 bit 1 = input stream 2 bit 2 = input stream 3 bit 3 = input stream 4 bit 4 = output stream 1 bit 5 = output stream 2 bit 6 = output stream 3 bit 7 = output stream 4
datasheet 717 integrated intel ? high definition audio controller registers 17.1.2.13 intstsinterrupt status register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 24h attribute: ro default value: 00000000h size: 32 bits 17.1.2.14 walclkwall clock counter register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 30h attribute: ro default value: 00000000h size: 32 bits bit description 31 global interrupt status (gis) ? ro. this bit is an or of all the interrupt status bits in this register. note: this bit is not affected by the d3 hot to d0 transition. 30 controller interrupt status (cis) ? ro. status of general controller interrupt. 1 = interrupt condition occurred due to a response interrupt, a response buffer overrun interrupt, or a sdin state ch ange event. the exact cause can be determined by interrogating ot her registers. this bit is an or of all of the stated interrupt status bits for this register. notes: 1. this bit is set regardless of the state of the corresponding in terrupt enable bit, but a hardware interrupt will not be ge nerated unless the corresponding enable bit is set. 2. this bit is not affected by the d3 hot to d0 transition. 29:8 reserved 7:0 stream interrupt status (sis) ? ro. 1 = interrupt condition occurred on the correspon ding stream. this bit is an or of all of the stream?s interru pt status bits. note: these bits are set regardless of the stat e of the corresponding interrupt enable bits. the streams are numbered and the sie bits as signed sequentially, based on their order in the register set. bit 0 = input stream 1 bit 1 = input stream 2 bit 2 = input stream 3 bit 3 = input stream 4 bit 4 = output stream 1 bit 5 = output stream 2 bit 6 = output stream 3 bit 7 = output stream 4 bit description 31:0 wall clock counter ? ro. a 32-bit counter that is incremented on each link bit clock period and rolls over from ffff ffffh to 0000 0000h. this counter will roll over to 0 with a period of approximately 179 seconds. this counter is enabled while the bit clock bit is set to 1. software uses this counter to synchronize between multiple controllers. will be reset on controller reset.
integrated intel ? high definition audio controller registers 718 datasheet 17.1.2.15 ssyncstream synchronization register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 38h attribute: r/w default value: 00000000h size: 32 bits 17.1.2.16 corblbasecorb lowe r base address register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 40h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 31:8 reserved 7:0 stream synchronization (ssync) ? r/w. when set to 1, th ese bits block data from being sent on or received from the link. each bit controls th e associated stream descriptor (that is, bit 0 corresponds to the first stream descriptor, etc.) to synchronously start a set of dma engines, these bits are first set to 1. the run bits for the associated stream descriptors are then set to 1 to start the dma engines. when all streams are ready (fifordy =1), the associated ssync bits can all be set to 0 at the same time, and transmission or receptio n of bits to or from the link will begin together at the start of the next full link frame. to synchronously stop the streams, fist thes e bits are set, and th en the individual run bits in the stream descript or are cleared by software. if synchronization is not desired, these bits ma y be left as 0, and th e stream will simply begin running normally when the stream?s run bit is set. the streams are numbered and the sie bits a ssigned sequentially, based on their order in the register set. bit 0 = input stream 1 bit 1 = input stream 2 bit 2 = input stream 3 bit 3 = input stream 4 bit 4 = output stream 1 bit 5 = output stream 2 bit 6 = output stream 3 bit 7 = output stream 4 bit description 31:7 corb lower base address ? r/w. lower address of the command output ring buffer, allowing the corb ba se address to be assigned on any 128-b boundary. this register field must not be wr itten when the dma engine is running or the dma transfer may be corrupted. 6:0 corb lower base unimplemented bits ? ro. hardwired to 0. this required the corb to be allocated with 128b granularity to allow for cache line fetch optimizations.
datasheet 719 integrated intel ? high definition audio controller registers 17.1.2.17 corbubasecorb uppe r base address register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 44h attribute: r/w default value: 00000000h size: 32 bits 17.1.2.18 corbwpcorb write pointer register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 48h attribute: r/w default value: 0000h size: 16 bits 17.1.2.19 corbrpcorb read pointer register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 4ah attribute: r/w, ro default value: 0000h size: 16 bits bit description 31:0 corb upper base address ? r/w. upper 32 bits of the address of the command output ring buffer. this regi ster field must not be written when the dma engine is running or the dma transfer may be corrupted. bit description 15:8 reserved 7:0 corb write pointer ? r/w. software writes the last valid corb entry offset into this field in dword granularity. the dma engine fetches commands from the corb until the read pointer matches the write pointer. supports 256 corb entries (256x4b = 1kb). this register field may be writte n when the dma engine is running. bit description 15 corb read pointer reset ? r/w. software writes a 1 to this bit to reset the corb read pointer to 0 and clear any residual pr efetched commands in the corb hardware buffer within the intel high de finition audio controller. the hardware will physically update this bit to 1 when th e corb pointer reset is comple te. software must read a 1 to verify that the reset comp leted correctly. software must clear this bit back to 0 and read back the 0 to verify that the clea r completed correctly. the corb dma engine must be stopped prior to resetting the re ad pointer or else dma transfer may be corrupted. 14:8 reserved 7:0 corb read pointer (corbrp) ? ro. software reads this field to determine how many commands it can write to the corb without over-running. the value read indicates the corb read pointer offset in dw ord granularity. the offset entry read from this field has been successfully fetched by the dma controller and may be over-written by software. supports 256 corb entries (256 x 4b=1kb). this field may be read while the dma engine is running.
integrated intel ? high definition audio controller registers 720 datasheet 17.1.2.20 corbctlcorb control register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 4ch attribute: r/w default value: 00h size: 8 bits 17.1.2.21 corbstcorb status register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 4dh attribute: r/wc default value: 00h size: 8 bits 17.1.2.22 corbsizecorb size register intel ? high definition audio controllerd27:f0) memory address:hdbar + 4eh attribute: ro default value: 42h size: 8 bits bit description 7:2 reserved 1 enable corb dma engine ? r/w. 0 = dma stop 1 = dma run after software writes a 0 to this bit, th e hardware may not stop immediately. the hardware will physically update the bit to 0 when the dma engine is truly stopped. software must read a 0 from this bit to ve rify that the dma engine is truly stopped. 0 corb memory error interrupt enable ? r/w. if this bit is set, the controller will generate an interrupt if the cmei status bit (hdbar + 4dh: bit 0) is set. bit description 7:1 reserved 0 corb memory error indication (cmei) ? r/wc. 1 = controller detected an e rror in the path way between the controller and memory. this may be an ecc bit error or any other type of de tectable data error which renders the command data fetched invalid. software can clear this bit by writing a 1 to it. however, this type of error leaves the audio subsystem in an un-viab le state and typically requir es a controller reset by writing a 0 to the controller re set # bit (hdbar + 08h: bit 0). bit description 7:4 corb size capability ? ro. hardwired to 0100b indicating that the pch only supports a corb size of 256 corb entries (1024b) 3:2 reserved 1:0 corb size ? ro. hardwired to 10b which sets th e corb size to 256 entries (1024b)
datasheet 721 integrated intel ? high definition audio controller registers 17.1.2.23 rirblbaserirb lowe r base address register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 50h attribute: r/w, ro default value: 00000000h size: 32 bits 17.1.2.24 rirbubaserirb uppe r base address register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 54h attribute: r/w default value: 00000000h size: 32 bits 17.1.2.25 rirbwprirb write pointer register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 58h attribute: r/w, ro default value: 0000h size: 16 bits bit description 31:7 rirb lower base address ? r/w. lower address of the response input ring buffer, allowing the rirb base address to be assi gned on any 128-b boundary. this register field must not be written when the dma engine is running or the dma transfer may be corrupted. 6:0 rirb lower base unimplemented bits ? ro. ha rdwired to 0. this re quired the rirb to be allocated with 128-b granularity to allow for cache line fetch optimizations. bit description 31:0 rirb upper base address ? r/w. upper 32 bits of th e address of the response input ring buffer. this regi ster field must not be writ ten when the dma engine is running or the dma transfer may be corrupted. bit description 15 rirb write pointer reset ? r/w. software writes a 1 to this bit to reset the rirb write pointer to 0. the rirb dma engine mu st be stopped prior to resetting the write pointer or else dma transfer may be corrupted. this bit is always read as 0. 14:8 reserved 7:0 rirb write pointer (rirbwp) ? ro. indicates the last valid rirb entry written by the dma controller. software reads this fiel d to determine how many responses it can read from the rirb. the value read indicates the rirb write pointe r offset in 2 dword rirb entry units (since each rirb entry is 2 dwords long). supports up to 256 rirb entries (256 x 8 b = 2 kb). this register fi eld may be written when the dma engine is running.
integrated intel ? high definition audio controller registers 722 datasheet 17.1.2.26 rintcntresponse interrupt count register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 5ah attribute: r/w default value: 0000h size: 16 bits 17.1.2.27 rirbctlrirb control register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 5ch attribute: r/w default value: 00h size: 8 bits bit description 15:8 reserved 7:0 n response interrupt count ? r/w. 0000 0001b = 1 response sent to rirb ........... 1111 1111b = 255 responses sent to rirb 0000 0000b = 256 responses sent to rirb the dma engine should be stopped when changi ng this field or else an interrupt may be lost. note that each response occupies 2 dwords in the rirb. this is compared to the total number of resp onses that have been returned, as opposed to the number of frames in which there we re responses. if more than one codecs responds in one frame, th en the count is increased by the number of responses received in the frame. bit description 7:3 reserved 2 response overrun interrupt control ? r/w. if this bit is set, the hardware will generate an interrupt when the response overrun interrupt status bit (hdbar + 5dh: bit 2) is set. 1 enable rirb dma engine ? r/w. 0 = dma stop 1 = dma run after software writes a 0 to this bit, th e hardware may not stop immediately. the hardware will physically update the bit to 0 when the dma engine is truly stopped. software must read a 0 from this bit to ve rify that the dma engine is truly stopped. 0 response interrupt control ? r/w. 0 = disable interrupt 1 = generate an interrupt after n number of responses are sent to the rirb buffer or when an empty response slot is encountered on all sdi[x] inputs (whichever occurs first). the n counter is rese t when the interrupt is generated.
datasheet 723 integrated intel ? high definition audio controller registers 17.1.2.28 rirbstsrirb status register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 5dh attribute: r/wc default value: 00h size: 8 bits 17.1.2.29 rirbsizerirb size register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 5eh attribute: ro default value: 42h size: 8 bits 17.1.2.30 icimmediate command register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 60h attribute: r/w default value: 00000000h size: 32 bits bit description 7:3 reserved 2 response overrun interrupt status ? r/wc. 1 = software sets this bit to 1 when the rirb dma engine is not able to write the incoming responses to memory before a dditional incoming responses overrun the internal fifo. when the ov errun occurs, the hardware will drop the responses which overrun the buffer. an interrupt ma y be generated if the response overrun interrupt control bit is set. note that this status bit is set even if an interrupt is not enabled for this event. software clears this bi t by writing a 1 to it. 1 reserved 0 response interrupt ? r/wc. 1 = hardware sets this bit to 1 when an in terrupt has been gene rated after n number of responses are sent to the rirb buffe r or when an empty response slot is encountered on all sdi[x] inputs (whichever occurs first). note th at this status bit is set even if an interrupt is not enabled for this event. software clears this bi t by writing a 1 to it. bit description 7:4 rirb size capability ? ro. hardwired to 0100b indica ting that the pch only supports a rirb size of 256 rirb entries (2048b). 3:2 reserved 1:0 rirb size ? ro. hardwired to 10b which sets th e corb size to 256 entries (2048b). bit description 31:0 immediate command write r/w . the command to be sent to the codec using the immediate command mechanism is written to this register. the command stored in this register is sent out over the link during the next available frame after a 1 is written to the icb bit (hdbar + 68h: bit 0).
integrated intel ? high definition audio controller registers 724 datasheet 17.1.2.31 irimmediate response register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 64h attribute: ro default value: 00000000h size: 32 bits 17.1.2.32 icsimmediate command status register (intel ? high definition audio controllerd27:f0) memory address:hdbar + 68h attribute: r/w, r/wc default value: 0000h size: 16 bits bit description 31:0 immediate response read (irr) ? ro. this register contains the response received from a codec resulting from a co mmand sent using th e immediate command mechanism. if multiple codecs responded in the same time, there is no assurance as to which response will be latched. therefore, br oadcast-type commands must not be issued using the immediate command mechanism. bit description 15:2 reserved 1 immediate result valid (irv) ? r/wc. 1 = set to 1 by hardware when a new response is latched into the immediate response register (hdbar + 64). this is a status flag indicating that software may read the response from the immedi ate response register. software must clear this bit by writing a 1 to it before issuing a new command so that the software may determine when a new response has arrived. 0 immediate command busy (icb) ? r/w. when this bit is read as 0, it indicates that a new command may be issued using the immediate command mechanism. when this bit transitions from a 0 to a 1 (using softwa re writing a 1), the controller issues the command currently stored in the immediate command register to the codec over the link. when the corresponding response is latched into the immediate response register, the controller hardware sets th e irv flag and clears the icb bit back to 0. software may write this bit to a 0 if the bit fails to retu rn to 0 after a reasonable time out period. note: an immediate command must not be issued while the corb/rirb mechanism is operating, otherwise the responses conflict. this must be enforced by software.
datasheet 725 integrated intel ? high definition audio controller registers 17.1.2.33 dplbasedma position lower base address register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 70h attribute: r/w, ro default value: 00000000h size: 32 bits 17.1.2.34 dpubasedma position upper base address register (intel ? high definition audi o controllerd27:f0) memory address:hdbar + 74h attribute: r/w default value: 00000000h size: 32 bits bit description 31:7 dma position lower base address ? r/w. lower 32 bits of the dma position buffer base address. this register field must not be written when any dma engine is running or the dma transfer may be corrupted. this same address is used by the flush control and must be programmed with a valid value before the flush control bit (hdbar+08h:bit 1) is set. 6:1 dma position lower base unim plemented bits ? ro. hardwired to 0 to force the 128- byte buffer alignment for cach e line write optimizations. 0 dma position buffer enable ? r/w. 1 = controller will write the dma positions of each of the dma engi nes to the buffer in the main memory periodically (typically once per fram e). software can use this value to know what data in memory is valid data. bit description 31:0 dma position upper base address ? r/w. upper 32 bits of the dma position buffer base address. this register field must not be written when any dma engine is running or the dma transfer may be corrupted.
integrated intel ? high definition audio controller registers 726 datasheet 17.1.2.35 sdctlstream descriptor control register (intel ? high definition audio controllerd27:f0) memory address:input stream[0 ]: hdbar + 80h attribute: r/w, ro input stream[1]: hdbar + a0h input stream[2]: hdbar + c0h input stream[3]: hdbar + e0h output stream[0]: hdbar + 100h output stream[1]: hdbar + 120h output stream[2]: hdbar + 140h output stream[3]: hdbar + 160h default value: 040000h size: 24 bits bit description 23:20 stream number ? r/w. this value reflect the tag associated with the data being transferred on the link. when data controlled by this descriptor is se nt out over the link, it will have its stream number encoded on the sync signal. when an input stream is dete cted on any of the sdi signals that match this value, the data samples are loaded into fifo associated with this descriptor. note that while a single sdi input may contain data from more than one stream number, two different sdi inputs may not be configured with the same stream number. 0000 = reserved 0001 = stream 1 ........ 1110 = stream 14 1111 = stream 15 19 bidirectional direction control ? ro. this bit is only meaningful for bidirectional streams; therefore, this bit is hardwired to 0. 18 traffic priority ? ro. hardwired to 1 indicating that all streams will use vc1 if it is enabled through the pc i express* registers. 17:16 stripe control ? ro. this bit is only meaningful for input streams; therefore, this bit is hardwired to 0. 15:5 reserved 4 descriptor error interrupt enable ? r/w. 0 = disable 1 = an interrupt is generated when th e descriptor error status bit is set. 3 fifo error interrupt enable ? r/w. this bit controls whether th e occurrence of a fifo error (overrun for input or underrun for output) will cause an interrupt or not. if this bit is not set, bit 3in the status register will be set, but the interrupt will not occu r. either way, the samples will be dropped. 2 interrupt on completion enable ? r/w. this bit controls whether or not an interru pt occurs when a buffe r completes with the ioc bit set in its descriptor. if this bit is not set, bit 2 in th e status register will be set, but the interrupt will not occur. 1 stream run (run) ? r/w. 0 = dma engine associated with this input st ream will be disabled. the hardware will report a 0 in this bit when the dma engine is actually stopped. software must read a 0 from this bit before modifying related control registers or restarting the dma engine. 1 = dma engine associated with this input st ream will be enabled to transfer data from the fifo to the main memory. the ssync bi t must also be cleared in order for the dma engine to run. for outp ut streams, the cadence ge nerator is reset whenever the run bit is set.
datasheet 727 integrated intel ? high definition audio controller registers 17.1.2.36 sdstsstream descriptor status register (intel ? high definition audi o controllerd27:f0) memory address:input stream[0]: hdbar + 83h attribute: r/wc, ro input stream[1]: hdbar + a3h input stream[2]: hdbar + c3h input stream[3]: hdbar + e3h output stream[0]: hdbar + 103h output stream[1]: hdbar + 123h output stream[2]: hdbar + 143h output stream[3]: hdbar + 163h default value: 00h size: 8 bits 0 stream reset (srst) ? r/w. 0 = writing a 0 causes the corresponding st ream to exit reset. when the stream hardware is ready to begin operation, it wi ll report a 0 in this bit. software must read a 0 from this bit before acce ssing any of the stream registers. 1 = writing a 1 causes the corresponding stre am to be reset. the stream descriptor registers (except the srst bit itself) an d fifos for the corresponding stream are reset. after the stream hardware has completed sequencing into the reset state, it will report a 1 in this bit. software must read a 1 from this bit to verify that the stream is in reset. the run bit must be cleare d before srst is asserted. bit description bit description 7:6 reserved 5 fifo ready (fifordy) ? ro. for output streams, the controller hardware will set this bit to 1 while the output dma fifo contains enough data to maintain the stream on the link. this bit defaults to 0 on rese t because the fifo is cleared on a reset. for input streams, the controller hardware wi ll set this bit to 1 when a valid descriptor is loaded and the engine is re ady for the run bit to be set. 4 descriptor error ? r/wc. 1 = a serious error occurred duri ng the fetch of a descriptor. this could be a result of a master abort, a parity or ecc error on the bus, or any other error which renders the current buffe r descriptor or buffer de scriptor list useless. this error is treated as a fatal stream error, as the stream ca nnot continue running. the run bit will be cleared and the stre am will stopped. software may attempt to restart the stream engine afte r addressing the cause of the error and writing a 1 to this bit to clear it. 3 fifo error ? r/wc. 1 = fifo error occurred. this bit is set even if an interrupt is no t enabled. the bit is cleared by writing a 1 to it. for an input stream, this indi cates a fifo overrun occurring while the run bit is set. when this happens, the fifo pointers do no t increment and the incoming data is not written into the fifo, thereby being lost. for an output stream, this in dicates a fifo underrun when there are still buffers to send. the hardware should not transmit anythi ng on the link for the associated stream if there is not valid data to send. 2 buffer completion interrupt status ? r/wc. this bit is set to 1 by the hardware af ter the last sample of a buffer has been processed, and if the interrupt on completi on bit is set in the command byte of the buffer descriptor. it remains active until softwa re clears it by writing a 1 to it. 1:0 reserved
integrated intel ? high definition audio controller registers 728 datasheet 17.1.2.37 sdlpibstream descriptor link position in buffer register (intel ? high definition audio controllerd27:f0) memory address:input stream[0]: hdbar + 84h attribute: ro input stream[1]: hdbar + a4h input stream[2]: hdbar + c4h input stream[3]: hdbar + e4h output stream[0]: hdbar + 104h output stream[1]: hdbar + 124h output stream[2]: hdbar + 144h output stream[3]: hdbar + 164h default value: 00000000h size: 32 bits 17.1.2.38 sdcblstream descriptor cyclic buffer length register (intel ? high definition audio controllerd27:f0) memory address:input stream[0]: hdbar + 88h attribute: r/w input stream[1]: hdbar + a8h input stream[2]: hdbar + c8h input stream[3]: hdbar + e8h output stream[0]: hdbar + 108h output stream[1]: hdbar + 128h output stream[2]: hdbar + 148h output stream[3]: hdbar + 168h default value: 00000000h size: 32 bits bit description 31:0 link position in buffer ? ro. indicates the number of bytes that have been received off the link. this register will count from 0 to the value in the cyclic buffer length register and then wrap to 0. bit description 31:0 cyclic buffer length ? r/w. indicates the number of bytes in the complete cyclic buffer. this register represen ts an integer number of samp les. link position in buffer will be reset when it reaches this value. software may only write to this register afte r global reset, controll er reset, or stream reset has occurred. this value should be only modified when the run bit is 0. once the run bit has been set to enable the engine, software must not write to this register until after the next reset is asserted , or transfer may be corrupted.
datasheet 729 integrated intel ? high definition audio controller registers 17.1.2.39 sdlvistream descriptor last valid index register (intel ? high definition audi o controllerd27:f0) memory address:input stream[0]: hdbar + 8ch attribute: r/w input stream[1]: hdbar + ach input stream[2]: hdbar + cch input stream[3]: hdbar + ech output stream[0]: hdbar + 10ch output stream[1]: hdbar + 12ch output stream[2]: hdbar + 14ch output stream[3]: hdbar + 16ch default value: 0000h size: 16 bits 17.1.2.40 sdfifowstream descript or fifo watermark register (intel ? high definition audi o controllerd27:f0) memory address:input stream[0]: hdbar + 8eh attribute:ro input stream[1]: hdbar + aeh input stream[2]: hdbar + ceh input stream[3]: hdbar + eeh output stream[0]: hdbar + 10eh output stream[1]: hdbar + 12eh output stream[2]: hdbar + 14eh output stream[3]: hdbar + 16eh default value: 0004h size: 16 bits bit description 15:8 reserved 7:0 last valid index ? r/w. the value written to this re gister indicates the index for the last valid buffer descriptor in bdl. after the controller has processe d this desc riptor, it will wrap back to the first descriptor in the list and continue processing. this field must be at least 1; that is, there must be at least 2 valid entries in the buffer descriptor list before dma operations can begin. this value should only modified when the run bit is 0. bit description 15:3 reserved 2:0 fifo watermark (fifow) ? ro. indicates the minimum number of bytes accumulated/free in the fifo be fore the controller will star t a fetch/eviction of data. the hd audio controller hardwires the fifo wa termark to either 32 b or 64 b based on the number of bytes per frame for the conf igured input stream. 100 = 32 b (default) 101 = 64 b others = unsupported note: when the bit field is prog rammed to an unsupported size, the hardware sets itself to the default value. software must read the bit fi eld to test if the value is supported after setting the bit field.
integrated intel ? high definition audio controller registers 730 datasheet 17.1.2.41 sdfifosstream descriptor fifo size register C input streams (intel ? high definition audio controllerd27:f0) memory address:input stream[0]: hdbar + 90h attribute: ro input stream[1]: hdbar + b0h input stream[2]: hdbar + d0h input stream[3]: hdbar + f0h default value: 0000h size:16 bits 17.1.2.42 sdfifosstream descriptor fifo size register C output streams (intel ? high definition audio controllerd27:f0) memory address:output stream[0]: hdbar + 110h attribute: r/w output stream[1]: hdbar + 130h output stream[2]: hdbar + 150h output stream[3]: hdbar + 170h default value: 0000h size: 16 bits bit description 15:0 fifo size ?ro. indicates the maximum number of bytes that could be evicted by the controller at one time. this is the maxi mum number of bytes that may have been received from the link but not yet dma?d into memory, and is also the maximum possible value that the picb coun t will increase by at one time. the fifo size is calculated based on factors including th e stream format programmed in sdfmt register. as the default value is zero, sw must write to the respective sdfmt register to kick of the fifo size calculation, and read back to find out the hw allocated fifo size. bit description 15:0 fifo size ? r/w. indicates the maximum number of bytes that could be fetched by the controller at one time. this is the maximum number of bytes that may have been dma?d into memory but not yet transmitted on the link, and is also the maximum possible value that the picb coun t will increase by at one time. the fifo size is calculated based on factors including th e stream format programmed in sdfmt register. as the default value is zero, sw must write to the respective sdfmt register to kick of the fifo size calculation, and read back to find out the hw allocated fifo size.
datasheet 731 integrated intel ? high definition audio controller registers 17.1.2.43 sdfmtstream descriptor format register (intel ? high definition audi o controllerd27:f0) memory address:input stream[0]: hdbar + 92h attribute: r/w input stream[1]: hdbar + b2h input stream[2]: hdbar + d2h input stream[3]: hdbar + f2h output stream[0]: hdbar + 112h output stream[1]: hdbar + 132h output stream[2]: hdbar + 152h output stream[3]: hdbar + 172h default value: 0000h size: 16 bits bit description 15 reserved 14 sample base rate ? r/w 0 = 48 khz 1 = 44.1 khz 13:11 sample base rate multiple ? r/w 000 = 48 khz, 44.1 khz or less 001 = x2 (96 khz, 88.2 khz, 32 khz) 010 = x3 (144 khz) 011 = x4 (192 khz, 176.4 khz) others = reserved. 10:8 sample base rate devisor ? r/w. 000 = divide by 1(48 khz, 44.1 khz) 001 = divide by 2 (24 khz, 22.05 khz) 010 = divide by 3 (16 khz, 32 khz) 011 = divide by 4 (11.025 khz) 100 = divide by 5 (9.6 khz) 101 = divide by 6 (8 khz) 110 = divide by 7 111 = divide by 8 (6 khz) 7 reserved 6:4 bits per sample (bits) ? r/w. 000 = 8 bits. the data will be packed in memory in 8-bit containers on 16-bit boundaries 001 = 16 bits. the data will be packed in memory in 16-bit co ntainers on 16-bit boundaries 010 = 20 bits. the data will be packed in memory in 32-bit containers on 32-bit boundaries 011 = 24 bits. the data will be packed in memory in 32-bit co ntainers on 32-bit boundaries 100 = 32 bits. the data will be packed in memory in 32-bit co ntainers on 32-bit boundaries others = reserved. 3:0 number of channels (chan) ? r/w. indicates number of channels in each frame of the stream. 0000 =1 0001 =2 ........ 1111 =16
integrated intel ? high definition audio controller registers 732 datasheet 17.1.2.44 sdbdplstream descriptor buffer descriptor list pointer lower base address register (intel ? high definition audio controllerd27:f0) memory address:input stream[0]: hdbar + 98h attribute: r/w,ro input stream[1]: hdbar + b8h input stream[2]: hdbar + d8h input stream[3]: hdbar + f8h output stream[0]: hdbar + 118h output stream[1]: hdbar + 138h output stream[2]: hdbar + 158h output stream[3]: hdbar + 178h default value: 00000000h size: 32 bits 17.1.2.45 sdbdpustream descriptor buffer descriptor list pointer upper base address register (intel ? high definition audio controllerd27:f0) memory address:input stream[0]: hdbar + 9ch attribute:r/w input stream[1]: hdbar + bch input stream[2]: hdbar + dch input stream[3]: hdbar + fch output stream[0]: hdbar + 11ch output stream[1]: hdbar + 13ch output stream[2]: hdbar + 15ch output stream[3]: hdbar + 17ch default value: 00000000h size: 32 bits bit description 31:7 buffer descriptor list po inter lower base address ? r/w. lower address of the buffer descriptor list. this valu e should only be modified when the run bit is 0, or dma transfer may be corrupted. 6:0 hardwired to 0 forcing alignment on 128-b boundaries. bit description 31:0 buffer descriptor list pointer upper base address ? r/w. upper 32-bit address of the buffer descriptor list. th is value should only be modified when the run bit is 0, or dma transfer may be corrupted.
datasheet 733 integrated intel ? high definition audio controller registers 17.2 integrated digital display audio registers and verb ids the integrated digital display ports providing audio support provide the necessary registers and interfaces for software, per th e intel high definition audio specification. 17.2.1 configuration default register the configuration default is a 32-bit register required in each pin widget. it is used by software as an aid in determining the co nfiguration of jacks and devices attached to the codec. at the time the codec is first powe red on, this register is internally loaded with default values indicating the typical sy stem use of this particular pin/jack. after this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events. its state need not be preserved across power level changes. command options data structure the configuration default register is defined as shown in ta b l e 1 7 - 4 . port connectivity[1:0] indicates the external connectivity of the pin complex. software can use this value to know what pin complexes are connected to jacks, internal devices, or not connected at all. the encodings of the port connectivity field are defined in table 17-5 . table 17-3. configuration default verb id payload(8 bits) response bits (32 bits) get f1ch 0 config bits [31:0] set 1 71ch config bits [7:0] 0 set 2 71dh config bits [15:8] 0 set 3 71eh config bits [23:16] 0 set 4 71fh config bits [31:24] 0 table 17-4. configuration data structure bits description 31:30 port connectivity 29:24 location 23:20 default device 19:16 connection type 15:12 color 11:8 misc 7:4 default association 3:0 sequence
integrated intel ? high definition audio controller registers 734 datasheet location[5:0] indicates the physical location of the jack or device to which the pin complex is connected. this allows software to indicate, for instance, that the device is the ?front panel headphone jack? as opposed to rear panel connections. the encodings of the default device field are defined in table 17-6 . the location field is divided into two pieces, the upper bits [5:4] and the lower bits [3:0]. the upper bits [5:4] provide a gross location, such as ?external? (on the primary system chassis, accessible to the user), ?i nternal? (on the motherboard, not accessible without opening the box), on a separate chassis (such as a mobile box), or other. the lower bits [3:0] provide a geometric loca tion, such as ?front,? ?left,? etc., or provide special encodings to indicate locations such as mobile lid mounted microphones. an ?x? in ta b l e 1 7 - 6 indicates a combination that software should support. while all combinations are permi tted, they are not all likely or expected. default device[3:0] indicates the intended use of the jack or device. this can indicate either the label on the jack or the de vice that is hardwired to the port, as with integrated speakers and the like. the encodi ngs of the default device field are defined in table 17-7 . connection type[3:0] indicates the type of physical connection, such as a 1/8-inch stereo jack or an optical digital connector, etc. software can use this information to provide helpful user interface descriptions to the user or to modify reported codec capabilities based on the capabilities of the physical transport external to the codec. the encodings of the connection type field are defined in table 17-8 . color[3:0] indicates the color of the physical jack for use by software. encodings for the color field are defined in table 17-9 . misc[3:0] is a bit field used to indicate other information about the jack. currently, only bit 0 is defined. if bit 0 is set, it in dicates that the jack has no presence detect capability, so even if a pin complex indica tes that the codec hardware supports the presence detect functionality on the jack, the external circuitry is not capable of supporting the functionality. the bit definitions for the misc field are in table 17-10 . default association and sequence are used together by software to group pin complexes (and therefore jacks) together into functional blocks to support multichannel operation. software may assume that all jacks with the same association number are intended to be grouped together, for instance to provide six channel analog output. the default association can also be used by software to prioritize resource allocation in constrained situations. lower default association values would be higher in priority for resources such as processing nodes or input and output converters. note that this is the default association only, and software can override this value if required, in particular if the user provides addition al information about the particular system configuration. a value of 0000b is reserved and should not be used. software may interpret this value to indicate that the pi n configuration data has not been properly initialized. a value of 1111b is a special va lue indicating that the association has the lowest priority. multiple different pin comp lexes may share this value, and each is intended to be exposed as independent devices. sequence indicates the order of the jacks in the association group. the lowest numbered jack in the association group sh ould be assigned the lowest numbered channels in the stream, etc. the numbers need not be sequential within the group, only the order matters. sequence numbers within a set of default associations must be unique.
datasheet 735 integrated intel ? high definition audio controller registers table 17-5. port connectivity value value 00b the port complex is connected to a jack 01b no physical connection for port 10b a fixed function device (integrated speaker, integrated mic etc) is attached 11b both a jack and an in ternal device attached table 17-6. location bits 5:4 00b external of primary chassis 01b internal 10b separate chassis 11b other bits 3:0 0h xxxx 1h:rear xx 2h:front xx 3h:left xx 4h:right xx 5h:top xx 6h:bottom xx x 7h:special x (rear panel) x (riser) x (mobile lid- inside) 8h:special x (drive bay) x (digital display) x (mobile lid- outside) 9h:special x (atapi) ah-fh:reserved
integrated intel ? high definition audio controller registers 736 datasheet table 17-7. default device default device encoding line out 0h speaker 1h hp out 2h cd 3h s/pdif* out 4h digital other side 5h modem line side 6h modem hand set side 7h line in 8h aux 9h mic in ah te l e p h o ny b h s/pdif in ch digital other in dh reserved eh other fh table 17-8. connection type connection type encoding unknown 0h 1/8? stereo/mono 1h 1/4? stereo/mono 2h atapi internal 3h rca 4h optical 5h other digital 6h other analog 7h multichannel analog (din) 8h xlr/professional 9h rj-11 (modem) ah combination bh other fh
datasheet 737 integrated intel ? high definition audio controller registers config default register needs to be programme d in bios to enable or disable the audio on the port. more details of the register an d other audio registers? programming can be found in high definition audio specific ation 1.0a at www.intel.com/standards. table 17-9. color color encoding unknown 0h black 1h grey 2h blue 3h green 4h red 5h orange 6h yellow 7h purple 8h pink 9h reserved a?dh white eh other fh table 17-10. misc misc bit reserved 3 reserved 2 reserved 1
integrated intel ? high definition audio controller registers 738 datasheet
datasheet 739 smbus controller registers (d31:f3) 18 smbus controller registers (d31:f3) 18.1 pci configuration registers (smbusd31:f3) note: registers that are not shown should be treated as reserved (see section 9.2 for details). 18.1.1 vidvendor identificati on register (smbusd31:f3) address: 00h ? 01h attribute: ro default value: 8086h size: 16 bits table 18-1. smbus controller pci re gister address map (smbusd31:f3) offset mnemonic register name default attribute 00h?01h vid vendor identification 8086 ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0280h ro 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 05h ro 0bh bcc base class code 0ch ro 10h smbmbar0 memory base address register 0 (bit 31:0) 00000004h r/w, ro 14h smbmbar1 memory based address register 1 (bit 63:32) 00000000h r/w 20h?23h smb_base smbus base address 00000001h r/w, ro 2ch?2dh svid subsystem vendor identification 0000h ro 2eh?2fh sid subsystem identification 0000h r/wo 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description ro 40h hostc host configuration 00h r/w bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel
smbus controller registers (d31:f3) 740 datasheet 18.1.2 diddevice identificati on register (smbusd31:f3) address: 02h ? 03h attribute: ro default value: see bit description size: 16 bits 18.1.3 pcicmdpci command register (smbusd31:f3) address: 04h ? 05h attributes: ro, r/w default value: 0000h size: 16 bits bit description 15:0 device id ? ro. this is a 16-bit value assigned to the pch smbus controller. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the did register. bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = enable 1 = disables smbus to assert its pirqb# signal. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. 0 = enables serr# generation. 1 = disables serr# generation. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? r/w. 0 = disable 1 = sets detected parity error bit (d31:f3:06 , bit 15) when a parity error is detected. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle en able (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? ro. hardwired to 0. 1 memory space enable (mse) ? r/w. 0 = disables memory mapped config space. 1 = enables memory mapped config space. 0 i/o space enable (iose) ? r/w. 0 = disable 1 = enables access to the smbus i/o space registers as defined by the base address register.
datasheet 741 smbus controller registers (d31:f3) 18.1.4 pcistspci status register (smbusd31:f3) address: 06h ? 07h attributes: ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 to the bit has no effect. 18.1.5 ridrevision identificati on register (smbusd31:f3) offset address: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = parity error detected. 14 signaled system error (sse) ? r/wc. 0 = no system error detected. 1 = system error detected. 13 received master abort (rma) ? ro. hardwired to 0. 12 received target abort (rta) ? ro. hardwired to 0. 11 signaled target abort (sta) ? ro. hardwired to 0. 10:9 devsel# timing status (devt) ? ro. this 2-bit field defines the timing for devsel# assertion for positive decode. 01 = medium timing. 8 data parity error detected (d ped) ? ro. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (udf) ? ro. hardwired to 0. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. hardwired to 0 because there are no capability list structures in this function 3 interrupt status (ints) ? ro. this bit indicates that an interrupt is pe nding. it is independent from the state of the interrupt enable bit in the pci command register. 2:0 reserved bit description 7:0 revision id ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register.
smbus controller registers (d31:f3) 742 datasheet 18.1.6 piprogramming interfac e register (smbusd31:f3) offset address: 09h attribute: ro default value: 00h size: 8 bits 18.1.7 sccsub class code register (smbusd31:f3) address offset: 0ah attributes: ro default value: 05h size: 8 bits 18.1.8 bccbase class code register (smbusd31:f3) address offset: 0bh attributes: ro default value: 0ch size: 8 bits 18.1.9 smbmbar0d31_f3_smbus memory base address 0 register (smbusd31:f3) address offset: 10?13h attributes: r/w, ro default value: 00000004h size: 32 bits bit description 7:0 reserved bit description 7:0 sub class code (scc) ? ro. 05h = smbus serial controller bit description 7:0 base class code (bcc) ? ro. 0ch = serial controller. bit description 31:8 base address ? r/w. provides the 32 byte system memory base address for the pch smb logic. 7:4 reserved 3 prefetchable (pref) ? ro. hardwired to 0. indicates that smbmbar is not pre- fetchable. 2:1 address range (addrng) ? ro. indicates that this smbmbar can be located anywhere in 64 bit address space. hardwired to 10b. 0 memory space indicator ? ro. this read-only bit always is 0, indicating that the smb logic is memory mapped.
datasheet 743 smbus controller registers (d31:f3) 18.1.10 smbmbar1d31_f3_smbus memory base address 1 register (smbusd31:f3) address offset: 14h?17h attributes: r/w default value: 00000000h size: 32 bits 18.1.11 smb_basesmbus ba se address register (smbusd31:f3) address offset: 20 ? 23h attribute: r/w, ro default value: 00000001h size: 32-bits 18.1.12 svidsubsystem vendor identification register (smbusd31:f2/f4) address offset: 2ch ? 2dh attribute: ro default value: 0000h size: 16 bits lockable: no power well: core bit description 31:0 base address ? r/w. provides bits 63:32 system memory base address for the pch smb logic. bit description 31:16 reserved ? ro 15:5 base address ? r/w. this field provides the 32-b yte system i/o base address for the pch?s smb logic. 4:1 reserved ? ro 0 io space indicator ? ro. hardwired to 1 in dicating that the smb logic is i/o mapped. bit description 15:0 subsystem vendor id (svid) ? ro. the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide svid register. note: software can write to this register only once per core well re set. writes should be done as a single 16-bit cycle.
smbus controller registers (d31:f3) 744 datasheet 18.1.13 sidsubsystem identification register (smbusd31:f2/f4) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 18.1.14 int_lninterrupt line register (smbusd31:f3) address offset: 3ch attributes: r/w default value: 00h size: 8 bits 18.1.15 int_pninterrupt pin register (smbusd31:f3) address offset: 3dh attributes: ro default value: see description size: 8 bits bit description 15:0 subsystem id (sid) ? r/wo. the sid register, in combination with the svid register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide sid register. note: software can write to this register only once per core well re set. writes should be done as a single 16-bit cycle. bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the pch. it is to communicate to software the interrupt line that the interrupt pin is connected to pirqb#. bit description 7:0 interrupt pin (int_pn) ? ro. this reflects the valu e of d31ip.smip in chipset configuration space.
datasheet 745 smbus controller registers (d31:f3) 18.1.16 hostchost configurat ion register (smbusd31:f3) address offset: 40h attribute: r/w default value: 00h size: 8 bits bit description 7:4 reserved 3 ssreset C soft smbus reset ? r/w. 0 = the hw will reset this bit to 0 wh en smbus reset operation is completed. 1 = the smbus state machine and logic in the pch is reset. 2 i 2 c_en ? r/w. 0 = smbus behavior. 1 = the pch is enabled to communicate with i 2 c devices. this will change the formatting of some commands. 1 smb_smi_en ? r/w. 0 = smbus interrupts will not generate an smi#. 1 = any source of an smb interrupt will inst ead be routed to gene rate an smi#. refer to section 5.20.4 (interrupts / smi#). this bit needs to be set fo r smbalert# to be enabled. 0 smbus host enable (hst_en) ? r/w. 0 = disable the smbus host controller. 1 = enable. the smb host cont roller interface is enable d to execute commands. the intren bit (offset smb_base + 02h, bit 0) needs to be enabled for the smb host controller to interrupt or smi#. note that the smb host controller will not respond to any new requests until all inte rrupt requests have been cleared.
smbus controller registers (d31:f3) 746 datasheet 18.2 smbus i/o and memory mapped i/o registers the smbus registers (see ta b l e 1 8 - 2 ) can be accessed through i/o bar or memory bar registers in pci configuration space. the of fsets are the same for both i/o and memory mapped i/o registers. table 18-2. smbus i/o and memory mapped i/o register address map smb_base + offset mnemonic register name default attribute 00h hst_sts host status 00h r/wc, ro 02h hst_cnt host control 00h r/w, wo 03h hst_cmd host command 00h r/w 04h xmit_slva transmit slave address 00h r/w 05h hst_d0 host data 0 00h r/w 06h hst_d1 host data 1 00h r/w 07h host_block_db host block data byte 00h r/w 08h pec packet e rror check 00h r/w 09h rcv_slva receive slave address 44h r/w 0ah?0bh slv_data receive slave data 0000h ro 0ch aux_sts auxiliary status 00h r/wc, ro 0dh aux_ctl auxiliary control 00h r/w 0eh smlink_pin_ctl smlink pin control (tco compatible mode) see register description r/w, ro 0fh smbus_pin_ctl smbus pin control see register description r/w, ro 10h slv_sts slave status 00h r/wc 11h slv_cmd slave command 00h r/w 14h notify_daddr notify device address 00h ro 16h notify_dlow notify data low byte 00h ro 17h notify_dhigh notify data high byte 00h ro
datasheet 747 smbus controller registers (d31:f3) 18.2.1 hst_stshost status register (smbusd31:f3) register offset: smb_base + 00h attribute: r/wc, ro default value: 00h size: 8-bits all status bits are set by hardware and cleared by the software writing a one to the particular bit position. writing a 0 to any bit position has no effect. bit description 7 byte done status (ds) ? r/wc. 0 = software can clear this by writing a 1 to it. 1 = host controller received a byte (for bl ock read commands) or if it has completed transmission of a byte (for block write commands) when the 32- byte buffer is not being used. note that this bit will be set, even on the last byte of the transfer. this bit is not set when transmission is due to the lan interface heartbeat. this bit has no meaning for block transf ers when the 32-byte buffer is enabled. note: when the last byte of a block message is received, the host controller will set this bit. however, it will not immediately set the intr bit (bit 1 in this register). when the interrupt handle r clears the ds bit, the message is considered complete, and the host controller will then set the intr bit (and generate another interrupt). thus, for a block mess age of n bytes, the pch will generate n+1 interrupts. the interrupt handler needs to be implemented to handle these cases. when not using the 32 byte buffer, hardware will drive the smbclk signal low when the ds bit is set until sw clears the bit. this includes the last byte of a transfer. software must cl ear the ds bit before it can clear the busy bit. 6 inuse_sts ? r/w. this bit is used as semaphore among various independent software threads that may need to use the pch?s smbus logi c, and has no other effect on hardware. 0 = after a full pci reset, a read to this bit returns a 0. 1 = after the first read, subseque nt reads will return a 1. a write of a 1 to this bit will reset the next read value to 0. writing a 0 to this bit has no effect. software can poll this bit until it reads a 0, and will th en own the usage of the host controller. 5 smbalert_sts ? r/wc. 0 = interrupt or smi# was not generated by smbalert#. software clears this bit by writing a 1 to it. 1 = the source of the interrupt or smi# wa s the smbalert# signal. this bit is only cleared by software writing a 1 to the bit position or by rsmrst# going low. if the signal is programmed as a gp io, then this bit will never be set. 4 failed ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = the source of the interrupt or smi# was a failed bus transaction. this bit is set in response to the kill bit being set to terminate the host transaction. 3 bus_err ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = the source of the interrupt of smi# was a transaction collision. 2 dev_err ? r/wc. 0 = software clears this bit by writing a 1 to it. the pch will then deassert the interrupt or smi#. 1 = the source of the interrupt or sm i# was due to one of the following: ? invalid command field, ? unclaimed cycle (host initiated), ? host device time-out error.
smbus controller registers (d31:f3) 748 datasheet 18.2.2 hst_cnthost control register (smbusd31:f3) register offset: smb_base + 02h attribute: r/w, wo default value: 00h size: 8-bits note: a read to this register will clear th e byte pointer of the 32-byte buffer. 1 intr ? r/wc. this bit can only be set by te rmination of a command. intr is not dependent on the intren bit (offset smb_base + 02h, bit 0) of the host controller register (offset 02h). it is only dependent on the te rmination of the command. if the intren bit is not set, then the intr bit will be set, although the interrupt will not be generated. software can poll the intr bit in this non-interrupt case. 0 = software clears this bit by writing a 1 to it. the pch then deasserts the interrupt or smi#. 1 = the source of the interrupt or smi# was the successful completion of its last command. 0 host_busy ? r/wc. 0 = cleared by the pch when the current transaction is completed. 1 = indicates that the pch is running a command from the host interface. no smb registers should be accessed while this bit is set, except the block data byte register. the block data byte register can be accessed when th is bit is set only when the smb_cmd bits in the host cont rol register are programmed for block command or i 2 c read command. this is necessary in order to check the done_sts bit. bit description bit description 7 pec_en ? r/w. 0 = smbus host controller does not perform the transa ction with the pec phase appended. 1 = causes the host controller to perform the smbus transaction with the packet error checking phase appended. for writes, the value of the pec byte is transferred from the pec register. for reads, the pec byte is loaded in to the pec register. this bit must be written prior to the write in which the start bit is set. 6 start ? wo. 0 = this bit will always return 0 on read s. the host_busy bit in the host status register (offset 00h) can be used to identify when the pch has finished the command. 1 = writing a 1 to this bit initiates the co mmand described in the smb_cmd field. all registers should be setup prior to writing a 1 to this bit position. 5 last_byte ? wo. this bit is used for block read commands. 1 = software sets this bit to indicate that the next byte will be the last byte to be received for the block. this causes the pch to send a nack (instead of an ack) after receiving the last byte. note: once the second_to_sts bit in tco 2_sts register (d31:f0, tcobase+6h, bit 1) is set, the last_byte bit also ge ts set. while the second_to_sts bit is set, the last_byte bit cannot be cleare d. this prevents the pch from running some of the smbus commands (block read/write, i 2 c read, block i 2 c write).
datasheet 749 smbus controller registers (d31:f3) 4:2 smb_cmd ? r/w. the bit encoding below indi cates which command the pch is to perform. if enabled, the pch will generate an interrupt or smi# when the command has completed if the value is for a non-suppo rted or reserved command, the pch will set the device error (dev_err) status bit (o ffset smb_base + 00h, bit 2) and generate an interrupt when the start bit is set. th e pch will perform no command, and will not operate until dev_err is cleared. 000 = quick : the slave address and read/write value (bit 0) are stored in the transmit slave address register. 001 = byte : this command uses the transmit slave address and command registers. bit 0 of the slave address register determines if th is is a read or write command. 010 = byte data : this command uses the transmit slave address, command, and data0 registers. bit 0 of the slave address register determines if this is a read or write command. if it is a read, the da ta0 register will contain the read data. 011 = word data : this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave address register determines if this is a read or write command. if it is a read, after the command completes, the data0 and data1 registers wi ll contain the read data. 100 = process call: this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave address register determines if this is a read or write command. after the co mmand completes, the data0 and data1 registers will contain the read data. 101 = block : this command uses the transmit slave address, command, data0 registers, and the block data byte regist er. for block write, the count is stored in the data0 register and indicates how ma ny bytes of data will be transferred. for block reads, the count is received an d stored in the data0 register. bit 0 of the slave address register selects if this is a read or write command. for writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. 110 = i 2 c read : this command uses the transmit slave address, command, data0, data1 registers, and the block data byte register. the read data is stored in the block data byte register. the pch co ntinues reading data until the nak is received. 111 = block process: this command uses the transm it slave address, command, data0 and the block data byte register. fo r block write, the count is stored in the data0 register and indicates how many bytes of data will be transferred. for block read, the count is received and stored in the data0 register. bit 0 of the slave address register al ways indicate a write comm and. for writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. note: e32b bit in the auxiliary control register must be set for this command to work. 1 kill ? r/w. 0 = normal smbus host controller functionality. 1 = kills the current ho st transaction taking place, se ts the failed status bit, and asserts the interrupt (or smi#). this bit, once se t, must be cleare d by software to allow the smbus host controll er to function normally. 0 intren ? r/w. 0 = disable. 1 = enable the generation of an interrup t or smi# upon the completion of the command. bit description
smbus controller registers (d31:f3) 750 datasheet 18.2.3 hst_cmdhost command register (smbusd31:f3) register offset: smb_base + 03h attribute: r/w default value: 00h size: 8 bits 18.2.4 xmit_slvatransmit slave address register (smbusd31:f3) register offset: smb_base + 04h attribute: r/w default value: 00h size: 8 bits this register is transmitted by the host co ntroller in the slave address field of the smbus protocol. 18.2.5 hst_d0host data 0 register (smbusd31:f3) register offset: smb_base + 05h attribute: r/w default value: 00h size: 8 bits 18.2.6 hst_d1host data 1 register (smbusd31:f3) register offset: smb_base + 06h attribute: r/w default value: 00h size: 8 bits bit description 7:0 this 8-bit field is transmitted by the host controller in the command field of the smbus protocol during the execution of any command. bit description 7:1 address ? r/w. this field provides a 7-bit address of the targeted slave. 0 rw ? r/w. direction of the host transfer. 0 = write 1 = read bit description 7:0 data0/count ? r/w. this field contains the 8-bit data sent in the data0 field of the smbus protocol. for block write commands, this register reflects the number of bytes to transfer. this register should be progra mmed to a value between 1 and 32 for block counts. a count of 0 or a count above 32 will result in unpredicta ble behavior. the host controller does not check or log invalid block counts. bit description 7:0 data1 ? r/w. this 8-bit register is transm itted in the data1 field of the smbus protocol during the execution of any command.
datasheet 751 smbus controller registers (d31:f3) 18.2.7 host_block_dbhost bl ock data byte register (smbusd31:f3) register offset: smb_base + 07h attribute: r/w default value: 00h size: 8 bits 18.2.8 pecpacket error check (pec) register (smbusd31:f3) register offset: smb_base + 08h attribute: r/w default value: 00h size: 8 bits bit description 7:0 block data (bdta) ? r/w. this is either a register, or a pointer into a 32-byte block array, depending upon whether the e32b bit is set in the auxiliary control register. when the e32b bit (offset sm b_base + 0dh, bit 1) is cl eared, this is a register containing a byte of data to be sent on a block write or read from on a block read. when the e32b bit is set, reads and writes to this register are us ed to access the 32- byte block data storage array. an internal index pointer is used to address the array, which is reset to 0 by readin g the hctl register (offset 02h). the index pointer then increments automatically upon each access to this register. the transfer of block data into (read) or out of (write) this storage array during an smbus transaction always starts at index address 0. when the e2b bit is set, for writes, software will write up to 32-bytes to this register as part of the setup for the co mmand. after the host controller has sent the address, command, and byte count fields, it will send the bytes in the sram pointed to by this register. when the e2b bit is cleared for writes, software will place a single by te in this register. after the host controller has sent the address, command, an d byte count fi elds, it will send the byte in this register. if there is more data to send, software will write the next series of bytes to the sram pointed to by th is register and clear the done_sts bit. the controller will then send th e next byte. during the time between the last byte being transmitted to the next byte being transmitted, the controller will insert wait-states on the interface. when the e2b bit is set for reads, after rece iving the byte count into the data0 register, the first series of data bytes go into the sr am pointed to by this register. if the byte count has been exhausted or the 32-byte sr am has been filled, the controller will generate an smi# or interrupt (depending on configuration) and set the done_sts bit. software will then read the data. during th e time between when the last byte is read from the sram to when the done_sts bit is cleared, the controller will insert wait- states on the interface. bit description 7:0 pec_data ? r/w. this 8-bit register is written with the 8-bit crc valu e that is used as the smbus pec data prior to a write transaction. for read transactions, the pec data is loaded from the smbus into this register an d is then read by software. software must ensure that the inuse_sts bit is properly ma intained to avoid having this field over- written by a write transaction following a read transaction.
smbus controller registers (d31:f3) 752 datasheet 18.2.9 rcv_slvareceive slave address register (smbusd31:f3) register offset: smb_base + 09h attribute: r/w default value: 44h size: 8 bits lockable: no power well: resume 18.2.10 slv_datareceive slave data register (smbusd31:f3) register offset: smb_base + 0ah?0bh attribute: ro default value: 0000h size: 16 bits lockable: no power well: resume this register contains the 16-bit data value written by the external smbus master. the processor can then read the value from this re gister. this register is reset by rsmrst#, but not pltrst#. 18.2.11 aux_stsauxiliary stat us register (smbusd31:f3) register offset: smb_base + 0ch attribute: r/wc, ro default value: 00h size: 8 bits lockable: no power well: resume bit description 7 reserved 6:0 slave_addr ? r/w. this field is the slave addres s that the pch decodes for read and write cycles. the default is not 0, so the sm bus slave interface can respond even before the processor comes up (or if the processor is dead). this regi ster is cleared by rsmrst#, but not by pltrst#. bit description 15:8 data message byte 1 (data_msg1) ? ro. see section 5.20.7 for a discussion of this field. 7:0 data message byte 0 (data_msg0) ? ro. see section 5.20.7 for a discussion of this field. bit description 7:2 reserved 1 smbus tco mode (stco) ? ro. this bit reflects the st rap setting of tco compatible mode versus advanced tco mode. 0 = the pch is in the compatible tco mode. 1 = the pch is in the advanced tco mode. 0 crc error (crce) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set if a received message contai ned a crc error. when this bit is set, the derr bit of the host status register will also be set. this bit will be set by the controller if a software abort occurs in th e middle of the crc portion of the cycle or an abort happens after the pch has received the final data bit transmitted by an external slave.
datasheet 753 smbus controller registers (d31:f3) 18.2.12 aux_ctlauxiliary cont rol register (smbusd31:f3) register offset: smb_base + 0dh attribute: r/w default value: 00h size: 8 bits lockable: no power well: resume 18.2.13 smlink_pin_ctlsmlink pin control register (smbusd31:f3) register offset: smb_base + 0eh attribute: r/w, ro default value: see below size: 8 bits note: this register is in the resume well and is reset by rsmrst#. this register is only applicable in the tco compatible mode. bit description 7:2 reserved 1 enable 32-byte buffer (e32b) ? r/w. 0 = disable. 1 = enable. when set, the host block data register is a pointer into a 32-byte buffer, as opposed to a single re gister. this enables the block commands to transfer or receive up to 32-bytes before the pch generates an interrupt. 0 automatically append crc (aac) ? r/w. 0 = the pch will not automatically append the crc. 1 = the pch will automatically append the cr c. this bit must no t be changed during smbus transactions or undetermined behavior will result. it should be programmed only once during the li fetime of the function. bit description 7:3 reserved 2 smlink_clk_ctl ? r/w. 0 = the pch will drive the smlink0 pin low, independent of what the other smlink logic would otherwise indicate for the smlink0 pin. 1 = the smlink0 pin is not overdriven low. the other smlink logic controls the state of the pin. (default) 1 smlink1_cur_sts ? ro. this read-only bit has a de fault value that is dependent on an external signal level. th is pin returns the value on th e smlink1 pin. this allows software to read the cu rrent state of the pin. 0 = low 1 = high 0 smlink0_cur_sts ? ro. this read-only bit has a de fault value that is dependent on an external signal level. th is pin returns the value on th e smlink0 pin. this allows software to read the cu rrent state of the pin. 0 = low 1 = high
smbus controller registers (d31:f3) 754 datasheet 18.2.14 smbus_pin_ctlsmbus pin control register (smbusd31:f3) register offset: smb_base + 0fh attribute: r/w, ro default value: see below size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 18.2.15 slv_stsslave status register (smbusd31:f3) register offset: smb_base + 10h attribute: r/wc default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. all bits in this register are implemented in the 64 khz clock domain. therefore, software must poll this register until a write takes effect before assuming that a write has completed internally. bit description 7:3 reserved 2 smbclk_ctl ? r/w. 1 = the smbclk pin is not overdriven low. the other smbus logic controls the state of the pin. 0 = the pch drives the smbclk pin low, independent of what the other smb logic would otherwise indicate for the smbclk pin. (default) 1 smbdata_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smbdata pin. this allows software to read the cu rrent state of the pin. 0 = low 1 = high 0 smbclk_cur_sts ? ro. this read-only bit has a de fault value that is dependent on an external signal level. th is pin returns the value on th e smbclk pin. this allows software to read the cu rrent state of the pin. 0 = low 1 = high bit description 7:1 reserved 0 host_notify_sts ? r/wc. the pch sets this bit to a 1 when it has completely received a successful host notify command on the smbus pins. software reads this bit to determine that the source of the interr upt or smi# was the reception of the host notify command. software clears this bi t after reading any information needed from the notify address and data regi sters by writing a 1 to this bit. note that the pch will allow the notify address and data registers to be over-written once this bit has been cleared. when this bit is 1, the pch will nack the first byte (host address) of any new ?host notify? commands on the smbus pins. writing a 0 to this bit has no effect.
datasheet 755 smbus controller registers (d31:f3) 18.2.16 slv_cmdslave comman d register (smbusd31:f3) register offset: smb_base + 11h attribute: r/w default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 18.2.17 notify_daddrnotify device address register (smbusd31:f3) register offset: smb_base + 14h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. bit description 7:2 reserved 2 smbalert_dis ? r/w. 0 = allows the generation of the interrupt or smi#. 1 = software sets this bit to block the generation of the interrupt or smi# due to the smbalert# source. this bit is logically inverted and anded with the smbalert_sts bit (offset smb_base + 00 h, bit 5). the resulting signal is distributed to the smi# and/or interrupt generation logic. this bit does not effect the wake logic. 1 host_notify_wken ? r/w. software sets this bit to 1 to enable the reception of a host notify command as a wake event. when enabled this event is ?or?d" in with the other smbus wake events an d is reflected in the smb_ wak_sts bit of the general purpose event 0 status register. 0 = disable 1 = enable 0 host_notify_intren ? r/w. software sets this bit to 1 to enable the generation of interrupt or smi# when host_notify_st s (offset smb_base + 10h, bit 0) is 1. this enable does not affect the setting of the host_notify_sts bit. when the interrupt is generated, either pirqb# or smi# is generated, depending on the value of the smb_smi_en bit (d31:f3:40h, bit 1). if the host_notify_sts bit is set when this bit is written to a 1, then the interrupt (o r smi#) will be generated. the interrupt (or smi#) is logically generated by and?ing the sts and intren bits. 0 = disable 1 = enable bit description 7:1 device_address ? ro. this field contains the 7-bi t device address received during the host notify protocol of the smbus 2.0 sp ecification. software should only consider this field valid when the host_notify_sts bit (d31:f3:smb_base +10, bit 0) is set to 1. 0 reserved
smbus controller registers (d31:f3) 756 datasheet 18.2.18 notify_dlownotify data low byte register (smbusd31:f3) register offset: smb_base + 16h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 18.2.19 notify_dhighnotify data high byte register (smbusd31:f3) register offset: smb_base + 17h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. bit description 7:0 data_low_byte ? ro. this field contains the firs t (low) byte of data received during the host notify protocol of the smbu s 2.0 specification. so ftware should only consider this field valid when the host_n otify_sts bit (d31:f3:smb_base +10, bit 0) is set to 1. bit description 7:0 data_high_byte ? ro. this field contains the second (high) byte of data received during the host notify protocol of the smbu s 2.0 specification. software should only consider this field valid when the host_n otify_sts bit (d31:f3:smb_base +10, bit 0) is set to 1.
datasheet 757 pci express* configuration registers 19 pci express* configuration registers 19.1 pci express* configuration registers (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) note: this section assumes the default pci express function number-to-root port mapping is used. function numbers for a given root po rt are assignable through the root port function number and hide for pci expr ess root ports register (rcba+0404h). note: register address locations that are not shown in table 19-1 , should be treated as reserved. table 19-1. pci express* configuration registers address map (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) (sheet 1 of 3) offset mnemonic register name function 0C7 default attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 04h ro 0bh bcc base class code 06h ro 0ch cls cache line size 00h r/w 0dh plt primary latency timer 00h ro 0eh headtyp header type 81h ro 18h?1ah bnum bus number 000000h r/w 1bh slt secondary latency timer 00h ro 1ch?1dh iobl i/o base and limit 0000h r/w, ro 1eh?1fh ssts secondary status register 0000h r/wc 20h?23h mbl memory base and limit 00000000h r/w 24h?27h pmbl prefetchable memory base and limit 00010001h r/w, ro 28h?2bh pmbu32 prefetchable memory base upper 32 bits 00000000h r/w 2ch?2fh pmlu32 prefetchable memory limit upper 32 bits 00000000h r/w 34h capp capabilities list pointer 40h ro 3ch?3dh intr interrupt information see bit description r/w, ro
pci express* configuration registers 758 datasheet 3eh?3fh bctrl bridge control register 0000h r/w 40h?41h clist capabilities list 8010h ro 42h?43h xcap pci express* capabilities 0041h r/wo, ro 44h?47h dcap device capabilities 00000fe0h ro 48h?49h dctl device control 0000h r/w, ro 4ah?4bh dsts device status 0010h r/wc, ro 4ch?4fh lcap link capabilities see bit description ro, r/wo 50h?51h lctl link control 0000h r/w, ro 52h?53h lsts link status see bit description ro 54h?57h slcap slot capabilities register 00000060h r/wo, ro 58h?59h slctl slot control 0000h r/w, ro 5ah?5bh slsts slot status 0000h r/wc, ro 5ch?5dh rctl root control 0000h r/w 60h?63h rsts root status 00000000h r/wc, ro 64h?67h dcap2 device capabilities 2 register 00000016h ro 68h?69h dctl2 device control 2 register 0000h r/w, ro 70h?71h lctl2 link control 2 register 0001h r/w 72h?73h lsts2 link status 2 register 0000h r/w 80h?81h mid message signaled interrupt identifiers 9005h ro 82h?83h mc message signaled interrupt message control 0000h r/w, ro 84h?87h ma message signaled interrupt message address 00000000h r/w 88h?89h md message signaled interrupt message data 0000h r/w 90h?91h svcap subsystem vendor capability a00dh ro 94h?97h svid subsystem vendor identification 00000000h r/wo a0h?a1h pmcap power management capability 0001h ro a2h?a3h pmc pci power management capability c802h ro a4h?a7h pmcs pci power management control and status 00000000h r/w, ro d4h?d7h mpc2 miscellaneous port configuration 2 00000000h r/w, ro d8h?dbh mpc miscellaneous port configuration 08110000h r/w dch?dfh smscs smi/sci status 00000000h r/wc e1h rpdcgen rort port dynamic clock gating enable 00h r/w table 19-1. pci express* config uration registers address map (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) (sheet 2 of 3) offset mnemonic register name function 0C7 default attribute
datasheet 759 pci express* configuration registers 19.1.1 vidvendor identi fication register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 19.1.2 diddevice identification register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 02h?03h attribute: ro default value: port 1= bit description size: 16 bits port 2= bit description port 3= bit description port 4= bit description port 5= bit description port 6= bit description port 7= bit description port 8= bit description e8h?ebh pecr1 pci express configuration register 1 00000020h r/w ech?efh pecr3 pci express configuration register 3 00000000h r/w 104h?107h ues uncorrectable error status see bit description r/wc, ro 108h?10bh uem uncorrectable error mask 00000000h r/wo, ro 10ch?10fh uev uncorrectable error severity 00060011h ro 110h?113h ces correctable error status 00000000h r/wc 114h?117h cem correctable error mask 00000000h r/wo 118h?11bh aecc advanced error capabilities and control 00000000h ro 130h?133h res root error status 00000000h r/wc, ro 300h?303h pecr2 pci express configuration register 2 60005007h r/w 324h?327h peetm pci express extended test mode register see bit description ro 330h?333h pec1 pci express configuration register 1 00000000h ro, r/w table 19-1. pci express* configuration registers address map (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) (sheet 3 of 3) offset mnemonic register name function 0C7 default attribute bit description 15:0 vendor id ? ro. this is a 16-bit value assi gned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the pch?s pci express controller. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the did register.
pci express* configuration registers 760 datasheet 19.1.3 pcicmdpci command register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 04h?05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. this disables pin-base d intx# interrupts on enabled hot- plug and power management events. this bit has no effect on msi operation. 0 = internal intx# messages are generated if there is an interrupt for hot-plug or power management and msi is not enabled. 1 = internal intx# messages will not be generated. this bit does not affect interrupt forwardi ng from devices connected to the root port. assert_intx and deasse rt_intx messages will still be forwarded to the internal interrupt controllers if this bit is set. 9 fast back to back enable (fbe) ? reserved per the pci express* base specification . 8 serr# enable (see) ? r/w. 0 = disable. 1 = enables the root port to generate an serr# message when psts.sse is set. 7 wait cycle control (wcc) ? reserved per the pci express base specification . 6 parity error response (per) ? r/w. 0 = disable. 1 = indicates that the device is capable of reporting parity errors as a master on the backbone. 5 vga palette snoop (vps ) ? reserved per the pci express* base specification . 4 postable memory write enable (pmwe) ? reserved per the pci express* base specification . 3 special cycle en able (sce) ? reserved per the pci express* base specification . 2 bus master enable (bme) ? r/w. 0 = disable. memory and i/o requests received at a root port must be handled as unsupported requests. 1 = enable. allows the root port to forward memory and i/o read/write cycles onto the backbone from a pci express* device. note: this bit does not affect forwarding of completions in either upstream or downstream direction nor controls forwardi ng of requests othe r than memory or i/o 1 memory space enable (mse) ? r/w. 0 = disable. memory cycles within the rang e specified by the memory base and limit registers are master aborted on the backbone. 1 = enable. allows memory cycles within th e range specified by the memory base and limit registers can be forwarde d to the pci express device. 0 i/o space enable (iose) ? r/w. this bit controls acce ss to the i/o space registers. 0 = disable. i/o cycles within the range specif ied by the i/o base an d limit regi sters are master aborted on the backbone. 1 = enable. allows i/o cycles within the range specified by the i/o base and limit registers can be forwarded to the pci express device.
datasheet 761 pci express* configuration registers 19.1.4 pcistspci status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 06h ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = set when the root port receives a command or data from the backbone with a parity error. this is set even if pcimd. per (d28:f0/f1/f2/f3:04, bit 6) is not set. 14 signaled system error (sse) ? r/wc. 0 = no system error signaled. 1 = set when the root port signals a system error to the internal serr# logic. 13 received master abort (rma) ? r/wc. 0 = root port has not received a completion with unsupported re quest status from the backbone. 1 = set when the root port receives a comp letion with unsupported request status from the backbone. 12 received target abort (rta) ? r/wc. 0 = root port has not received a completion with completer abort from the backbone. 1 = set when the root port receives a completion with completer abort from the backbone. 11 signaled target abort (sta) ? r/wc. 0 = no target abort received. 1 = set whenever the root port forwards a target abort received from the downstream device onto the backbone. 10:9 devsel# timing status (dev_sts) ? reserved per the pci express* base specification . 8 master data parity error detected (dped) ? r/wc. 0 = no data parity error received. 1 = set when the root port receives a completion with a data parity error on the backbone and pcimd.per (d28:f0/f1/f2/f3:04, bit 6) is set. 7 fast back to back capable (fb2bc) ? reserved per the pci express* base specification . 6 reserved 5 66 mhz capable ? reserved per the pci express* base specification . 4 capabilities list ? ro. hardwired to 1. indicates th e presence of a ca pabilities list. 3 interrupt status ? ro. indicates status of ho t-plug and power management interrupts on the root port that re sult in intx# message generation. 0 = interrupt is deasserted. 1 = interrupt is asserted. this bit is not set if msi is enabled. if msi is not enabled, this bit is set regardless of the state of pcicmd.interrupt disable bit (d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7:04h:bit 10). 2:0 reserved
pci express* configuration registers 762 datasheet 19.1.5 ridrevision iden tification register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) offset address: 08h attribute: ro default value: see bit description size: 8 bits 19.1.6 piprogramming interface register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 09h attribute: ro default value: 00h size: 8 bits 19.1.7 sccsub class code register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 0ah attribute: ro default value: 04h size: 8 bits 19.1.8 bccbase class code register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 0bh attribute: ro default value: 06h size: 8 bits bit description 7:0 revision id ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit description 7:0 programming interface ? ro. 00h = no specific register level programming interface defined. bit description 7:0 sub class code (scc) ? ro. this field is determined by bit 2 of the mpc register (d28:f0-5:offset d8h, bit 2). 04h = pci-to-pci bridge. 00h = host bridge. bit description 7:0 base class code (bcc) ? ro. 06h = indicates the device is a bridge device.
datasheet 763 pci express* configuration registers 19.1.9 clscache line size register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 0ch attribute: r/w default value: 00h size: 8 bits 19.1.10 pltprimary late ncy timer register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 0dh attribute: ro default value: 00h size: 8 bits 19.1.11 headtypheader type register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 0eh attribute: ro default value: 81h size: 8 bits bit description 7:0 cache line size (cls) ? r/w. this is read/write but contains no functionality, per the pci express* base specification . bit description 7:3 latency count. reserved per the pci express* base specification. 2:0 reserved bit description 7 multi-function device ? ro. 0 = single-func tion device. 1 = multi-function device. 6:0 configuration layout ? ro. this field is determined by bit 2 of the mpc register (d28:f0-5:offset d8h, bit 2). 00h = indicates a host bridge. 01h = indicates a pci-to-pci bridge.
pci express* configuration registers 764 datasheet 19.1.12 bnumbus nu mber register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 18?1ah attribute: r/w default value: 000000h size: 24 bits 19.1.13 sltsecondary la tency timer register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 1bh attribute: ro default value: 00h size: 8 bits 19.1.14 iobli/o base and limit register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 1ch?1dh attribute: r/w, ro default value: 0000h size: 16 bits bit description 23:16 subordinate bus number (sbbn) ? r/w. indicates the highest pci bus number below the bridge. 15:8 secondary bus number (scbn) ? r/w. indicates the bus number the port. 7:0 primary bus number (pbn) ? r/w. indicates the bus number of the backbone. bit description 7:0 secondary latency timer ? reserved for a root port per the pci express* base specification. bit description 15:12 i/o limit address (iola) ? r/w. i/o base bits corresponding to address lines 15:12 for 4-kb alignment. bits 11:0 are assumed to be padded to fffh. 11:8 i/o limit address capability (iolc) ? ro. indicates that the bridge does not support 32-bit i/o addressing. 7:4 i/o base address (ioba) ? r/w. i/o base bits corresponding to address lines 15:12 for 4-kb alignment. bits 11:0 are assumed to be padded to 000h. 3:0 i/o base address capability (iobc) ? ro. indicates that the bridge does not support 32-bit i/o addressing.
datasheet 765 pci express* configuration registers 19.1.15 sstssecondary status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 1eh?1fh attribute: r/wc default value: 0000h size: 16 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no error. 1 = the port received a poisoned tlp. 14 received system error (rse) ? r/wc. 0 = no error. 1 = the port received an err_fatal or err_nonfatal message from the device. 13 received master abort (rma) ? r/wc. 0 = unsupported request not received. 1 = the port received a completion with ?unsupported request? status from the device. 12 received target abort (rta) ? r/wc. 0 = completion abort not received. 1 = the port received a completion with ?completion abort? st atus from the device. 11 signaled target abort (sta) ? r/wc. 0 = completion abort not sent. 1 = the port generated a completion with ?completion abort? status to the device. 10:9 secondary devsel# timing status (sdts): reserved per pci express* base specification . 8 data parity error detected (dpd) ? r/wc. 0 = conditions belo w did not occur. 1 = set when the bctrl.pere (d28:fo/f1/f2/f3/f4/f5:3e: bit 0) is set, and either of the following two conditions occurs: ?port receives completi on marked poisoned. ?port poisons a write request to the secondary side. 7 secondary fast back to back capable (sfbc): reserved per pci express* base specification . 6 reserved 5 secondary 66 mhz capable (sc66): reserved per pci express* base specification . 4:0 reserved
pci express* configuration registers 766 datasheet 19.1.16 mblmemory base and limit register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 20h?23h attribute: r/w default value: 00000000h size: 32 bits accesses that are within the rang es specified in this register will be sent to the attached device if cmd.mse (d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7:04:bit 1) is set. accesses from the attached device that are outside th e ranges specified will be forwarded to the backbone if cmd.bme (d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7:04:bit 2) is set. the comparison performed is mb ? ad[31:20] ? ml. 19.1.17 pmblprefetcha ble memory base an d limit register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 24h?27h attribute: r/w, ro default value: 00010001h size: 32 bits accesses that are within the ranges specified in this register will be sent to the device if cmd.mse (d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7;04, bit 1) is set. accesses from the device that are outside the ranges specif ied will be forwarded to the backbone if cmd.bme (d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7;04, bit 2) is set. the comparison performed is pmbu32:pmb ? ad[63:32]:ad[31:20] ? pmlu32:pml. bit description 31:20 memory limit (ml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the upper 1-mb aligned value of the range. 19:16 reserved 15:4 memory base (mb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lower 1-mb aligned value of the range. 3:0 reserved bit description 31:20 prefetchable memory limit (pml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine th e upper 1-mb aligned value of the range. 19:16 64-bit indicator (i64l) ? ro. indicates support for 64-bit addressing 15:4 prefetchable memory base (pmb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lower 1-mb aligned value of the range. 3:0 64-bit indicator (i64b) ? ro. indicates support for 64-bit addressing
datasheet 767 pci express* configuration registers 19.1.18 pmbu32prefetchable me mory base upper 32 bits register (pci express*d 28:f0/f1/f2/f3/f4/f5/f6/ f7/f6/f7) address offset: 28h?2bh attribute: r/w default value: 00000000h size: 32 bits 19.1.19 pmlu32prefetchable memory limit upper 32 bits register (pci express*d 28:f0/f1/f2/f3/f4/f5/f6/ f7/f6/f7) address offset: 2ch?2fh attribute: r/w default value: 00000000h size: 32 bits 19.1.20 cappcapabilities list pointer register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 34h attribute: ro default value: 40h size: 8 bits bit description 31:0 prefetchable memory base upper portion (pmbu) ? r/w. upper 32-bits of the prefetchable address base. bit description 31:0 prefetchable memory limit upper portion (pmlu) ? r/w. upper 32-bits of the prefetchable address limit. bit description 7:0 capabilities pointer (ptr) ? ro. indicates that the pointer for the first entry in the capabilities list is at 40h in configuration space.
pci express* configuration registers 768 datasheet 19.1.21 intrinterrupt information register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 3ch?3dh attribute: r/w, ro default value: see bit description size: 16 bits function level reset: no (bits 7:0 only) bit description 15:8 interrupt pin (ipin) ? ro. indicates the interrupt pin driven by the root port. at reset, this register takes on the following values that re flect the reset state of the d28ip register in chipset config space: note: the value that is programmed into d28ip is always reflected in this register. 7:0 interrupt line (iline) ? r/w. default = 00h. software written value to indicate which interrupt line (vector) the interrupt is connected to. no hardware action is taken on this register. these bi ts are not reset by flr. port reset value 1 d28ip.p1ip 2 d28ip.p2ip 3 d28ip.p3ip 4 d28ip.p4ip 5 d28ip.p5ip 6 d28ip.p6ip 7 d28ip.p7ip 8 d28ip.p8ip
datasheet 769 pci express* configuration registers 19.1.22 bctrlbridge control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7/f6/f7) address offset: 3eh?3fh attribute: r/w default value: 0000h size: 16 bits bit description 15:12 reserved 11 discard timer serr# enable (dtse): reserved per pci express* base specification, revision 1.0a 10 discard timer status (dts): reserved per pci express* base specification, revision 1.0a. 9 secondary discard timer (sdt): reserved per pci express* base specification, revision 1.0a. 8 primary discard timer (pdt): reserved per pci express* base specification, revision 1.0a. 7 fast back to back enable (fbe): reserved per pci express* base specification, revision 1.0a. 6 secondary bus reset (sbr) ? r/w. triggers a hot rese t on the pci express* port. 5 master abort mode (mam): reserved per express specification. 4 vga 16-bit decode (v16) ? r/w. 0 = vga range is enabled. 1 = the i/o aliases of the vga range (see bc trl:ve definition belo w), are not enabled, and only the base i/o ranges can be decoded. 3 vga enable (ve) ? r/w. 0 = the ranges below will not be claimed off the backbone by the root port. 1 = the following ranges will be claime d off the backbone by the root port: ? memory ranges a0000h-bffffh ? i/o ranges 3b0h ? 3bbh and 3c0h ? 3dfh, and a ll aliases of bits 15:10 in any combination of 1s 2 isa enable (ie) ? r/w. this bit only applies to i/ o addresses that are enabled by the i/o base and i/o limit registers and are in the first 64 kb of pci i/o space. 0 = the root port will not block any forwar ding from the backbone as described below. 1 = the root port will block any forwarding from the backbone to the device of i/o transactions addressing the last 768 by tes in each 1-kb block (offsets 100h to 3ffh). 1 serr# enable (se) ? r/w. 0 = the messages descri bed below are not forwarded to the backbone. 1 = err_cor, err_nonfatal, and err_fatal messages received are forwarded to the backbone. 0 parity error respon se enable (pere) ? r/w. when set, 0 = poisoned write tlps and completions indicating poisoned tlps will not set the ssts.dpd (d28:f0/f1/f2/f3/f4/f5/f6/f7:1e, bit 8). 1 = poisoned write tlps and completions indicating poisoned tlps will set the ssts.dpd (d28:f0/f1/f2/f3/f4/f5/f6/f7:1e, bit 8).
pci express* configuration registers 770 datasheet 19.1.23 clistcapabilities list register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 40?41h attribute: ro default value: 8010h size: 16 bits 19.1.24 xcappci express* capabilities register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 42h?43h attribute: r/wo, ro default value: 0042h size: 16 bits bit description 15:8 next capability (next) ? ro. value of 80h indicates the location of the next pointer. 7:0 capability id (cid) ? ro. indicates this is a pci express* capability. bit description 15:14 reserved 13:9 interrupt message number (imn) ? ro. the pch does not have multiple msi interrupt numbers. 8 slot implemented (si) ? r/wo. indicates whether the ro ot port is connected to a slot. slot support is platform specific. bios programs this field, and it is maintained until a platform reset. 7:4 device / port type (dt) ? ro. indicates this is a pci express* root port. 3:0 capability version (cv) ? ro. indicates pci express 2.0.
datasheet 771 pci express* configuration registers 19.1.25 dcapdevice capa bilities register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 44h?47h attribute: ro default value: 00008000h size: 32 bits bit description 31:28 reserved 27:26 captured slot power limit sc ale (csps) ? ro. not supported. 25:18 captured slot power limit va lue (cspv) ? ro. not supported. 17:16 reserved 15 role based error reporting (rber) ? ro. indicates that this device implements the functionality defined in th e error reporting ecn as required by the pci express 2.0 specification. 14:12 reserved 11:9 endpoint l1 acceptable latency (e1al) ? ro. this field is reserved with a setting of 000b for devices other than endpoin ts, per the pci express 2.0 spec. 8:6 endpoint l0s acceptable latency (e0al) ? ro. this field is reserved with a setting of 000b for devices other than endpoin ts, per the pci express 2.0 spec. 5 extended tag field supported (etfs) ? ro. indicates that 8-bit tag fields are supported. 4:3 phantom functions supported (pfs) ? ro. no phantom functions supported. 2:0 max payload size supported (mps) ? ro. indicates the maximum payload size supported is 128b.
pci express* configuration registers 772 datasheet 19.1.26 dctldevice control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 48h?49h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15 reserved 14:12 max read request size (mrrs) ? ro. hardwired to 0. 11 enable no snoop (ens) ? ro. not supported. the root port will never issue non-snoop requests. 10 aux power pm enable (apme) ? r/w. the os will set th is bit to 1 if the device connected has detected aux power. it has no effect on the root port otherwise. 9 phantom functions enable (pfe) ? ro. not supported. 8 extended tag field enable (etfe) ? ro. not supported. 7:5 max payload size (mps) ? r/w. the root port only supports 128-b payloads, regardless of the programming of this field. 4 enable relaxed ordering (ero) ? ro. not supported. 3 unsupported request reporting enable (ure) ? r/w. 0 = the root port will ignore unsupported request errors. 1 = allows signaling err_nonfatal, err_fa tal, or err_cor to the root control register when detecting an unmasked un supported request (ur). an err_cor is signaled when a unmasked advisory non- fatal ur is received. an err_fatal, err_or nonfatal, is sent to the root control register when an uncorrectable non- advisory ur is received wi th the severity set by the uncorrectable error severity register. 2 fatal error reporting enable (fee) ? r/w. 0 = the root port will ignore fatal errors. 1 = enables signaling of err_fatal to the root control register due to internally detected errors or error mess ages received across the li nk. other bits also control the full scope of related error reporting. 1 non-fatal error reporting enable (nfe) ? r/w. 0 = the root port will ignore non-fatal errors. 1 = enables signaling of err_nonfatal to th e root control register due to internally detected errors or error mess ages received across the li nk. other bits also control the full scope of related error reporting. 0 correctable error reporting enable (cee) ? r/w. 0 = the root port will ignore correctable errors. 1 = enables signaling of err_corr to the root control register due to internally detected errors or error mess ages received across the li nk. other bits also control the full scope of related error reporting.
datasheet 773 pci express* configuration registers 19.1.27 dstsdevice status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 4ah?4bh attribute: r/wc, ro default value: 0010h size: 16 bits bit description 15:6 reserved 5 transactions pending (tdp) ? ro. this bit has no mean ing for the root port since only one transaction may be pending to the pch, so a read of this bit cannot occur until it has already returned to 0. 4 aux power detected (apd) ? ro. the root port contains aux power for wakeup. 3 unsupported request detected (urd) ? r/wc. indicates an unsupported request was detected. 2 fatal error detected (fed) ? r/wc. indicates a fatal error was detected. 0 = fatal has not occurred. 1 = a fatal error occurred from a data link prot ocol error, link training error, buffer overflow, or malformed tlp. 1 non-fatal error detected (nfed) ? r/wc. indicates a non- fatal error was detected. 0 = non-fatal has not occurred. 1 = a non-fatal error occurred from a po isoned tlp, unexpected completions, unsupported requ ests, completer abort, or completer timeout. 0 correctable error detected (ced) ? r/wc. indicates a correctable error was detected. 0 = correctable has not occurred. 1 = the port received an internal correct able error from receiver errors / framing errors, tlp crc error, dllp crc error, replay num rollover, replay timeout.
pci express* configuration registers 774 datasheet 19.1.28 lcaplink capa bilities register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 4ch ? 4fh attribute: r/wo, ro default value: see bit description size: 32 bits bit description 31:24 port number (pn) ? ro. indicates the port number fo r the root port. this value is different for each implemented port: 23:21 reserved 20 link active reporting capable (larc) ? ro. hardwired to 1 to indicate that this port supports the optional capability of repo rting the dl_active state of the data link control and management state machine. 19:18 reserved 17:15 l1 exit latency (el1) ? r/wo. 000b = less than 1us 001b = 1 us to less than 2 us 010b = 2 us to less than 4 us 011b = 4 us to less than 8 us 100b = 8 us to less than 16 us 101b = 16 us to less than 32 us 110b = 32 us to 64 us 111b = more than 64 us 14:12 l0s exit latency (el0) ? ro. indicates as exit latency based upon common-clock configuration. note: lclt.ccc is at d28:f0/f1/f2 /f3/f4/f5/f6/f 7:50h:bit 6 function port # value of pn field d28:f0 1 01h d28:f1 2 02h d28:f2 3 03h d28:f3 4 04h d28:f4 5 05h d28:f5 6 06h d28:f6 7 07h d28:f7 8 08h lclt.ccc value of el0 (these bits) 0 mpc.ucel (d28:f0/f1/f2/f3:d8h:bits20:18) 1 mpc.ccel (d28:f0/f1/f2/f3:d8h:bits17:15)
datasheet 775 pci express* configuration registers 11:10 active state link pm support (apms) ? r/wo. indicates what level of active state link power management is su pported on the root port. 9:4 maximum link width (mlw) ? ro. for the root ports, several values can be taken, based upon the value of the chipset config register field rpc.pc1 (chipset config registers:offset 0224h:bit s1:0) for ports 1-4 and rpc.pc2 (chipset config registers:offset 0224h:bit s1:0) for ports 5 and 6 3:0 maximum link speed (mls) ? ro. 0001b = indicates the link speed is 2.5 gb/s 0010b = 5.0 gb/s and 2.5gb/s link speeds supported these bits report a value of 0001b if gen2 disable bit 14 is set in the mpc register, else the value reported is 0010b bit description bits definition 00b neither l0s nor l1 are supported 01b l0s entry supported 10b l1 entry supported 11b both l0s and l1 entry supported value of mlw field port # rpc.pc1=00b rpc.pc1=11b 1 01h 04h 2 01h 01h 3 01h 01h 4 01h 01h port # rpc.pc2=00b rpc.pc2=11b 5 01h 04h 6 01h 01h 7 01h 01h 8 01h 01h
pci express* configuration registers 776 datasheet 19.1.29 lctllink co ntrol register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 50h?51h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:10 reserved 9 hardware autonomous width disable ? ro. hardware never attempts to change the link width except when attempting to correct unreliable link operation. 8reserved 7 extended synch (es) ? r/w. 0 = extended sy nch disabled. 1 = forces extended transmission of fts ordered sets in fts and extra ts2 at exit from l1 prior to entering l0. 6 common clock conf iguration (ccc) ? r/w. 0 = the pch and device are not using a common reference clock. 1 = the pch and device are operating with a distributed common reference clock. 5 retrain link (rl) ? r/w. 0 = this bit always returns 0 when read. 1 = the root port will tr ain its downstream link. note: software uses lsts.lt (d28:f0/f1/f2/f3/f4/f5/f6/f7:52, bit 11) to check the status of training. note: it is permitted to write 1b to this bi t while simultaneously writing modified values to other fields in this register. if the ltssm is not already in recovery or configuration, the resulting link training must use the modified values. if the ltssm is already in recovery or configuration, the modified values are not required to affect the link traini ng that is already in progress. 4 link disable (ld) ? r/w. 0 = link enabled. 1 = the root port will disable the link. 3 read completion bo undary control (rcbc) ? ro. indicates the read completion boundary is 64 bytes. 2reserved 1:0 active state link pm control (apmc) ? r/w. indicates whether the root port should enter l0s or l1 or both. 00 = disabled 01 = l0s entry enabled 10 = l1 entry enabled 11 = l0s and l1 entry enabled
datasheet 777 pci express* configuration registers 19.1.30 lstslink status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 52h?53h attribute: ro default value: see bit description size: 16 bits bit description 15:14 reserved 13 data link layer active (dlla) ? ro. default value is 0b. 0 = data link control and management state machine is not in the dl_active state 1 = data link control and management st ate machine is in the dl_active state 12 slot clock configuration (scc) ? ro. set to 1b to indicate that the pch uses the same reference clock as on the platform and does no t generate its own clock. 11 link training (lt) ? ro. default value is 0b. 0 = link training completed. 1 = link training is occurring. 10 link training error (lte ) ? ro. not supported. set value is 0b. 9:4 negotiated link width (nlw) ? ro. this field indicates the negotiated width of the given pci express* link. the contents of this nlw field is undefined if the link has not successfully trained. note: 000001b = x1 link width, 000010b =x2 linkwidth, 000100b = x4 linkwidth 3:0 link speed (ls) ? ro. this field indica tes the negotiated link speed of the given pci express* link. 0001b = link is 2.5 gb/s 0010b = link is 5.0 gb/s port # possible values 1 000001b, 000010b, 000100b 2 000001b 3 000001b, 000010b 4 000001b 5 000001b, 000010b, 000100b 6 000001b 7 000001b, 000010b 8 000001b
pci express* configuration registers 778 datasheet 19.1.31 slcapslot capa bilities register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 54h ? 57h attribute: r/wo, ro default value: 00040060h size: 32 bits bit description 31:19 physical slot number (psn) ? r/wo. this is a value that is unique to the slot number. bios sets this field and it remains set until a platform reset. 18:17 reserved 16:15 slot power limit scale (sls) ? r/wo. specifies the scale used for the slot power limit value. bios sets this field and it remains set unti l a platform reset. 14:7 slot power limit value (slv) ? r/wo. specifies the upper limit (in conjunction with sls value), on the upper limi t on power supplied by the sl ot. the two values together indicate the amount of power in watts allowed for the slot. bios sets this field and it remains set until a platform reset. 6 hot plug capable (hpc) ? r/wo. 1b = indicates that ho t-plug is supported. 5 hot plug surprise (hps) ? r/wo. 1b = indicates the device may be removed from the slot without prior notification. 4 power indicator present (pip) ? ro. 0b = indicates that a power indicato r led is not present for this slot. 3 attention indicator present (aip) ? ro. 0b = indicates that an attention indicator led is not present for this slot. 2 mrl sensor present (msp) ? ro. 0b = indicates that an mrl sensor is not present. 1 power controller present (pcp) ? ro. 0b = indicates that a po wer controller is not im plemented for this slot. 0 attention button present (abp) ? ro. 0b = indicates that an attention butt on is not implemen ted for this slot.
datasheet 779 pci express* configuration registers 19.1.32 slctlslot control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 58h ? 59h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:13 reserved 12 link active changed enable (lace) ? r/w. when set, this field enables generation of a hot plug interrupt when the data link layer link active field (d28:f0/f1/f2/f3/f4/ f5/f6/f7:52h:bit 13) is changed. 11 reserved 10 power controller control (pcc) ? ro.this bit has no me aning for module based hot-plug. 9:6 reserved 5 hot plug interrupt enable (hpe) ? r/w. 0 = hot plug interrupts based on hot-plug events is disabled. 1 = enables generation of a hot-plug interrupt on enabled hot-plug events. 4 reserved 3 presence detect changed enable (pde) ? r/w. 0 = hot plug interrupts base d on presence de tect logic changes is disabled. 1 = enables the generation of a hot-plug interrupt or wake message when the presence detect logic changes state. 2:0 reserved
pci express* configuration registers 780 datasheet 19.1.33 slstsslot status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 5ah ? 5bh attribute: r/wc, ro default value: 0000h size: 16 bits bit description 15:9 reserved 8 link active state changed (lasc) ? r/wc. 1 = this bit is set when the value reported in data link layer link active field of the link status register (d28:f0/f1/f2/f3/f4/f5/f6/f7:52h:bit 13) is changed. in response to a data link layer state change d event, software mu st read data link layer link active field of the link status re gister to determine if the link is active before initiating configuration cy cles to the hot plugged device. 7reserved 6 presence detect state (pds) ? ro. if xcap.si (d28:f0/f1/f2/f3/f4/f5/f6/ f7:42h:bit 8) is set (indicating that this root port spawns a slot), then this bit: 0 = indicates the slot is empty. 1 = indicates the slot has a device connected. otherwise, if xcap.si is cleared, this bit is always set (1). 5 mrl sensor state (ms) ? reserved as the mrl sensor is not implemented. 4 reserved 3 presence detect changed (pdc) ? r/wc. 0 = no change in the pds bit. 1 = the pds bit changed states. 2 mrl sensor changed (msc) ? reserved as the mrl sensor is not implemented. 1 power fault detected (pfd) ? reserved as a power cont roller is not implemented. 0reserved
datasheet 781 pci express* configuration registers 19.1.34 rctlroot control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 5ch ? 5dh attribute: r/w default value: 0000h size: 16 bits 19.1.35 rstsroot status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 60h ? 63h attribute: r/wc, ro default value: 00000000h size: 32 bits bit description 15:4 reserved 3 pme interrupt enable (pie) ? r/w. 0 = interrupt generation disabled. 1 = interrupt generation enabled when pc ists.inerrupt status (d28:f0/f1/f2/f3/f4/ f5/f6/f7:60h, bit 16) is in a set state (either due to a 0 to 1 transition, or due to this bit being set with rsts.is already set). 2 system error on fatal error enable (sfe) ? r/w. 0 = an serr# will not be generated. 1 = an serr# will be generated, assuming cmd.see (d28:f0/f1/f2/f3/f4/f5/f6/ f7:04, bit 8) is set, if a fatal error is reported by any of the devices in the hierarchy of this root port, including fa tal errors in this root port. 1 system error on non-fatal error enable (sne) ? r/w. 0 = an serr# will not be generated. 1 = an serr# will be generated, assuming cmd.see (d28:f0/f1/f2/f3/f4/f5/f6/ f7:04, bit 8) is set, if a non-fatal error is reported by any of the devices in the hierarchy of this root port, including non-fatal errors in this root port. 0 system error on correctable error enable (sce) ? r/w. 0 = an serr# will not be generated. 1 = an serr# will be generated, assuming cmd.see (d28:f0/f1/f2/f3/f4/f5/f6/ f7:04, bit 8) if a correctable error is repo rted by any of the devices in the hierarchy of this root port, including correct able errors in this root port. bit description 31:18 reserved 17 pme pending (pp) ? ro. 0 = when the original pme is cleared by softwa re, it will be set again, the requestor id will be updated, and th is bit will be cleared. 1 = indicates another pme is pendin g when the pme status bit is set. 16 pme status (ps) ? r/wc. 0 = pme was not asserted. 1 = indicates that pme was asserted by the requestor id in rid. subsequent pmes are kept pending until th is bit is cleared. 15:0 pme requestor id (rid) ? ro. indicates the pci requ estor id of the last pme requestor. valid only when ps is set.
pci express* configuration registers 782 datasheet 19.1.36 dcap2device ca pabilities 2 register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 64h ? 67h attribute: ro default value: 00000016h size: 32 bits 19.1.37 dctl2device control 2 register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 68h ? 69h attribute: ro, r/w default value: 0000h size: 16 bits bit description 31:5 reserved 4 completion timeout disa ble supported (ctds) ? ro. a value of 1b indicates support for the comple tion timeout disable mechanism. 3:0 completion timeout ranges supported (ctrs) C ro. this field indicates device support for the optional completion ti meout programmability mechanism. this mechanism allows system software to modify the completion timeout value. this field is hardwired to support 10 ms to 250 ms and 250 ms to 4 s. bit description 15:5 reserved 4 completion timeout disable (ctd) ? r/w. when set to 1b, this bit disables the completion timeout mechanism. if there are outstanding requests when the bit is cleared, it is permitted but not required for hardware to apply the comple tion timeout mechanism to the outstanding requests. if this is done, it is permitted to base the start ti me for each request on either the time this bit was cleared or the time each request was issued. 3:0 completion timeout value (ctv) ? r/w. this field allows system software to modify the completion timeout value. 0000b = default range: 40?50 ms (specification range 50 us to 50 ms) 0101b = 40?50 ms (specification range is 16 ms to 55 ms) 0110b = 160?170 ms (specification range is 65 ms to 210 ms) 1001b = 400?500 ms (specification range is 260 ms to 900 ms) 1010b = 1.6?1.7 s (specification range is 1 s to 3.5 s) all other values are reserved. note: software is permitted to ch ange the value in this field at any time. for requests already pending when the completion ti meout value is changed, hardware is permitted to use either the new or the old value for the outstanding requests, and is permitted to base th e start time for each requ est either on when this value was changed or on when each request w as issued.
datasheet 783 pci express* configuration registers 19.1.38 lctl2link control 2 register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 70h ? 71h attribute: r/w default value: 0001h size: 16 bits bit description 15:13 reserved 12 compliance de-emphasis (cd) r/w. this bit sets the de-emphasis level in polling.compliance state if the entry occurre d due to the enter comp liance bit being 1b. encodings: 0 = 6 db 1 = 3.5 db when the link is operating at 2.5 gt/s, the setting of this bit has no effect. the default value of this bit is 0b. this bit is intended for de bug, compliance te sting purposes. syst em firmware and software are allowed to modify this bit on ly during debug or compliance testing. 11:5 reserved 4 enter compliance (ec) r/w. software is permitted to force a link to enter compliance mode at the speed indicated in th e target link speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link. 3:0 target link speed (tls) ? r/w. this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences. 0001b = 2.5 gt/s target link speed 0010b = 5.0 gt/s and 2.5 gt/s target link speeds all other values reserved.
pci express* configuration registers 784 datasheet 19.1.39 lsts2link status 2 register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 72h?73h attribute: ro default value: 0000h size: 16 bits 19.1.40 midmessage signaled in terrupt identifiers register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 80h?81h attribute: ro default value: 9005h size: 16 bits 19.1.41 mcmessage signaled inte rrupt message control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 82?83h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:1 reserved 0 current de-emphasis level (cdl) ? ro. when the link is operating at 5 gt/s speed, this bit reflects the level of de-emphasis. encodings: 0 = 6 db 1 = 3.5 db the value in this bit is undefined when the link is operating at 2.5 gt/s speed. bit description 15:8 next pointer (next) ? ro. indicates the location of the next pointer in the list. 7:0 capability id (cid) ? ro. capabilities id indicates msi. bit description 15:8 reserved 7 64 bit address capable (c64) ? ro. capable of generating a 32-bit message only. 6:4 multiple message enable (mme) ? r/w. these bits are r/w for software compatibility, but only one message is ever sent by the root port. 3:1 multiple message capable (mmc) ? ro. only one message is required. 0 msi enable (msie) ? r/w. 0 = msi is disabled. 1 = msi is enabled and traditional interrupt pins are not used to generate interrupts. note: cmd.bme (d28:f0/f1/f2/f3/f4/f5/f6/f7:04h:bit 2) must be set for an msi to be generated. if cmd.bme is cleared, and this bit is set, no interrupts (not even pin based) are generated.
datasheet 785 pci express* configuration registers 19.1.42 mamessage signaled interrupt message address register (pci express*d28 :f0/f1/f2/f3/f4/f5/f6/f7) address offset: 84h ? 87h attribute: r/w default value: 00000000h size: 32 bits 19.1.43 mdmessage signaled in terrupt message data register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 88h ? 89h attribute: r/w default value: 0000h size: 16 bits 19.1.44 svcapsubsystem ve ndor capability register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 90h ? 91h attribute: ro default value: a00dh size: 16 bits 19.1.45 svidsubsystem vendor identification register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 94h ? 97h attribute: r/wo default value: 00000000h size: 32 bits bit description 31:2 address (addr) ? r/w. lower 32 bits of the sy stem specified message address, always dw aligned. 1:0 reserved bit description 15:0 data (data) ? r/w. this 16-bit field is programm ed by system software if msi is enabled. its content is driven onto the lo wer word (pci ad[15:0]) during the data phase of the msi memory write transaction. bit description 15:8 next capability (next) ? ro. indicates the location of the next pointer in the list. 7:0 capability identifier (cid) ? ro. value of 0dh indicates this is a pci bridge subsystem vendor capability. bit description 31:16 subsystem identifier (sid) ? r/wo. indicates the subsystem as identified by the vendor. this field is write once and is locked down until a bridge reset occurs (not the pci bus reset). 15:0 subsystem vendor identifier (svid) ? r/wo. indicates the manufacturer of the subsystem. this field is write once and is lo cked down until a bridge reset occurs (not the pci bus reset).
pci express* configuration registers 786 datasheet 19.1.46 pmcappower management capability register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: a0h ? a1h attribute: ro default value: 0001h size: 16 bits 19.1.47 pmcpci power manageme nt capabilities register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: a2h ? a3h attribute: ro default value: c802h size: 16 bits bit description 15:8 next capability (next) ? ro. indicates this is the last item in the list. 7:0 capability identifier (cid) ? ro. value of 01h indicates this is a pci power management capability. bit description 15:11 pme_support (pmes) ? ro. indicates pme# is supported for states d0, d3 hot and d3 cold . the root port does not ge nerate pme#, but reporting th at it does is necessary for some legacy operating systems to enable pme# in devices connected behind this root port. 10 d2_support (d2s) ? ro. the d2 state is not supported. 9 d1_support (d1s) ? ro the d1 state is not supported. 8:6 aux_current (ac) ? ro. reports 375 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi) ? ro. 1 = indicates that no device-specific initialization is required. 4reserved 3 pme clock (pmec) ? ro. 1 = indicates that pci clock is not required to generate pme#. 2:0 version (vs) ? ro. indicates support for revision 1.1 of the pci power management specification .
datasheet 787 pci express* configuration registers 19.1.48 pmcspci power mana gement control and status register (pci express*d28 :f0/f1/f2/f3/f4/f5/f6/f7) address offset: a4h ? a7h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 31:24 reserved 23 bus power / clock control enable (bpce) ? reserved per pci express* base specification, revision 1.0a . 22 b2/b3 support (b23s) ? reserved per pci express* base specification, revision 1.0a . 21:16 reserved 15 pme status (pmes) ? ro. 1 = indicates a pme was receiv ed on the downstream link. 14:9 reserved 8 pme enable (pmee) ? r/w. 1 = indicates pme is enabled. the root port ta kes no action on this bit, but it must be r/w for some legacy operating systems to enable pme# on devices connected to this root port. this bit is sticky and resides in the resume well. the reset for this bit is rsmrst# which is not asserted du ring a warm reset. 7:2 reserved 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the root port and to set a new power state. the values are: 00 = d0 state 11 = d3 hot state note: when in the d3 hot state, the controller?s config uration space is available, but the i/o and memory spaces are not. type 1 configuration cycles are also not accepted. interrupts are not required to be blocked as software will disable interrupts prior to placing the port into d3 hot . if software attempts to write a ?10? or ?01? to these bits, the write will be ignored.
pci express* configuration registers 788 datasheet 19.1.49 mpc2miscellaneous port configuration register 2 (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: d4h ? d7h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 31:5 reserved 4 aspm control override enable (aspmcoen) ? r/w. 1 = root port will use the values in the aspm control ov erride registers 0 = root port will use the aspm regi sters in the link control register. notes: this register allows bios to control th e root port aspm settings instead of the os. 3:2 aspm control override (aspmo) ? r/w. provides bios control of whether root port should enter l0s or l1 or both. 00 = disabled 01 = l0s entry enabled 10 = l1 entry enabled 11 = l0s and l1 entry enabled. 1 eoi forwarding disable (eoifd) ? r/w. when set, eoi messages are not claimed on the backbone by this port an wi ll not be forwarded across the pcie link. 0 = broadcast eoi messages that are sent on the backbone are claimed by this port and forwarded ac ross the pcie link. 1 = broadcast eoi messages ar e not claimed on the backbone by this port and will not be forwarded across the pcie link. 0 l1 completion timeout mode (lictm) ? r/w. 0 = pci express specification compliant. completion timeout is disabled during software initiated l1, and enabled during aspm initiate l1. 1 = completion timeout is enabled during l1, regardless of how l1 entry was initiated.
datasheet 789 pci express* configuration registers 19.1.50 mpcmiscellaneous port configuration register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: d8h ? dbh attribute: r/w, ro default value: 08110000h size: 32 bits bit description 31 power management sc i enable (pmce) ? r/w. 0 = sci generation based on a powe r management event is disabled. 1 = enables the root port to generate sc i whenever a power management event is detected. 30 hot plug sci enable (hpce) ? r/w. 0 = sci generation based on a hot-plug event is disabled. 1 = enables the root port to generate sc i whenever a hot-plug event is detected. 29 link hold off (lho) ? r/w. 1 = port will not take any tlp. this is used during loopback mode to fill up the downstream queue. 28 address translator enable (ate) ? r/w. this bit is used to enable address translation using the at bits in th is register during loopback mode. 0 = disable 1 = enable 27 lane reversal (lr) ? ro. this register reads the settin g of the pcielr1 soft strap. 0 = pci express lanes 0-3 are reversed. 1 = no lane reversal (default). note: the port configuration straps must be set such that port 1 or port 5 is configured as a x4 port using lanes 0?3, or 4?7 when lane reversal is enabled. x2 lane reversal is not supported. note: this register is only valid on port 1 (f or ports 1?4) or port 5 (for ports 5?8). 26 invalid receive bus number check enable (irbnce) ? r/w. when set, the receive transaction layer will signal an e rror if the bus number of a memory request does not fall within the range between scbn and sbbn. if this chec k is enabled and the request is a memory write, it is treated as an unsupported reques t. if this check is enabled and the request is a non-posted memory read reques t, the request is considered a malformed tlp and a fatal error. messages, i/o, config, and completions are never checked fo r valid bus number. 25 invalid receive range check enable (irrce) ? r/w. when set, the receive transaction layer will treat the tlp as an unsupported request error if the address range of a memory request does not outside the range between prefetchable and non- prefetchable base and limit. messages, i/o, configuration, and comple tions are never checked for valid address ranges. 24 bme receive check enable (bmerce) ? r/w. when set, the receive transaction layer will treat the tlp as an unsupported request error if a memory read or write request is received and the bus master enable bit is not set. messages, i/o, config, and comple tions are never checked for bme. 23 reserved 22 detect override (forcedet) ? r/w. 0 = normal operation. detected output fro m afe is sampled for presence detection. 1 = override mode. ignores afe de tect output and link training proceeds as if a device were detected.
pci express* configuration registers 790 datasheet 21 flow control during l1 entry (fcdl1e) ? r/w. 0 = no flow control update dllps se nt during l1 ack transmission. 1 = flow control update dllps sent during l1 ack transmission as required to meet the 30 ? s periodic flow control update. 20:18 unique clock exit latency (ucel) ? r/w. this value represents the l0s exit latency for unique-clock configurations (lctl.ccc = 0) (d28:f0 /f1/f2/f3/f4/f5/f6/ f7:offset 50h:bit 6). it defaults to 512 ns to less than 1 s, bu t may be overridden by bios. 17:15 common clock exit latency (ccel) ? r/w. this value represents the l0s exit latency for common-clock configurations (lctl.ccc = 1) (d28:f0/f1/f2/f3/f4/f5/f6/ f7:offset 50h:bit 6). it defaults to 128 ns to less than 256 ns, but may be overridden by bios. 14 pcie gen2 speed disable 0 = pcie supported data rate is defined as set through supported link speed and target link speed settings. 1 = pcie supported data rate is limited to 2.5 gt/s (g en1). supported link speed register bits will reflect ?0001b? when this bit is set. when this bit is changed, link retrain ne eds to be performed for the change to be effective. 13:8 reserved 7 port i/oxapic enable (pae) ? r/w. 0 = hole is disabled. 1 = a range is opened through the bri dge for the following memory addresses: 6:3 reserved 2 bridge type (bt) ? r/wo. this register can be used to modify the base class and header type fields from the de fault pci-to-pci bridge to a host bridge. having the root port appear as a host bridge is us eful in some server configurations. 0 = the root port bridge type is a pci- to-pci bridge, header sub-class = 04h, and he ader ty pe = ty pe 1. 1 = the root port bridge type is a pci- to-pci bridge, header sub-class = 00h, and he ader ty pe = ty pe 0. 1 hot plug smi enable (hpme) ? r/w. 0 = smi generation based on a hot-plug event is disabled. 1 = enables the root port to generate sm i whenever a hot-plug event is detected. 0 power management smi enable (pmme) ? r/w. 0 = smi generation based on a powe r management event is disabled. 1 = enables the root port to generate sm i whenever a power management event is detected. bit description port # address 1 fec1_0000h ? fec1_7fffh 2 fec1_8000h ? fec1_ffffh 3 fec2_0000h ? fec2_7fffh 4 fec2_8000h ? fec2_ffffh 5 fec3_0000h ? fec3_7fffh 6 fec3_8000h ? fec3_ffffh 7 fec4_0000h ? fec4_7fffh 8 fec4_8000h ? fec4_ffffh
datasheet 791 pci express* configuration registers 19.1.51 smscssmi/sci status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: dch ? dfh attribute: r/wc default value: 00000000h size: 32 bits bit description 31 power management sci status (pmcs) ? r/wc. 1 = pme control logic needs to generate an interrupt, and this interrupt has been routed to generate an sci. 30 hot plug sci status (hpcs) ? r/wc. 1 = hot-plug controller needs to generate an interrupt, an d has this interrupt been routed to generate an sci. 29:5 reserved 4 hot plug link active state changed smi status (hplas) ? r/wc. 1 = slsts.lasc (d28:f0/f1/f2/f3/f4/f5/f6/f7:5a, bit 8) transitioned from 0-to-1, and mpc.hpme (d28:f0/f1/f2/f3/f4/f5/f6/f7:d8, bit 1) is set. when this bit is set, an smi# will be generated. 3:2 reserved 1 hot plug presence detect smi status (hppdm) ? r/wc. 1 = slsts.pdc (d28:f0/f1/f2/f3/f4/f5/f6/f7: 5a, bit 3) transitioned from 0-to-1, and mpc.hpme (d28:f0/f1/f2/f3/f4/f5/f6/f7:d8, bit 1) is set. when this bit is set, an smi# will be generated. 0 power management smi status (pmms) ? r/wc. 1 = rsts.ps (d28:f0/f1/f2/f3/f4/f5/f6/f7:60, bit 16) transitioned from 0-to-1, and mpc.pmme (d28:f0/f1/f2/f3/f4/f5/f6/f7:d8, bit 1) is set.
pci express* configuration registers 792 datasheet 19.1.52 rpdcgenroot port dy namic clock gating enable register (pci expressd28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: e1h attribute: r/w default value: 00h size: 8-bits 19.1.53 pecr1pci express* configuration register 1 (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: e8h?ebh attribute: r/w default value: 00000020h size: 32 bits bits description 7:4 reserved. ro 3 shared resource dynamic link cl ock gating enable (srdlcgen) r/w. 0 = disables dynamic clock gating of th e shared resource link clock domain. 1 = enables dynamic clock gating on the root port shared resource link clock domain. only the value from port 1 is used for ports 1?4. only the value from port 5 is used for ports 5?8. 2 shared resource dynamic backbone clock gate enable (srdbcgen) r/w. 0 = disables dynamic clock gating of the shared resource backbone clock domain. 1 = enables dynamic clock gati ng on the root port shared resource backbone clock domain. only the value from port 1 is used for ports 1?4. only the value from port 5 is used for ports 5?8. 1 root port dynamic link cloc k gate enable (rpdlcgen) r/w. 0 = disables dynamic clock gating of the root port link clock domain. 1 = enables dynamic clock gating on the root port link clock domain. 0 root port dynamic backbone cl ock gate enable (rpdbcgen) r/w. 0 = disables dynamic clock gating of th e root port backbone clock domain. 1 = enables dynamic clock gating on th e root port backbone clock domain. bit description 31:2 reserved 1 pecr1 field 2 ? r/w. bios may set this bit to 1. 0 reserved
datasheet 793 pci express* configuration registers 19.1.54 pecr3pci express* configuration register 3 (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: ech?efh attribute: r/w default value: 00000000h size: 32 bits bit description 31:2 reserved 1 subtractive decode compatibility device id (sdcdid) ? r/w. 0 = this function reports the device device id value assigned to the pci express root ports listed in section . 1 = this function reports a device id of 244eh for desktop or 2448h for mobile. if subtractive decode (sde) is enabled, havi ng this bit as '0' allows the function to present a device id that is recognized by the os. 0 subtractive decode enable (sde) ? r/w. 0 = subtractive decode is disabled this fu nction and will only claim transactions positively. 1 = this port will subtractively forward tran sactions across the pcie link downstream memory and io transactions that are not positively claimed an y internal device or bridge. software must ensu re that only one pch device is enabled for subtractive decode at a time.
pci express* configuration registers 794 datasheet 19.1.55 uesuncorrectable error status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 104h ? 107h attribute: r/wc, ro default value: 00000000000x0xxx 0x0x0000000x0000b size: 32 bits this register maintains its state through a platform reset. it loses its state upon suspend. bit description 31:21 reserved 20 unsupported request error status (ure) ? r/wc. indicates an unsupported request was received. 19 ecrc error status (ee) ? ro. ecrc is not supported. 18 malformed tlp status (mt) ? r/wc. indicates a malformed tlp was received. 17 receiver overflow status (ro) ? r/wc. indicates a receiver overflow occurred. 16 unexpected completion status (uc) ? r/wc. indicates an unexpected completion was received. 15 completion abort status (ca) ? r/wc. indicates a completer abort was received. 14 completion timeout status (ct) ? r/wc. indicates a completion timed out. this bit is set if completion timeout is enabled and a completion is not returned within the time specified by the completion timeout value 13 flow control protocol error status (fcpe) ? ro. flow control protocol errors not supported. 12 poisoned tlp status (pt) ? r/wc. indicates a poisoned tlp was received. 11:5 reserved 4 data link protocol error status (dlpe) ? r/wc. indicates a data link protocol error occurred. 3:1 reserved 0 training error status (te) ? ro. training errors not supported.
datasheet 795 pci express* configuration registers 19.1.56 uemuncorrectable error mask register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 108h ? 10bh attribute: r/wo, ro default value: 00000000h size: 32 bits when set, the corresponding error in the ue s register is masked, and the logged error will cause no action. when cleared, the corresponding error is enabled. bit description 31:21 reserved 20 unsupported request error mask (ure) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is masked. 19 ecrc error mask (ee) ? ro. ecrc is not supported. 18 malformed tlp mask (mt) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is masked. 17 receiver overflow mask (ro) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is masked. 16 unexpected completion mask (uc) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is masked. 15 completion abort mask (ca) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is masked. 14 completion timeout mask (ct) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is masked. 13 flow control protocol error mask (fcpe) ? ro. flow control protocol errors not supported. 12 poisoned tlp mask (pt) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is masked. 11:5 reserved
pci express* configuration registers 796 datasheet 19.1.57 uev uncorrectable error severity register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 10ch ? 10fh attribute: ro, r/w default value: 00060011h size: 32 bits 4 data link protocol error mask (dlpe) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3/f4/f5/f6/f7:144) is masked. 3:1 reserved 0 training error mask (te) ? ro. training errors not supported bit description bit description 31:21 reserved 20 unsupported request error severity (ure) ? r/w. 0 = error considered no n-fatal. (default) 1 = error is fatal. 19 ecrc error severity (ee) ? ro. ecrc is not supported. 18 malformed tlp severity (mt) ? r/w. 0 = error considered non-fatal. 1 = error is fatal. (default) 17 receiver overflow severity (ro) ? r/w. 0 = error considered non-fatal. 1 = error is fatal. (default) 16 reserved 15 completion abort severity (ca) ? r/w. 0 = error considered no n-fatal. (default) 1 = error is fatal. 14 reserved 13 flow control protocol error severity (fcpe) ? ro. flow control protocol errors not supported. 12 poisoned tlp severity (pt) ? r/w. 0 = error considered no n-fatal. (default) 1 = error is fatal. 11:5 reserved 4 data link protocol error severity (dlpe) ? r/w. 0 = error considered non-fatal. 1 = error is fatal. (default) 3:1 reserved 0 training error severity (te) ? r/w. te is not supported.
datasheet 797 pci express* configuration registers 19.1.58 ces correctable error status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 110h ? 113h attribute: r/wc default value: 00000000h size: 32 bits 19.1.59 cem corr ectable error mask register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 114h ? 117h attribute: r/wo default value: 00002000h size: 32 bits when set, the corresponding error in the ce s register is masked, and the logged error will cause no action. when cleared, the corresponding error is enabled. bit description 31:14 reserved 13 advisory non-fatal error status (anfes) ? r/wc. 0 = advisory non-fatal error did not occur. 1 = advisory non-fatal error did occur. 12 replay timer timeout status (rtt) ? r/wc. indicates the replay timer timed out. 11:9 reserved 8 replay number rollover status (rnr) ? r/wc. indicates the replay number rolled over. 7 bad dllp status (bd) ? r/wc. indicates a ba d dllp was received. 6 bad tlp status (bt) ? r/wc. indicates a bad tlp was received. 5:1 reserved 0 receiver error status (re) ? r/wc. indicates a receiver error occurred. bit description 31:14 reserved 13 advisory non-fatal error mask (anfem) ? r/wo. 0 = does not mask advisory non-fatal errors. 1 = masks advisory non-fatal errors from (a ) signaling err_cor to the device control register and (b) updating the unco rrectable error status register. this register is set by default to enable compatibility with soft ware that does not comprehend role-based error reporting. note: the correctable error detected bit in device status register is set whenever the advisory non-fatal error is detect ed, independent of this mask bit. 12 replay timer timeout mask (rtt) ? r/wo. mask for replay timer timeout. 11:9 reserved 8 replay number rollover mask (rnr) ? r/wo. mask for replay number rollover. 7 bad dllp mask (bd) ? r/wo. mask for bad dllp reception. 6 bad tlp mask (bt) ? r/wo. mask for bad tlp reception. 5:1 reserved 0 receiver error mask (re) ? r/wo. mask for receiver errors.
pci express* configuration registers 798 datasheet 19.1.60 aecc advanced error ca pabilities and control register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 118h ? 11bh attribute: ro default value: 00000000h size: 32 bits 19.1.61 res root erro r status register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 130h ? 133h attribute: r/wc, ro default value: 00000000h size: 32 bits bit description 31:9 reserved 8 ecrc check enable (ece) ? ro. ecrc is not supported. 7 ecrc check capable (ecc) ? ro. ecrc is not supported. 6 ecrc generation enable (ege) ? ro. ecrc is not supported. 5 ecrc generation capable (egc) ? ro. ecrc is not supported. 4:0 first error pointer (fep) ? ro. identifies the bit position of the last error reported in the uncorrectable erro r status register. bit description 31:27 advanced error interrupt message number (aemn) ? ro. there is only one error interrupt allocated. 26:7 reserved 6 fatal error messages received (femr) ? ro. set when one or more fatal uncorrectable error messag es have been received. 5 non-fatal error messages received (nfemr) ro. set when one or more non- fatal uncorrectable error me ssages have been received 4 first uncorrectable fatal (fuf) ro. set when the first uncorrectable error message received is for a fatal error. 3 multiple err_fatal/nonfatal received (menr) ? ro. for the pch, only one error will be captured. 2 err_fatal/nonfatal received (enr) ? r/wc. 0 = no error message received. 1 = either a fatal or a non-fatal error message is received. 1 multiple err_cor received (mcr) ? ro. for the pch, only one error will be captured. 0 err_cor received (cr) ? r/wc. 0 = no error message received. 1 = a correctable error message is received.
datasheet 799 pci express* configuration registers 19.1.62 pecr2 pci express* configuration register 2 (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 320?323h attribute: r/w default value: 60005007h size: 32 bits 19.1.63 peetm pci ex press* extended te st mode register (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 324h?327h attribute: ro default value: see description size: 32 bits 19.1.64 pec1 pci express* configuration register 1 (pci express*d28:f0/f1/f2/f3/f4/f5/f6/f7) address offset: 330h?333h attribute: ro, r/w default value: 14000016h size: 32 bits bit description 31:20 reserved 21 pecr2 field 1 ? r/w. bios must set this bit to 1b. 20:0 reserved bit description 31:3 reserved 2 scrambler bypass mode (bau) ? r/w. 0 = normal operation. scrambler and descrambler are used. 1 = bypasses the data scrambler in the transmit direction and the data de-scrambler in the receive direction. note: this functionality intended for debug/testing only. note: if bypassing scrambler with the pch root port 1 in x4 configuration, each pch root port must have this bit set. 1:0 reserved bit description 31:8 reserved 7:0 pec1 field 1 ? r/w. bios must program this field to 40h.
pci express* configuration registers 800 datasheet
datasheet 801 high precision event timer registers 20 high precision event timer registers the timer registers are memory-mapped in a non-indexed scheme. this allows the processor to directly access each register without having to use an index register. the timer register space is 1024 bytes. the registers are generally aligned on 64-bit boundaries to simplify implementation with ia64 processors. there are four possible memory address ranges beginning at 1) fed0_0000h, 2) fed0_1000h, 3) fed0_2000h, 4) fed0_3000h. the choice of address range will be selected by configuration bits in the high precision timer configuration register (chipset config registers:offset 3404h). behavioral rules: 1. software must not attempt to read or write across register boundaries. for example, a 32-bit access should be to offs et x0h, x4h, x8h, or xch. 32-bit accesses should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0ah, 0bh, 0dh, 0eh, or 0fh. any accesses to these offsets will result in an unexpected behavior, and may result in a master abort. however, these accesses should not result in system hangs. 64- bit accesses can only be to x0h and must not cross 64-bit boundaries. 2. software should not write to read only registers. 3. software should not expect any partic ular or consistent value when reading reserved registers or bits. 20.1 memory mapped registers table 20-1. memory-mapped regist er address map (sheet 1 of 2) offset mnemonic register default attribute 000h?007h gcap_id general capabi lities and identification 0429b17f80 86a201h ro 008h?00fh ? reserved ? ? 010h?017h gen_conf general configuration 0000000000 000000h r/w 018h?01fh ? reserved ? ? 020h?027h gintr_sta general interrupt status 0000000000 000000h r/wc 028h?0efh ? reserved ? ? 0f0h?0f7h main_cnt main counter value n/a r/w 0f8h?0ffh ? reserved ? ? 100h?107h tim0_conf timer 0 configuration and capabilities n/a r/w, ro 108h?10fh tim0_comp timer 0 comparator value n/a r/w 110h?11fh ? reserved ? ? 120h?127h tim1_conf timer 1 configuration and capabilities n/a r/w, ro
high precision event timer registers 802 datasheet notes: 1. reads to reserved registers or bits will return a value of 0. 2. software must not at tempt locks to the memory-mapped i/o ranges for high precision event timers. if attempted, the lock is not honored, wh ich means potential deadlock conditions may occur. 128h?12fh tim1_comp timer 1 comparator value n/a r/w 130h?13fh ? reserved ? ? 140h?147h tim2_conf timer 2 configuration and capabilities n/a r/w, ro 148h?14fh tim2_comp timer 2 comparator value n/a r/w 150h?15fh ? reserved ? ? 160h?167h tim3_cong timer 3 configuration and capabilities n/a r/w, ro 168h?16fh tim3_comp timer 3 comparator value n/a r/w 180h?187h tim4_cong timer 4 configuration and capabilities n/a r/w, ro 188h?18fh tim4_comp timer 4 comparator value n/a r/w 190h?19fh ? reserved ? ? 1a0h?1a7h tim5_cong timer 5 configuration and capabilities n/a r/w, ro 1a8h?1afh tim5_comp timer 5 comparator value n/a r/w 1b0h?1bfh ? reserved ? ? 1c0h?1c7h tim6_cong timer 6 configuration and capabilities n/a r/w, ro 1c8h?1cfh tim6_comp timer 6 comparator value n/a r/w 1d0h?1dfh ? reserved ? ? 1e0h?1e7h tim7_cong timer 7 configuration and capabilities n/a r/w, ro 1e8h?1efh tim7_comp timer 7 comparator value n/a r/w 1f0h?19fh ? reserved ? ? 200h?3ffh ? reserved ? ? table 20-1. memory-mapped register address map (sheet 2 of 2) offset mnemonic register default attribute
datasheet 803 high precision event timer registers 20.1.1 gcap_idgeneral capabilitie s and identification register address offset: 00h attribute: ro default value: 0429b17f8086a201h size: 64 bits 20.1.2 gen_confgeneral configuration register address offset: 010h attribute: r/w default value: 00000000 00000000h size: 64 bits bit d escription 63:32 main counter tick period (counter_clk_p er_cap) ? ro. this field indicates the period at which the counter increments in femptoseconds (10^-15 seconds). this will return 0429b17fh when read. this in dicates a period of 69841279 fs (69.841279 ns). 31:16 vendor id capability (vendor_id_cap) ? ro. this is a 16-bit value assigned to intel. 15 legacy replacement rout capable (leg_r t_cap) ? ro. hardwired to 1. legacy replacement interrupt rout option is supported. 14 reserved. this bit returns 0 when read. 13 counter size capability (count_size_cap) ? ro. hardwired to 1. counter is 64-bit wide. 12:8 number of timer capability (num_tim_cap) ? ro. this fiel d indicates the number of timers in this block. 07h = eight timers. 7:0 revision identification (rev_id) ? ro. this indicates which revision of the function is implemented. default value will be 01h. bit description 63:2 reserved. these bits return 0 when read. 1 legacy replacement rout (leg_rt_cnf) ? r/w. if the enable_cnf bit and the leg_rt_cnf bit are both set, then the interrupts will be routed as follows: ? timer 0 is routed to irq0 in 8259 or irq2 in the i/o apic ? timer 1 is routed to irq8 in 8259 or irq8 in the i/o apic ? timer 2-n is routed as per the routing in the timer n config registers. ? if the legacy replacement rout bit is set, the in dividual routing bits for timers 0 and 1 (apic) will have no impact. ? if the legacy replacement rout bit is not set, th e individual routing bits for each of the timers are used. ? this bit will default to 0. bios can set it to 1 to enable the legacy replacement routing, or 0 to disable the legacy replacement routing. 0 overall enable (enable_cnf) ? r/w. this bit must be set to enable any of the timers to generate interrupts. if this bit is 0, then the main counter will halt (will not increment) and no inte rrupts will be caused by any of these timers. for level-triggered interrupts, if an interrupt is pending when the enable_cnf bit is changed from 1 to 0, the interrupt status indications (in the various txx_int_sts bits) will not be cleared. software must write to the txx_in t_sts bits to clear the interrupts. note: this bit will default to 0. bios can set it to 1 or 0.
high precision event timer registers 804 datasheet 20.1.3 gintr_stageneral interrupt status register address offset: 020h attribute: r/wc default value: 00000000 00000000h size: 64 bits 20.1.4 main_cntmain counter value register address offset: 0f0h attribute: r/w default value: n/a size: 64 bits bit de scription 63:8 reserved. these bits wi ll return 0 when read. 7 timer 7 interrupt active (t07_int_sts) ? r/wc. same functionality as timer 0. 6 timer 6 interrupt active (t06_int_sts) ? r/wc. same functionality as timer 0. 5 timer 5 interrupt active (t05_int_sts) ? r/wc. same functionality as timer 0. 4 timer 4 interrupt active (t04_int_sts) ? r/wc. same functionality as timer 0. 3 timer 3 interrupt active (t03_int_sts) ? r/wc. same functionality as timer 0. 2 timer 2 interrupt active (t02_int_sts) ? r/wc. same functionality as timer 0. 1 timer 1 interrupt active (t01_int_sts) ? r/wc. same functionality as timer 0. 0 timer 0 interrupt active (t00_int_sts) ? r/wc. the functionality of this bit depends on whether the edge or level-triggered mode is used for this timer. (default = 0) if set to level-triggered mode: this bit will be set by hardware if the corresponding timer interru pt is active. once the bit is set, it can be cl eared by software writing a 1 to the same bit position. writes of 0 to this bit will have no effect. if set to edge-triggered mode: this bit should be ignored by software. so ftware should always write 0 to this bit. note: defaults to 0. in edge triggered mode, th is bit will always re ad as 0 and writes will have no effect. bit de scription 63:0 counter value (counter_val[63:0]) ? r/w. reads return the current value of the counter. writes load the new value to the counter. notes: 1. writes to this register should only be done while the counter is halted. 2. reads to this register return th e current value of the main counter. 3. 32-bit counters will always return 0 for the upper 32-bits of this register. 4. if 32-bit software attempts to read a 64-bit counter, it should first halt the counter. since this delays the interrupts for all of the timers, this should be done only if the consequences are understood. it is strongly recommended that 32-bit software only operate the timer in 32-bit mode. 5. reads to this register are monotonic. no two consecutive re ads return the same value. the second of two reads always re turns a larger value (unless the timer has rolled over to 0).
datasheet 805 high precision event timer registers 20.1.5 timn_conftimer n conf iguration and capabilities register address offset: timer 0: 100?107h, attribute: ro, r/w timer 1: 120?127h, timer 2: 140?147h, timer 3: 160?167h, timer 4: 180?187h, timer 5: 1a0?1a7h, timer 6: 1c0?1c7h, timer 7: 1e0?1e7h, default value: n/a size: 64 bit note: the letter n can be 0, 1, 2, 3, 4, 5, 6, or 7 referring to timer 0, 1, 2, 3, 4, 5, 6, or 7. bit description 63:56 reserved. these bits wi ll return 0 when read. 55:52, 43 timer interrupt rout capabi lity (timern_int_rout_cap) ? ro. timer 0, 1:bits 52, 53, 54, and 55 in this field (corresponding to irq 20, 21, 22, and 23) have a value of 1. writes will have no effect. timer 2:bits 43, 52, 53, 54, and 55 in this field (corresponding to irq 11, 20, 21, 22, and 23) have a value of 1. wr ites will have no effect. timer 3:bits 44, 52, 53, 54, and 55 in this field (corresponding to irq 11, 20, 21, 22, and 23) have a value of 1. wr ites will have no effect. timer 4, 5, 6, 7:this field is always 0 as interrupts from these timers can only be delivered using direct proc essor interrupt messages. note: if irq 11 is used for hpet #2, software should ensure irq 11 is not shared with any other devices to ensure the proper operation of hpet #2. note: if irq 12 is used for hpet #3, software should ensure irq 12 is not shared with any other devices to ensure the proper operation of hpet #3. 51:45, 42:16 reserved . these bits return 0 when read. 15 timer n processor message interrupt deli very (tn_procmsg_int_del_cap) ? ro. this bit is always read as ?1?, since the pch hpet implementation supports the direct processor interrupt delivery. 14 timer n processor messa ge interrupt enable (tn_procmsg_en_cnf) ? r/w / ro. if the tn_procmsg_int_d el_cap bit is set for this timer, then the software can set the tn_procmsg_en_cnf bit to force the interrupts to be delivered directly as processor messages, rather than using th e 8259 or i/o (x) apic. in this case, the tn_int_rout_cnf field in this register will be ignored. the tn_procmsg_rout register will be used instead. timer 0, 1, 2, 3 specific: th is bit is a read/write bit. timer 4, 5, 6, 7 specific: this bit is al ways read only ?1? as interrupt from these timers can only be delivered using direct processor in terrupt messages.
high precision event timer registers 806 datasheet 13:9 timer n interrupt rout (tn_int_rout_cnf) ? r/w / ro. this 5-bit field indicates the routing for the interrupt to the 8259 or i/o (x) apic. software writes to this field to select which interrupt in the 8259 or i/o (x) will be used for this timer?s interrupt. if the value is not supported by th is particular timer, then the value read back will not match what is written. the software must only write valid values. timer 4, 5, 6, 7: this field is read only and reads will return 0. notes: 1. if the interrupt is handled using the 8259, only interrupts 0?15 are applicable and valid. software must not program an y value other than 0?15 in this field. 2. if the legacy replacement rout bit is set, then timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers. 3. timer 0,1: software is responsible to make sure it programs a valid value (20, 21, 22, or 23) for this field. the pch lo gic does not check the validity of the value written. 4. timer 2: software is responsible to ma ke sure it programs a valid value (11, 20, 21, 22, or 23) for this field. the pch logic does not check the validity of the value written. 5. timer 3: software is responsible to ma ke sure it programs a valid value (12, 20, 21, 22, or 23) for this field. the pch logic does not check the validity of the value written. 6. timers 4, 5, 6, 7: this field is alwa ys read only 0 as in terrupts from these timers can only be delivered using direct processor in terrupt messages. 8 timer n 32-bit mode (timern_32mode_cnf) ? r/w or ro. software can set this bit to force a 64-bit timer to behave as a 32-bit timer. timer 0:bit is read/write (default to 0). 0 = 64 bit; 1 = 32 bit timers 1, 2, 3, 4, 5, 6, 7:hardwired to 0. writes have no effect (since these seven timers are 32-bits). note: when this bit is set to 1, the hardware counter will do a 32-bit operation on comparator match and rollovers; th us, the upper 32-bit of the timer 0 comparator value register is ignored. the upper 32-bit of the main counter is not involved in any rollover from lower 32-bit of the main counter and becomes all zeros. 7 reserved . this bit returns 0 when read. 6 timer n value set (timern_val_set_cnf) ? r/w. software uses this bit only for timer 0 if it has been set to periodic mode. by writing this bit to a 1, the software is then allowed to directly set the timer?s accumulator. software does not have to write this bit back to 1 (it automatically clears). software should not write a 1 to this bit position if the timer is set to non-periodic mode. note: this bit will return 0 when read. writes will only have an effect for timer 0 if it is set to periodic mode. writes will have no effect for timers 1, 2, 3, 4, 5, 6, 7. 5 timer n size (timern_size_cap) ? ro. this read only field indicates the size of the timer. timer 0:value is 1 (64-bits). timers 1, 2, 3, 4, 5, 6, 7: value is 0 (32-bits). 4 periodic interrupt capable (timern_per_int_cap) ? ro. if this bit is 1, the hardware supports a periodic mo de for this timer?s interrupt. timer 0: hardwired to 1 (suppo rts the periodic interrupt). timers 1, 2, 3, 4, 5, 6, 7: hardwired to 0 (does not support periodic interrupt). bit description
datasheet 807 high precision event timer registers note: reads or writes to unimpleme nted timers should not be attempted. read from any unimplemented registers will re turn an undetermined value. 3 timer n type (timern_type_cnf) ? r/w or ro. timer 0:bit is read/write. 0 = disable ti mer to generate periodic interrupt; 1 = enable timer to generate a periodic interrupt. timers 1, 2, 3, 4, 5, 6, 7: hard wired to 0. writes have no affect. 2 timer n interrupt enable (timern_int_enb_cnf) ? r/w. this bi t must be set to enable timer n to cause an interrupt when it times out. 0 = disable (default). the timer can still co unt and generate appr opriate status bits, but will not cause an interrupt. 1 = enable. 1 timer interrupt type (timern_int_type_cnf) ? r/w. 0 = the timer interrupt is edge triggered. this means that an edge-type interrupt is generated. if another in terrupt occurs, an other edge will be generated. 1 = the timer interrupt is level triggered. this means that a leve l-triggered interrupt is generated. the interrupt will be held active until it is cleared by writing to the bit in the general interrupt status register . if another interrupt occurs before the interrupt is cleared, the in terrupt will remain active. timer 4, 5, 6, 7: this bit is read only, and will return 0 when read 0 reserved . these bits will return 0 when read. bit description
high precision event timer registers 808 datasheet 20.1.6 timn_comptimer n co mparator value register address offset: timer 0: 108h?10fh, timer 1: 128h?12fh, timer 2: 148h?14fh, timer 3: 168h?16fh, timer 4: 188h?18fh, timer 5: 1a8h?1afh, timer 6: 1c8h?1cfh, timer 7: 1e8h?1efh attribute: r/w default value: n/a size: 64 bit bit de scription 63:0 timer compare value ? r/w. reads to this register return the current value of the comparator if timer n is configured to non-periodic mode: writes to this register load the value against which the main counter should be compared for this timer. ? when the main counter equals the value last written to this regi ster, the corresponding interrupt can be generated (if so enabled). ? the value in this register does not change based on the interrupt being generated. if timer 0 is configured to periodic mode: ? when the main counter equals the value last written to this regi ster, the corresponding interrupt can be generated (if so enabled). ? after the main counter equals the value in this register, the value in this register is increased by the value last written to the register. for example, if the value written to the register is 00000123h, then 1. an interrupt will be generated when the main counter reaches 00000123h. 2. the value in this register will then be adjusted by the hardware to 00000246h. 3. another interrupt will be generated when the main counter reaches 00000246h 4. the value in this register will then be adjusted by the hardware to 00000369h ? as each periodic interrupt occurs, the value in this register will increment. when the incremented value is greater than the maximum value possible for this register (ffffffffh for a 32-bit timer or ffffffffffffffffh for a 64-bit timer), the value will wrap around through 0. for example, if the current value in a 32-bit timer is ffff0000h and the last value written to this register is 20000h, then after the next interrupt the value will change to 00010000h default value for each timer is all 1s for th e bits that are implemented. for example, a 32-bit timer has a default value of 00000000ffffffffh. a 64-bit timer has a default value of ffffffffffffffffh.
datasheet 809 high precision event timer registers 20.1.7 timern_procmsg_routt imer n processor message interrupt rout register address offset: timer 0: 110?117h, attribute: r/w timer 1: 130?137h, timer 2: 150?157h, timer 3: 170?177h, timer 4: 190?197h, timer 5: 1b0?1b7h, timer 6: 1d0?1d7h, timer 7: 1f0?1f7h, default value: n/a size: 64 bit note: the letter n can be 0, 1, 2, 3, 4, 5, 6, or 7 referring to timer 0, 1, 2, 3, 4, 5, 6, or 7. software can access the various bytes in this register using 32-bit or 64-bit accesses. 32-bit accesses can be done to offset 1x0h or 1x4h. 64-bit accesses can be done to 1x0h. 32-bit accesses must not be done to offsets 1x1h, 1x2h, 1x3h, 1x5h, 1x6h, or 1x7h. bit description 63:32 tn_procmsg_int_addr ? r/w. software sets this 32 -bit field to indicate the location that the direct processor interrupt mess age should be written. 31:0 tn_procmsg_int_val ? r/w. software sets this 32-bit field to indicate that value that is written during the direct processor interrupt message.
high precision event timer registers 810 datasheet
datasheet 811 serial peripheral interface (spi) 21 serial peripheral interface (spi) the serial peripheral interface resides in me mory mapped space. this function contains registers that allow for the setup and programming of devices that reside on the spi interface. note: all registers in this function (including me mory-mapped registers) must be addressable in byte, word, and dword quantities. the software must always make register accesses on natural boundaries (that is, dword accesses must be on dword boundaries; word accesses on word boundaries, etc.) in ad dition, the memory-mapped register space must not be accessed with the lock semantic exclusive-access mechanism. if software attempts exclusive-access mechanisms to the spi memory-mapped space, the results are undefined. 21.1 serial peripheral interface memory mapped configuration registers the spi host interface registers are memory-mapped in the rcrb (root complex register block) chipset register space with a base address (spibar) of 3800h and are located within the range of 3800h to 39ffh . the address for rcrb can be found in rcba register see section 13.1.37 . the individual registers are then accessible at spibar + offset as indicated in the following table. these memory mapped registers must be accessed in byte, word, or dword quantities. table 21-1. serial peripheral inte rface (spi) register address map (spi memory mapped configuratio n registers) (sheet 1 of 2) spibar + offset mnemonic register name default 00h?03h bfpr bios flash primary region 00000000h 04h?05h hsfs hardware sequencing flash status 0000h 06h?07h hsfc hardware sequencing flash control 0000h 08h?0bh faddr flash address 00000000h 0ch?0fh ? reserved 00000000h 10h?13h fdata0 flash data 0 00000000h 14h?4fh fdatan flash data n 00000000h 50h?53h frap flash region access permissions 00000202h 54h?57h freg0 flash region 0 00000000h 58h?5bh freg1 flash region 1 00000000h 5ch?5fh freg2 flash region 2 00000000h 60h?63h freg3 flash region 3 00000000h 64h?67h freg4 flash region 4 00000000h 67h?73h ? reserved for future flash regions 74h?77h pr0 flash protected range 0 00000000h
serial peripheral interface (spi) 812 datasheet 78h?7bh pr1 flash protected range 1 00000000h 7ch?7fh pr2 flash protected range 2 00000000h 80h?83h pr3 flash protected range 3 00000000h 84h?87h pr4 flash protected range 4 00000000h 88h?8fh ? reserved ? 90h ssfs software sequencing flash status 00h 91h?93h ssfc software sequencing flash control 0000h 94h?95h preop prefix opcode configuration 0000h 96h?97h optype opcode type configuration 0000h 98h?9fh opmenu opcode menu configuration 0000000000000 000h a0h bbar bios base address configuration 00000000h b0h?b3h fdoc flash descriptor observability control 00000000h b4h?b7h fdod flash descriptor observability data 00000000h b8h?c3h ? reserved ? c0h?c3h afc additional flash control 00000000h c4h?c7h lvscc host lower vendor specific component capabilities 00000000h c8h?c11h uvscc host upper vendor specific component capabilities 00000000h d0h?d3h fpb flash partition boundary 00000000h f0h?f3h srdl soft reset data lock 00000000h f4h?f7h srdc soft reset data control 00000000h f8h?fbh srd soft reset data 00000000h table 21-1. serial peripheral inte rface (spi) register address map (spi memory mapped configuration register s) (sheet 2 of 2) spibar + offset mnemonic register name default
datasheet 813 serial peripheral interface (spi) 21.1.1 bfpr Cbios flash pr imary region register (spi memory mapped configuration registers) memory address: spibar + 00h attribute: ro default value: 00000000h size: 32 bits note: this register is only applicable when spi device is in descriptor mode. 21.1.2 hsfshardware sequencing flash status register (spi memory mapped configuration registers) memory address: spibar + 04h attribute: ro, r/wc, r/w default value: 0000h size: 16 bits bit description 31:29 reserved 28:16 bios flash primary re gion limit (prl) ro. this specifies address bits 24:12 for the primary region limit. the value in this register loaded from the contents in the flash descriptor.flreg 1.region limit 15:13 reserved 12:0 bios flash primary region base (prb) ? ro. this specifies address bits 24:12 for the primary region base the value in this register is load ed from the contents in the flash descriptor.flreg1.region base bit description 15 flash configuration lock-down (flockdn) ? r/w/l. when set to 1, those flash program registers that are locked down by this flockdn bit cannot be written. once set to 1, this bit can only be cleared by a hardware reset du e to a global reset or host partition reset in an intel ? me enabled system. 14 flash descriptor valid (fdv) ro. this bit is set to a 1 if the flash controller read the correct flash descriptor signature. if the flash descriptor valid bit is not 1, software cannot use the hardware sequencing registers, but must use the software sequencing registers. any attempt to use the hardware sequencing registers will result in the fcerr bit being set. 13 flash descriptor override pin-strap status (fdopss) ? ro. this bit indicates the condition of the flash descriptor security override / intel me debug mode pin-strap. 0 = the flash descriptor secu rity override / intel me de bug mode strap is set using external pull-up on hda_sdo 1 = no override 12:6 reserved 5 spi cycle in progress (scip) ro. hardware sets this bi t when software sets the flash cycle go (fgo) bit in the hardware se quencing flash control register. this bit remains set until the cycle completes on the spi interface. hardware automatically sets and clears this bit so that software can dete rmine when read data is valid and/or when it is safe to begin programming the next command. software must only program the next command when this bit is 0. note: this field is only applicable when in descriptor mode and hardware sequencing is being used.
serial peripheral interface (spi) 814 datasheet 4:3 block/sector eras e size (berase) ? ro. this field identifies the erasable sector size for all flash components. valid bit settings: 00 = 256 byte 01 = 4 k byte 10 = 8 k byte 11 = 64 k byte if the fla is less than fpba, then this field reflects the valu e in the lvscc.lbes register. if the fla is greater or equal to fpba, then this field reflects the value in the uvscc.ubes register. note: this field is only applicable when in descriptor mode and hardware sequencing is being used. 2 access error log (ael) ? r/w/c. hardware sets this bit to a 1 when an attempt was made to access the bios regi on using the direct access method or an access to the bios program registers that violated the security restrictions. this bit is simply a log of an access security violat ion. this bit is cleared by software writing a 1. note: this field is only applicable when in descriptor mode and hardware sequencing is being used. 1 flash cycle error (fcerr) ? r/w/c. hardware sets this bit to 1 when an program register access is bl ocked to the flash due to one of the protection policies or when any of the programmed cycle re gisters is written while a programmed access is already in progress. this bit remains asserted until cleared by so ftware writing a 1 or until hardware reset occurs due to a global re set or host partition reset in an intel ? me enabled system. software must clear this bit before se tting the flash cycle go bit in this register. note: this field is only applicable when in descriptor mode and hardware sequencing is being used. 0 flash cycle done (fdone) ? r/w/c. the pch sets this bit to 1 when the spi cycle completes after software previously set the fgo bit. this bit re mains asserted until cleared by software writing a 1 or hardware re set due to a global re set or host partition reset in an intel ? me enabled system. when this bit is set and the spi smi# enable bit is set, an internal signal is asserted to the smi# generation block. software must make sure this bit is cleared prior to enabling the spi smi# assertion for a new programmed access. note: this field is only applicable when in descriptor mode and hardware sequencing is being used. bit description
datasheet 815 serial peripheral interface (spi) 21.1.3 hsfchardware sequencing flash control register (spi memory mapped configuration registers) memory address:spibar + 06h attribute: r/w, r/ws default value: 0000h size: 16 bits note: this register is only applicable when spi device is in descriptor mode. 21.1.4 faddrflash address register (spi memory mapped configuration registers) memory address: spibar + 08h attribute: r/w default value: 00000000h size: 32 bits bit description 15 flash spi smi# enable (fsmie) ? r/w. when set to 1, the spi asserts an smi# request whenever the flash cycle done bit is 1. 14 reserved 13:8 flash data byte count (fdbc) r/w. this field specifies the number of bytes to shift in or out during the data portion of the spi cycle. the contents of this register are 0s based with 0b representing 1 byte and 111111b representing 64 bytes. the number of bytes transferred is the value of this field plus 1. this field is ignored for the block erase command. 7:3 reserved 2:1 flash cycle (fcycle) ? r/w. this field defines the flash spi cycle type generated to the flash when the fgo bi t is set as defined below: 00 = read (1 up to 64 bytes by setting fdbc) 01 = reserved 10 = write (1 up to 64 bytes by setting fdbc) 11 = block erase 0 flash cycle go (fgo) ? r/w/s. a write to this register with a 1 in this bit initiates a request to the flash spi arbiter to start a cy cle. this register is cleared by hardware when the cycle is granted by the spi arbiter to run the cycle on the spi bus. when the cycle is complete, the fdone bit is set. software is forbidden to write to any regist er in the hsflctl register between the fgo bit getting set and the fdone bi t being cleared. any attempt to violate this rule will be ignored by hardware. hardware allows other bits in this register to be progra mmed for the same transaction when writing this bit to 1. this saves an addition al memory write. this bit always returns 0 on reads. bit description 31:25 reserved 24:0 flash linear address (fla) r/w. the fla is the starting byte linear address of a spi read or write cycle or an address within a block for the block erase command. the flash linear address must fall within a regi on for which bios has access permissions. hardware must convert the fla into a flash physical address (fpa) before running this cycle on the spi bus.
serial peripheral interface (spi) 816 datasheet 21.1.5 fdata0flash data 0 register (spi memory mapped co nfiguration registers) memory address: spibar + 10h attribute: r/w default value: 00000000h size: 32 bits 21.1.6 fdatanflash data [n] register (spi memory mapped co nfiguration registers) memory address: spibar + 14h attribute: r/w spibar + 18h spibar + 1ch spibar + 20h spibar + 24h spibar + 28h spibar + 2ch spibar + 30h spibar + 34h spibar + 38h spibar + 3ch spibar + 40h spibar + 44h spibar + 48h spibar + 4ch default value: 00000000h size: 32 bits bit description 31:0 flash data 0 (fd0) ? r/w. this field is shifted out as the spi data on the master-out slave-in data pin during the data portion of the spi cycle. this register also shifts in the data from th e master-in slave-out pin into this register during the data portion of the spi cycle. the data is always shifted starting with the least significant byte, msb to lsb, followed by the next least significant by te, msb to lsb, etc. specifically, the shift order on spi in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-?8-23-22-?16-31?24 bit 24 is the last bit shifted out/in. there are no alignment assumptions; byte 0 always represents the value specified by the cycle address. note that the data in this register may be modified by the hardware during any programmed spi transaction. direct memory reads do not modify the contents of this register. bit description 31:0 flash data n (fd[n]) ? r/w. similar definition as flash data 0. however, this register does not begin shifting until fd[n-1] has completely shifted in/out.
datasheet 817 serial peripheral interface (spi) 21.1.7 frapflash regions acce ss permissions register (spi memory mapped configuration registers) memory address: spibar + 50h attribute: ro, r/w default value: 00000202h size: 32 bits note: this register is only applicable when spi device is in descriptor mode. bit description 31:24 bios master write access grant (bmwag) ? r/w. each bit [31:29] corresponds to master[7:0]. bios can grant one or more masters write access to the bios region 1 overriding the permissions in the flash descriptor. master[1] is host processor/bios, master[2] is intel ? management engine, master[3] is host processor/gbe. master[0 ] and master[7:4] are reserved. the contents of this register are locked by the flockdn bit. 23:16 bios master read access grant (bmrag) r/w. each bit [28:16] corresponds to master[7:0]. bios can grant one or more ma sters read access to the bios region 1 overriding the read permissions in the flash descriptor. master[1] is host processor/bios, master[2] is intel ? management engine, master[3] is host processor/gbe. master[0 ] and master[7:4] are reserved. the contents of this register are locked by the flockdn bit 15:8 bios region write access (brwa) ro. each bit [15:8] corresponds to regions [7:0]. if the bit is set, this master can er ase and write that part icular region through register accesses. the contents of this register are that of the flash descri ptor. flash master 1 master region write access or a particular master has granted bios write permissions in their master write access grant register or the flash descriptor security override strap is set. 7:0 bios region read access (brra) ? ro. each bit [7:0] corresponds to regions [7:0]. if the bit is set, this master can re ad that particular re gion through register accesses. the contents of this register are that of the flash descri ptor.flash master 1.master region write access or a particular master has granted bios read permissions in their master read access grant regi ster or the flash descriptor security override strap is set.
serial peripheral interface (spi) 818 datasheet 21.1.8 freg0flash region 0 (f lash descriptor) register (spi memory mapped co nfiguration registers) memory address: spibar + 54h attribute: ro default value: 00000000h size: 32 bits note: this register is only applicable when spi device is in descriptor mode. 21.1.9 freg1flash region 1 (bios descriptor) register (spi memory mapped co nfiguration registers) memory address: spibar + 58h attribute: ro default value: 00000000h size: 32 bits note: this register is only applicable when spi device is in descriptor mode. bit description 31:29 reserved 28:16 region limit (rl) ro. this specifies address bits 24:12 for the region 0 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 0.region limit. 15:13 reserved 12:0 region base (rb) / flash descriptor base address region (fdbar) ? ro. this specifies address bits 24 :12 for the region 0 base the value in this register is load ed from the contents in the flash descriptor.flreg0.region base. bit description 31:29 reserved 28:16 region limit (rl) ro. this specifies address bits 24:12 for the region 1 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 1.region limit. 15:13 reserved 12:0 region base (rb) ? ro. this specifies address bits 24:12 for the region 1 base the value in this register is load ed from the contents in the flash descriptor.flreg1.region base.
datasheet 819 serial peripheral interface (spi) 21.1.10 freg2flash region 2 (intel ? me) register (spi memory mapped configuration registers) memory address: spibar + 5ch attribute: ro default value: 00000000h size: 32 bits note: this register is only applicable when spi device is in descriptor mode. 21.1.11 freg3flash regi on 3 (gbe) register (spi memory mapped configuration registers) memory address: spibar + 60h attribute: ro default value: 00000000h size: 32 bits note: this register is only applicable when spi device is in descriptor mode. bit description 31:29 reserved 28:16 region limit (rl) ro. this specifies address bits 24:12 for the region 2 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 2.region limit. 15:13 reserved 12:0 region base (rb) ? ro. this specifies address bits 24:12 for the region 2 base the value in this register is load ed from the contents in the flash descriptor.flreg2.region base bit description 31:29 reserved 28:16 region limit (rl) ro. this specifies address bits 24:12 for the region 3 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 3.region limit. 15:13 reserved 12:0 region base (rb) ? ro. this specifies address bits 24:12 for the region 3 base the value in this register is load ed from the contents in the flash descriptor.flreg3.region base
serial peripheral interface (spi) 820 datasheet 21.1.12 freg4flash region 4 (platform data) register (spi memory mapped co nfiguration registers) memory address: spibar + 64h attribute: ro default value: 00000000h size: 32 bits note: this register is only applicable when spi device is in descriptor mode. 21.1.13 pr0protected range 0 register (spi memory mapped co nfiguration registers) memory address: spibar + 74h attribute: r/w default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31:29 reserved 28:16 region limit (rl) ro. this specifies address bits 24:12 for the region 4 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 4.region limit. 15:13 reserved 12:0 region base (rb) ? ro. this specifies address bits 24:12 for the region 4 base the value in this register is load ed from the contents in the flash descriptor.flreg4.region base. bit description 31 write protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are va lid and that writes and erases directed to addresses between them (inclusive) must be bl ocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit r/w. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fiel ds are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base ? r/w. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range.
datasheet 821 serial peripheral interface (spi) 21.1.14 pr1protected range 1 register (spi memory mapped configuration registers) memory address: spibar + 78h attribute: r/w default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31 write protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are va lid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardwa re. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit r/w. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fields are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base ? r/w. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range.
serial peripheral interface (spi) 822 datasheet 21.1.15 pr2protected range 2 register (spi memory mapped co nfiguration registers) memory address: spibar + 7ch attribute: r/w default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31 write protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are va lid and that writes and erases directed to addresses between them (inclusive) must be bl ocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit r/w. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fiel ds are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base ? r/w. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range.
datasheet 823 serial peripheral interface (spi) 21.1.16 pr3protected range 3 register (spi memory mapped configuration registers) memory address: spibar + 80h attribute: r/w default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31 write protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are va lid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardwa re. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit r/w. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fields are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base ? r/w. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range.
serial peripheral interface (spi) 824 datasheet 21.1.17 pr4protected range 4 register (spi memory mapped co nfiguration registers) memory address: spibar + 84h attribute: r/w default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31 write protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are va lid and that writes and erases directed to a ddresses between them (inclusive) must be bl ocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit r/w. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be bl ocked by hardware. the base and li mit fields are ig nored when this bit is cleared. 14:13 reserved 12:0 protected range base ? r/w. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by th is protected range.
datasheet 825 serial peripheral interface (spi) 21.1.18 ssfssoftware sequencing flash status register (spi memory mapped configuration registers) memory address: spibar + 90h attribute: ro, r/wc default value: 00h size: 8 bits note: the software sequencing control and status registers are reserved if the hardware sequencing control and status registers are used. bit description 7:5 reserved 4 access error log (ael) ro. this bit reflects the value of the hardware sequencing status ael register. 3 flash cycle error (fcerr) r/wc. hardware sets this bit to 1 when a programmed access is blocked from running on the spi interface due to on e of the protection policies or when any of the programmed cycle register s is written while a programmed access is already in progress. this bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an intel ? me enabled system. 2 cycle done status ? r/wc. the pch sets this bit to 1 when the spi cycle completes (that is, scip bit is 0) after software sets the go bit. this bit remains asserted until cleared by software writing a 1 or hardware re set due to a global re set or host partition reset in an intel ? me enabled system. when this bit is set and the spi smi# enable bit is set, an internal signal is asserted to the smi# generation block. software must make sure this bit is cleared prior to enabling the spi smi# assertion for a new programmed access. 1 reserved 0 spi cycle in progress (scip) ? ro. hardware sets this bit when software sets the spi cycle go bit in the comman d register. this bit remains set until the cycle completes on the spi interface. hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. software must only program the next command when this bit is 0.
serial peripheral interface (spi) 826 datasheet 21.1.19 ssfcsoftware sequencing flash control register (spi memory mapped co nfiguration registers) memory address: spibar + 91h attribute: r/w default value: f80000h size: 24 bits bit description 23:19 reserved ? bios must set this field to ?11111?b 18:16 spi cycle frequency (scf) r/w. this register sets frequency to use for all spi software sequencing cycles (w rite, erase, fast read, read status, etc.) except for the read cycle which always run at 20 mhz. 000 = 20 mhz 001 = 33 mhz 100 = 50 mhz all other values reserved. this register is locked when the spi configuration lock-down bit is set. 15 spi smi# enable (sme) ? r/w. when set to 1, the spi asserts an smi# request whenever the cycle done status bit is 1. 14 data cycle (ds) ? r/w. when set to 1, there is data that corresponds to this transaction. when 0, no data is delivered for this cycle, and the dbc and data fields themselves are don?t cares. 13:8 data byte count (dbc) ? r/w. this field specifies the number of bytes to shift in or out during the data portion of the spi cycle. the valid settings (in decimal) are any value from 0 to 63. the number of byte s transferred is the value of this field plus 1. note that when this field is 00_0000b, then there is 1 byte to transfer and that 11_1111b means there are 64 bytes to transfer. 7 reserved 6:4 cycle opcode pointer (cop) ? r/w. this field selects one of the programmed opcodes in the opcode menu to be used as the spi command/opcode. in the case of an atomic cycle sequence, this determines the second command. 3 sequence prefix opcode pointer (spop) ? r/w. this field selects one of the two programmed prefix opcodes for use when performing an atomic cycle sequence. a value of 0 points to the opcode in the least significant byte of the prefix opcodes register. by making this prog rammable, the pch supports flash devices that have different opcodes for enabling writes to the data space versus status register. 2 atomic cycle sequence (acs) ? r/w. when set to 1 along with the scgo assertion, the pch will execute a sequen ce of commands on the spi interface without allowing the lan component to arbitrate and interleave cycles. the sequence is composed of: ? atomic sequence prefix command (8-bit opcode only) ? primary command specified below by so ftware (can include address and data) ? polling the flash status register (opcode 05h) until bit 0 becomes 0b. the spi cycle in progress bit remains se t and the cycle done status bit remains unset until the busy bit in the flash status register returns 0. 1 spi cycle go (scgo) ? r/ws. this bit always retu rns 0 on reads. however, a write to this register with a 1 in this bit starts the spi cycle defi ned by the other bits of this register. the ?spi cycle in progre ss? (scip) bit gets set by this action. hardware must ignore writes to this bi t while the cycle in progress bit is set. hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. this saves an additi onal memory write. 0 reserved
datasheet 827 serial peripheral interface (spi) 21.1.20 preopprefix opcode configuration register (spi memory mapped configuration registers) memory address: spibar + 94h attribute: r/w default value: 0000h size: 16 bits note: this register is not writable when the flash configuration lock-down bit (spibar + 04h:15) is set. 21.1.21 optypeopcode type configuration register (spi memory mapped configuration registers) memory address: spibar + 96h attribute: r/w default value: 0000h size: 16 bits entries in this register correspond to the entries in the opcode menu configuration register. note: the definition below only provides write protection for opcodes that have addresses associated with them. therefore, any erase or write opcodes that do not use an address should be avoided (for example, ?chip erase? and ?auto-address increment byte program?) note: this register is not writable when the spi configuration lock-down bit (spibar + 00h:15) is set. bit description 15:8 prefix opcode 1 ? r/w. software programs an spi opco de into this field that is permitted to run as the first comm and in an atomic cycle sequence. 7:0 prefix opcode 0 ? r/w. software programs an spi opco de into this field that is permitted to run as the first comm and in an atomic cycle sequence. bit description 15:14 opcode type 7 ? r/w. see the descriptio n for bits 1:0 13:12 opcode type 6 ? r/w. see the descriptio n for bits 1:0 11:10 opcode type 5 ? r/w. see the descriptio n for bits 1:0 9:8 opcode type 4 ? r/w. see the descriptio n for bits 1:0 7:6 opcode type 3 ? r/w. see the descriptio n for bits 1:0 5:4 opcode type 2 ? r/w. see the descriptio n for bits 1:0 3:2 opcode type 1 ? r/w. see the descriptio n for bits 1:0 1:0 opcode type 0 ? r/w. this field specifies informat ion about the corresponding opcode 0. this information allows the hardwa re to 1) know whether to use the address field and 2) provide bios and shared flash pr otection capabilities. the encoding of the two bits is: 00 = no address associated with this opcode; read cycle type 01 = no address associated with this opcode; write cycle type 10 = address required; read cycle type 11 = address required; write cycle type
serial peripheral interface (spi) 828 datasheet 21.1.22 opmenuopcode menu configuration register (spi memory mapped co nfiguration registers) memory address: spibar + 98h attribute: r/w default value: 0000000000000000h size: 64 bits eight entries are available in this register to give bios a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. this keeps the hardware flexible enough to operate with a wide variety of spi devices. note: it is recommended that bios avoid progra mming write enable op codes in this menu. malicious software could then perform writes and erases to the spi flash without using the atomic cycle mechanism. this could cause functional failures in a shared flash environment. write enable opcodes should on ly be programmed in the prefix opcodes. this register is not writable when the spi configuration lock-down bit (spibar + 00h:15) is set. bit description 63:56 allowable opcode 7 ? r/w. see the description for bits 7:0 55:48 allowable opcode 6 ? r/w. see the description for bits 7:0 47:40 allowable opcode 5 ? r/w. see the description for bits 7:0 39:32 allowable opcode 4 ? r/w. see the description for bits 7:0 31:24 allowable opcode 3 ? r/w. see the description for bits 7:0 23:16 allowable opcode 2 ? r/w. see the description for bits 7:0 15:8 allowable opcode 1 ? r/w. see the description for bits 7:0 7:0 allowable opcode 0 ? r/w. software programs an spi opcode into this field for use when initiating spi commands through the control register.
datasheet 829 serial peripheral interface (spi) 21.1.23 bbarbios base addres s configuration register (spi memory mapped configuration registers) memory address: spibar + a0h attribute: r/w, ro default value: 00000000h size: 32 bits eight entries are available in this register to give bios a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. this keeps the hardware flexible enough to operate with a wide variety of spi devices. 21.1.24 fdocflash descriptor ob servability control register (spi memory mapped configuration registers) memory address: spibar + b0h attribute: r/w default value: 00000000h size: 32 bits note: this register that can be used to observe the contents of the flash descriptor that is stored in the pch flash controller. this register is only applicable when spi device is in descriptor mode. bit description 31:24 reserved 23:8 bottom of system flash ? r/w. this field determines the bottom of the system bios. the pch will not run programmed co mmands nor memory reads whose address field is less than this value. this field corresponds to bits 23:8 of the 3-byte address; bits 7:0 are assumed to be 00h for this vector when co mparing to a potential spi address. note: the spi host controller prevents any programmed cycle using the address register with an address less than the value in this register. some flash devices specify that the read id command must have an address of 0000h or 0001h. if this command must be supported with these devices, it must be performed with the bios bar. 7:0 reserved bit description 31:15 reserved 14:12 flash descriptor section select (fdss) ? r/w. selects which section within the loaded flash descriptor to observe. 000 = flash signature and descriptor map 001 = component 010 = region 011 = master 111 = reserved 11:2 flash descriptor section index (fdsi) r/w. selects the dw offset within the flash descriptor section to observe. 1:0 reserved
serial peripheral interface (spi) 830 datasheet 21.1.25 fdodflash descriptor ob servability data register (spi memory mapped co nfiguration registers) memory address: spibar + b4h attribute: ro default value: 00000000h size: 32 bits note: this register that can be used to observe the contents of the flash descriptor that is stored in the pch flash controller. 21.1.26 afcadditional flash control register (spi memory mapped co nfiguration registers) memory address: spibar + c0h attribute: ro, r/w default value: 00000000h size: 32 bits. 21.1.27 lvscc host lower ve ndor specific component capabilities register (spi memory mapped co nfiguration registers) memory address: spibar + c4h attribute: ro, r/wl default value: 00000000h size: 32 bits note: all attributes described in lvscc must apply to all flash space below the fpba, even if it spans between two separate flash parts. th is register is only applicable when spi device is in descriptor mode. bit description 31:0 flash descriptor section data (fdsd) ro. returns the dw of data to observe as selected in the flash descriptor observability control. bit description 31:3 reserved 2:1 flash controller interface dy namic clock gating enable ? r/w. 0 = flash controller interface dynamic clock gating is disabled 1 = flash controller interface dy namic clock gating is enabled other configurations are reserved. 0 flash controller core dyna mic clock gating enable ? r/w. 0 = flash controller core dyna mic clock gating is disabled 1 = flash controller core dyna mic clock gating is enabled bit description 31:24 reserved 23 vendor component lock (lvcl) ? r/w. this register locks itself when set. 0 = the lock bit is not set 1 = the vendor component lock bit is set. note: this bit applies to both uvscc and lvscc registers. 22:16 reserved 15:8 lower erase opcode (leo) ? r/w. this register is pr ogrammed with the flash erase instruction opcode required by the vendor?s flash component. this register is locked by the vendor component lock (lvcl) bit.
datasheet 831 serial peripheral interface (spi) 7:5 reserved 4 write enable on write status (lwews) ? r/w. this register is locked by the vendor component lock (lvcl) bit. 0 = no automatic write of 00h will be ma de to the spi flash? s status register) 1 = a write of 00h to the spi flash?s status register will be sent on every write and erase to the spi flash. 06h 01h 00h is th e opcode sequence us ed to unlock the status register. notes: 1. this bit should not be set to 1 if there are non-volatile bits in the spi flash?s status register. this may lead to premature flash wear out. 2. this is not an atomic sequence. if th e spi component?s status register is non- volatile, then bios should issue an atomic software sequence cycle to unlock the flash part. 3. bit 3 and bit 4 should not be both set to 1. 3 lower write status required (lwsr) ? r/w. this register is locked by the vendor component lock (lvcl) bit. 0 = no automatic write of 00h will be ma de to the spi flash? s status register) 1 = a write of 00h to the spi flash?s status register will be sent on every write and erase to the spi flash. 50h 01h 00h is th e opcode sequence us ed to unlock the status register. notes: 1. this bit should not be set to 1 if there are non volatile bits in the spi flash?s status register. this may lead to premature flash wear out. 2. this is not an atomic sequence. if th e spi component?s status register is non- volatile, then bios should issue an atomic software sequence cycle to unlock the flash part. 3. bit 3 and bit 4 should not be both set to 1. 2 lower write granularity (lwg) r/w . this register is lo cked by the vendor component lock (lvcl) bit. 0 = 1 byte 1 = 64 byte notes: 1. if more than one flash component exists , this field must be set to the lowest common write granularity of th e different flash components. 2. if using 64 b write, bios must ensure that multiple byte writes do not occur over 256 b boundaries. this will lead to corru ption as the write will wrap around the page boundary on the spi flash part. this is a a feature page writable spi flash. 1:0 lower block/sector erase size (lbes) r/w. this field identifies the erasable sector size for all flash components. 00 = 256 byte 01 = 4 kb 10 = 8 kb 11 = 64 kb this register is locked by the vendor component lock (lvcl) bit. hardware takes no action base d on the value of this regi ster. the contents of this register are to be used only by software an d can be read in the hsfsts.berase register in both the bios and the gbe program registers if fla is less than fpba. bit description
serial peripheral interface (spi) 832 datasheet 21.1.28 uvscc host upper ve ndor specific component capabilities register (spi memory mapped co nfiguration registers) memory address: spibar + c8h attribute: ro, r/wl default value: 00000000h size: 32 bits note: all attributes described in uv scc must apply to all flash space equal to or above the fpba, even if it spans between two separate flash parts. this register is only applicable when spi device is in descriptor mode. note: to prevent this register from being modified you must use lvscc.vcl bit. bit description 31:16 reserved 15:8 upper erase opcode (ueo) ? r/w. this register is pr ogrammed with the flash erase instruction opcode required by the vendor?s flash component. this register is locked by the vendor component lock (uvcl) bit. 7:5 reserved 4 write enable on write status (uwews) ? r/w. this register is locked by the vendor component lock (uvcl) bit. 0 = no automatic write of 00h will be ma de to the spi flash? s status register) 1 = a write of 00h to the spi flash?s status register will be sent on every write and erase to the spi flash. 06h 01h 00h is the opcode sequence used to unlock the status register. notes: 1. this bit should not be set to 1 if there are non volatile bits in the spi flash?s status register. this may lead to premature flash wear out. 2. this is not an atomic se quence. if the spi component?s status register is non- volatile, then bios should issue an atomic software sequence cycle to unlock the flash part. 3. bit 3 and bit 4 should not be both set to 1. 3 upper write status required (uwsr) ? r/w. this register is locked by the vendor component lock (uvcl) bit. 0 = no automatic write of 00h will be ma de to the spi flash? s status register) 1 = a write of 00h to the spi flash?s status register will be sent on every write and erase to the spi flash. 50h 01h 00h is the opcode sequence used to unlock the status register. notes: 1. this bit should not be set to ?1? if ther e are non volatile bits in the spi flash?s status register. this may lead to premature flash wear out. 2. this is not an atomic se quence. if the spi component?s status register is non- volatile, then bios should issue an atomic software sequence cycle to unlock the flash part. 3. bit 3 and bit 4 should not be both set to 1.
datasheet 833 serial peripheral interface (spi) 21.1.29 fpb flash partit ion boundary register (spi memory mapped configuration registers) memory address: spibar + d0h attribute: ro default value: 00000000h size: 32 bits note: this register is only applicable when spi device is in descriptor mode. 2 upper write granularity (uwg) r/w. this register is locked by the vendor component lock (uvcl) bit. 0 = 1 byte 1 = 64 byte notes: 1. if more than one flash component exists , this field must be set to the lowest common write granularity of th e different flash components. 2. if using 64 b write, bios must ensure that multiple byte writes do not occur over 256 b boundaries. this will lead to corruption as the write will wrap around the page boundary on the spi flash part. this is a a feature page writable spi flash. 1:0 upper block/sector erase size (ubes) r/w. this field identifies the erasable sector size for all flash components. valid bit settings: 00 = 256 byte 01 = 4 kb 10 = 8 kb 11 = 64 kb this register is locked by the vendor component lock (uvcl) bit. hardware takes no action base d on the value of this regi ster. the contents of this register are to be used only by softwa re and can be read in the hsfsts.berase register in both the bios and the gbe program registers if fla is greater or equal to fpba. bit description bit description 31:13 reserved 12:0 flash partition bound ary address (fpba) ? ro. this register reflects the value of flash descriptor component fpba field.
serial peripheral interface (spi) 834 datasheet 21.1.30 srdl soft rese t data lock register (spi memory mapped co nfiguration registers) memory address: spibar + f0h attribute: r/wl default value: 00000000h size: 32 bits 21.1.31 srdc soft rese t data control register (spi memory mapped co nfiguration registers) memory address: spibar + f4h attribute: r/wl default value: 00000000h size: 32 bits 21.1.32 srd soft reset data register (spi memory mapped co nfiguration registers) memory address: spibar + f8h attribute: r/wl default value: 00000000h size: 32 bits bit description 31:1 reserved 0 set_stap lock (ssl) ? r/wl. 0 = the srdl (this register), srdc (spibar+f4h), and srd (spibar+f4h) registers are writeable. 1 = the srdl (this register), srdc (spibar+f4h), and srd (spibar+f4h) registers are locked. note: that this bit is reset to ?0? on cf9h resets. bit description 31:1 reserved 0 soft reset data select (srds) ? r/wl. 0 = the set_strap data sends the de fault processor configuration data. 1 = the set_strap message bits come from th e set_strap msg data register. notes: 1. this bit is reset by the rsmrst# or when the resume well loses power. 2. this bit is locked by the ssl bit (spibar+f0h:bit 0). bit description 31:14 reserved 13:0 set_stap data (ssd) ? r/wl. notes: 1. these bits are reset by the rsmrst#, or when the resume well loses power. 2. these bits are locked by the ssl bit (spibar+f0h:bit 0).
datasheet 835 serial peripheral interface (spi) 21.2 flash descriptor records the following sections describe the data st ructure of the flash descriptor on the spi device. these are not registers within the pch. 21.3 oem section memory address: f00h default value: size: 256 bytes 256 bytes are reserved at the top of the flash descriptor for use by the oem. the information stored by the oem can only be written during the manufacturing process as the flash descriptor read/write permission s must be set to read only when the computer leaves the manufacturing floor. the pch flash controller does not read this information. ffh is suggested to reduce programming time. 21.4 gbe spi flash program registers the gbe flash registers are memory-mapped with a base address mbarb found in the gbe lan register chapter device 25: function 0: offset 14h. the individual registers are then accessible at mbarb + offset as indicated in the following table. these memory mapped registers must be accessed in byte, word, or dword quantities. note: these register are only applicable when spi flash is used in descriptor mode. table 21-2. gigabit lan spi flas h program register address map (gbe lan memory mapped configurat ion registers) (sheet 1 of 2) mbarb + offset mnemonic register name default attribute 00h?03h glfpr gigabit lan flash primary region 00000000h ro 04h?05h hsfs hardware sequencing flash status 0000h ro, r/wc, r/w 06h?07h hsfc hardware sequencing flash control 0000h r/w, r/ws 08h?0bh faddr flash address 00000000h r/w 0ch?0fh ? reserved 00000000h 10h?13h fdata0 flash data 0 00000000h r/w 14h?4fh ? reserved 00000000h 50h?53h frap flash region access permissions 00000000h ro, r/w 54h?57h freg0 flash region 0 00000000h ro 58h?5bh freg1 flash region 1 00000000h ro 5ch?5f freg2 flash region 2 00000000h ro 60h?63h freg3 flash region 3 00000000h ro 64h?73h ? reserved for future flash regions 74h?77h pr0 flash protected range 0 00000000h r/w 78h?7bh pr1 flash protected range 1 00000000h r/w 7ch?8fh ? reserved 90h ssfs software sequencing flash status 00h ro, r/wc
serial peripheral interface (spi) 836 datasheet 21.4.1 glfpr Cgigabit lan flas h primary region register (gbe lan memory mapped configuration registers) memory address: mbarb + 00h attribute: ro default value: 00000000h size: 32 bits 21.4.2 hsfshardware sequenci ng flash status register (gbe lan memory mapped configuration registers) memory address: mbarb + 04h attribute: ro, r/wc, r/w default value: 0000h size: 16 bits 91h?93h ssfc software sequencing flash control 000000h r/w 94h?95h preop prefix opcode configuration 0000h r/w 96h?97h optype opcode type configuration 0000h r/w 98h?9fh opmenu opcode menu configuration 0000000000 000000h r/w a0h?dfh ? reserved table 21-2. gigabit lan spi flas h program register address map (gbe lan memory mapped configurat ion registers) (sheet 2 of 2) mbarb + offset mnemonic register name default attribute bit description 31:29 reserved 28:16 gbe flash primary region limit (prl) ro. this specifies address bits 24:12 for the primary region limit. the value in this register loaded from the contents in the flash descriptor.flreg3.region limit 15:13 reserved 12:0 gbe flash primary region base (prb) ? ro. this specifies address bits 24:12 for the primary region base the value in this register is load ed from the contents in the flash descriptor.flreg3.region base bit description 15 flash configuration lock-down (flockdn) ? r/w. when set to 1, those flash program registers that are locked down by this flockdn bit cannot be written. once set to 1, this bit can only be cleared by a hardware reset due to a global reset or host partition reset in an intel ? me enabled system. 14 flash descriptor valid (fdv) ro. this bit is set to a 1 if the flash controller read the correct flash de scriptor signature. if the flash descriptor valid bit is not 1, software ca nnot use the hardware sequencing registers, but must use the software sequencing registers. any attempt to use the hardware sequencing registers will result in the fcerr bit being set.
datasheet 837 serial peripheral interface (spi) 13 flash descriptor override pin strap status (fdopss) ro. this bit indicates the condition of the flash descriptor security override / intel me debug mode pin-strap. 0 = the flash descriptor secu rity override / intel me de bug mode strap is set using external pull-up on hda_sdo 1 = no override 12:6 reserved 5 spi cycle in progress (scip) ro. hardware sets this bi t when software sets the flash cycle go (fgo) bit in the hardware se quencing flash control register. this bit remains set until the cycle completes on the spi interface. hardware automatically sets and clears this bit so that software can dete rmine when read data is valid and/or when it is safe to begin programming the next command. software must only program the next command when this bit is 0. 4:3 block/sector eras e size (berase) ? ro. this field identifies the erasable sector size for all flash components. 00 = 256 byte 01 = 4 k byte 10 = 8 k byte 11 = 64 k byte if the flash linear address is less than fpba then this field refl ects the value in the lvscc.lbes register. if the flash linear address is greater or equa l to fpba then this field reflects the value in the uvscc.ubes register. 2 access error log (ael) ? r/w/c. hardware sets this bit to a 1 when an attempt was made to access the bios region using the di rect access method or an access to the bios program registers that violated the security restrictions. this bit is simply a log of an access security violatio n. this bit is cleared by software writing a 1. 1 flash cycle error (fcerr) ? r/w/c. hardware sets this bit to 1 when an program register access is blocked to the flash due to one of the protection policies or when any of the programmed cycle registers is wr itten while a programmed access is already in progress. this bit remains asserted until cleared by so ftware writing a 1 or until hardware reset occurs due to a global re set or host partitio n reset in an intel ? me enabled system. software must clear this bit before settin g the flash cycle go bit in this register. 0 flash cycle done (fdone) ? r/w/c. the pch sets this bit to 1 when the spi cycle completes after software previously set the fgo bit. this bit re mains asserted until cleared by software writing a 1 or hardware re set due to a global re set or host partition reset in an intel ? me enabled system. when this bit is set and the spi smi# enable bit is set, an internal signal is asserted to the smi# generation block. software must make sure this bit is cleared prio r to enabling the spi smi# as sertion for a new programmed access. bit description
serial peripheral interface (spi) 838 datasheet 21.4.3 hsfchardware sequencing flash control register (gbe lan memory mapped configuration registers) memory address: mbarb + 06h attribute: r/w, r/ws default value: 0000h size: 16 bits 21.4.4 faddrflash address register (gbe lan memory mapped configuration registers) memory address: mbarb + 08h attribute: r/w default value: 00000000h size: 32 bits bit description 15:10 reserved 9:8 flash data byte count (fdbc) r/w. this field specifies the number of bytes to shift in or out during the data portion of the spi cycle. the contents of this register are 0s based with 0b representi ng 1 byte and 11b representing 4 bytes. the number of bytes transferred is the value of this field plus 1. this field is ignored for the block erase command. 7:3 reserved 2:1 flash cycle (fcycle) ? r/w. this field defines the flash spi cycle type generated to the flash when the fgo bit is set as defined below: 00 = read (1 up to 4 bytes by setting fdbc) 01 = reserved 10 = write (1 up to 4 bytes by setting fdbc) 11 = block erase 0 flash cycle go (fgo) ? r/w/s. a write to this register with a 1 in this bit initiates a request to the flash spi arbiter to start a cy cle. this register is cleared by hardware when the cycle is granted by the spi arbiter to run the cycle on the spi bus. when the cycle is complete, the fdone bit is set. software is forbidden to write to any regist er in the hsflctl register between the fgo bit getting set and the fdone bi t being cleared. any attempt to violate this rule will be ignored by hardware. hardware allows other bits in this register to be progra mmed for the same transaction when writing this bit to 1. this saves an additional memory write. this bit always returns 0 on reads. bit description 31:25 reserved 24:0 flash linear address (fla) r/w. the fla is the starting byte linear address of a spi read or write cycle or an address with in a block for the bloc k erase command. the flash linear address must fall within a region for which bi os has access permissions.
datasheet 839 serial peripheral interface (spi) 21.4.5 fdata0flash data 0 register (gbe lan memory mapped configuration registers) memory address: mbarb + 10h attribute: r/w default value: 00000000h size: 32 bits 21.4.6 frapflash regions acce ss permissions register (gbe lan memory mapped configuration registers) memory address: mbarb + 50h attribute: ro, r/w default value: 00000808h size: 32 bits bit description 31:0 flash data 0 (fd0) ? r/w. this field is shifted out as the spi data on the master-out slave-in data pin during the data portion of the spi cycle. this register also shifts in the data from th e master-in slave-out pin into this register during the data portion of the spi cycle. the data is always shifted starting with the least significant byte, msb to lsb, followed by the next least significant byte, msb to lsb, etc. specifically, the shift order on spi in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-?8-23-22-?16-31?24 bit 24 is the last bit shifted out/in. there are no alignment assumptions; byte 0 always represents the value specif ied by the cycle address. note that the data in this register may be modified by the hardware during any programmed spi transaction. direct memory re ads do not modify the contents of this register. bit description 31:28 reserved 27:25 gbe master write access grant (gmwag) ? r/w. each bit 27:25 corresponds to master[3:1]. gbe can grant one or more ma sters write access to the gbe region 3 overriding the permissions in the flash descriptor. master[1] is host processor/bios, master[2] is intel ? management engine, master[3] is host processor/gbe. the contents of this register are locked by the flockdn bit. 24:20 reserved 19:17 gbe master read access grant (gmrag) r/w. each bit 19:17 corresponds to master[3:1]. gbe can grant one or more ma sters read access to the gbe region 3 overriding the read permissions in the flash descriptor. master[1] is host processor/bios, master[2] is intel ? management engine, master[3] is gbe. the contents of this register are locked by the flockdn bit 16:12 reserved 11:8 gbe region write access (grwa) ro. each bit 11:8 corresponds to regions 3:0. if the bit is set, this master can erase and write that particular re gion through register accesses. the contents of this register are that of the flash descri ptor. flash master 3.master region write access or a particular master has granted gbe write permissions in their master write access grant register or the fl ash descriptor security override strap is set. 7:4 reserved 3:0 gbe region read access (grra) ? ro. each bit 3:0 corresponds to regions 3:0. if the bit is set, this master can read that particular region thro ugh register accesses. the contents of this register are that of the flash descri ptor. flash master 3.master region write access or a particular master has grante d gbe read permissions in their master read access grant register.
serial peripheral interface (spi) 840 datasheet 21.4.7 freg0flash region 0 (f lash descriptor) register (gbe lan memory mapped configuration registers) memory address: mbarb + 54h attribute: ro default value: 00000000h size: 32 bits 21.4.8 freg1flash region 1 (bios descriptor) register (gbe lan memory mapped configuration registers) memory address: mbarb + 58h attribute: ro default value: 00000000h size: 32 bits 21.4.9 freg2flash region 2 (intel ? me) register (gbe lan memory mapped configuration registers) memory address: mbarb + 5ch attribute: ro default value: 00000000h size: 32 bits bit description 31:29 reserved 28:16 region limit (rl) ro. this specifies address bits 24:12 for the region 0 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 0.region limit. 15:13 reserved 12:0 region base (rb) ? ro. this specifies address bits 24:12 for the region 0 base the value in this register is load ed from the contents in the flash descriptor.flreg0.region base. bit description 31:29 reserved 28:16 region limit (rl) ro. this specifies address bits 24:12 for the region 1 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 1.region limit. 15:13 reserved 12:0 region base (rb) ? ro. this specifies address bits 24:12 for the region 1 base the value in this register is load ed from the contents in the flash descriptor.flreg1.region base. bit description 31:29 reserved 28:16 region limit (rl) ro. this specifies address bits 24:12 for the region 2 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 2.region limit. 15:13 reserved 12:0 region base (rb) ? ro. this specifies address bits 24:12 for the region 2 base the value in this register is load ed from the contents in the flash descriptor.flreg2.region base.
datasheet 841 serial peripheral interface (spi) 21.4.10 freg3flash regi on 3 (gbe) register (gbe lan memory mapped configuration registers) memory address: mbarb + 60h attribute: ro default value: 00000000h size: 32 bits 21.4.11 pr0protected range 0 register (gbe lan memory mapped configuration registers) memory address: mbarb + 74h attribute: r/w default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31:29 reserved 28:16 region limit (rl) ro. this specifies address bits 24:12 for the region 3 limit. the value in this register is load ed from the contents in the flash descriptor.flreg 3.region limit. 15:13 reserved 12:0 region base (rb) ? ro. this specifies address bits 24:12 for the region 3 base the value in this register is load ed from the contents in the flash descriptor.flreg3.region base. bit description 31 write protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are va lid and that writes and erases directed to addresses between them (inclusive) must be blocked by hardwa re. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit r/w. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fields are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base ? r/w. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range.
serial peripheral interface (spi) 842 datasheet 21.4.12 pr1protected range 1 register (gbe lan memory mapped configuration registers) memory address: mbarb + 78h attribute: r/w default value: 00000000h size: 32 bits note: this register can not be written when the flockdn bit is set to 1. bit description 31 write protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are va lid and that writes and erases directed to addresses between them (inclusive) must be bl ocked by hardware. the base and limit fields are ignored when this bit is cleared. 30:29 reserved 28:16 protected range limit r/w. this field corresponds to fla address bits 24:12 and specifies the upper limit of th e protected range. address bi ts 11:0 are assumed to be fffh for the limit comparison. any address gr eater than the value programmed in this field is unaffected by this protected range. 15 read protection enable ? r/w. when set, this bit indicates that the base and limit fields in this register are valid and that read directed to a ddresses between them (inclusive) must be blocked by hardware. th e base and limit fiel ds are ignored when this bit is cleared. 14:13 reserved 12:0 protected range base ? r/w. this field corresponds to fla address bits 24:12 and specifies the lower base of the protected ra nge. address bits 11:0 are assumed to be 000h for the base comparison. any address less than the value programmed in this field is unaffected by this protected range.
datasheet 843 serial peripheral interface (spi) 21.4.13 ssfssoftware sequencing flash status register (gbe lan memory mapped configuration registers) memory address: mbarb + 90h attribute: ro, r/wc default value: 00h size: 8 bits note: the software sequencing control and status registers are reserved if the hardware sequencing control and status registers are used. bit description 7:5 reserved 4 access error log (ael) ro. this bit reflects the valu e of the hardware sequencing status ael register. 3 flash cycle error (fcerr) r/wc. hardware sets this bit to 1 when a programmed access is blocked from running on the spi inte rface due to one of the protection policies or when any of the programme d cycle registers is written while a programmed access is already in progress. this bit remains asserted until cleared by software writing a 1 or hardware reset due to a global reset or host partition reset in an intel ? me enabled system. 2 cycle done status ? r/wc. the pch sets this bit to 1 when the spi cycle completes (that is, scip bit is 0) after software sets the go bit. this bit remains asserted until cleared by software writing a 1 or hardware re set due to a global re set or host partition reset in an intel ? me enabled system. when this bit is set and the spi smi# enable bit is set, an internal signal is asserted to the smi# generation block. software must make sure this bit is cleared prio r to enabling the spi smi# as sertion for a new programmed access. 1 reserved 0 spi cycle in progress (scip) ? ro. hardware sets this bit when software sets the spi cycle go bit in the command register. this bit remains set until the cycle completes on the spi interface. hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. software must only program the next command when this bit is 0.
serial peripheral interface (spi) 844 datasheet 21.4.14 ssfcsoftware sequencing flash control register (gbe lan memory mapped configuration registers) memory address: mbarb + 91h attribute: r/w default value: 000000h size: 24 bits bit description 23:19 reserved 18:16 spi cycle frequency (scf) r/w. this register sets frequency to use for all spi software sequencing cycles (w rite, erase, fast read, read status, etc.) except for the read cycle which always run at 20 mhz. 000 = 20 mhz 001 = 33 mhz all other values = reserved. this register is locked when the sp i configuration lock-down bit is set. 15 reserved 14 data cycle (ds) ? r/w. when set to 1, there is data that corresponds to this transaction. when 0, no data is delivered for this cycle, and the dbc and data fields themselves are don?t cares. 13:8 data byte count (dbc) ? r/w. this field specifies the numbe r of bytes to shift in or out during the data portion of the spi cycl e. the valid settings (in decimal) are any value from 0 to 3. the number of bytes transf erred is the value of this field plus 1. note that when this field is 00b, then there is 1 byte to transfer and that 11b means there are 4 bytes to transfer. 7 reserved 6:4 cycle opcode pointer (cop) ? r/w. this field selects one of the programmed opcodes in the opcode menu to be used as the spi command/opcode. in the case of an atomic cycle sequence, this determines the second command. 3 sequence prefix opcode pointer (spop) ? r/w. this field selects one of the two programmed prefix opcodes for use when performing an atomic cycle sequence. a value of 0 points to the opcode in the least significant byte of the prefix opcodes register. by making this programmable, the pch supports flash devices that have different opcodes for enabling writes to the data space versus status register. 2 atomic cycle sequence (acs) ? r/w. when set to 1 along with the scgo assertion, the pch will execute a sequence of commands on the spi interface without allowing the lan component to arbitrate and interleave cycles. the sequence is composed of: ? atomic sequence prefix command (8-bit opcode only) ? primary command specified below by so ftware (can include address and data) ? polling the flash status register (opcode 05h) until bit 0 becomes 0b. the spi cycle in progress bit remains set an d the cycle done status bit remains unset until the busy bit in the flas h status register returns 0. 1 spi cycle go (scgo) ? r/ws. this bit always returns 0 on reads. however, a write to this register with a ?1? in th is bit starts the spi cycle defi ned by the other bits of this register. the ?spi cycle in progress? (scip) bit gets set by this action. hardware must ignore writes to this bit while the cycle in progress bit is set. hardware allows other bits in this register to be progra mmed for the same transaction when writing this bit to 1. this saves an additional memory write. 0 reserved
datasheet 845 serial peripheral interface (spi) 21.4.15 preopprefix opcode configuration register (gbe lan memory mapped configuration registers) memory address: mbarb + 94h attribute: r/w default value: 0000h size: 16 bits note: this register is not writable when the spi configuration lock-down bit (mbarb + 00h:15) is set. 21.4.16 optypeopcode type configuration register (gbe lan memory mapped configuration registers) memory address: mbarb + 96h attribute: r/w default value: 0000h size: 16 bits entries in this register correspond to the entries in the opcode menu configuration register. note: the definition below only provides write protection for opcodes that have addresses associated with them. therefore, any erase or write opcodes that do not use an address should be avoided (for example, ?chip erase? and ?auto-address increment byte program?). note: this register is not writable when the spi configuration lock-down bit (mbarb + 00h:15) is set. bit description 15:8 prefix opcode 1 ? r/w. software programs an spi opco de into this field that is permitted to run as the first comm and in an atomic cycle sequence. 7:0 prefix opcode 0 ? r/w. software programs an spi opco de into this field that is permitted to run as the first comm and in an atomic cycle sequence. bit description 15:14 opcode type 7 ? r/w. see the descriptio n for bits 1:0 13:12 opcode type 6 ? r/w. see the descriptio n for bits 1:0 11:10 opcode type 5 ? r/w. see the descriptio n for bits 1:0 9:8 opcode type 4 ? r/w. see the descriptio n for bits 1:0 7:6 opcode type 3 ? r/w. see the descriptio n for bits 1:0 5:4 opcode type 2 ? r/w. see the descriptio n for bits 1:0 3:2 opcode type 1 ? r/w. see the descriptio n for bits 1:0 1:0 opcode type 0 ? r/w. this field specifies informat ion about the corresponding opcode 0. this information allows the hardwa re to 1) know whether to use the address field and 2) provide bios and shared flash pr otection capabilities. the encoding of the two bits is: 00 = no address associated with this opcode; read cycle type 01 = no address associated with this opcode; write cycle type 10 = address required; read cycle type 11 = address required; write cycle type
serial peripheral interface (spi) 846 datasheet 21.4.17 opmenuopcode menu configuration register (gbe lan memory mapped configuration registers) memory address: mbarb + 98h attribute: r/w default value: 0000000000000000h size: 64 bits eight entries are available in this register to give gbe a sufficient set of commands for communicating with the flash device, while also restricting what malicious software can do. this keeps the hardware flexible enough to operate with a wide variety of spi devices. note: it is recommended that gbe avoid programm ing write enable opcodes in this menu. malicious software could then perform writes and erases to the spi flash without using the atomic cycle mechanism. this could cause functional failures in a shared flash environment. write enable opcodes should on ly be programmed in the prefix opcodes. this register is not writable when the spi configuration lock-down bit (mbarb + 00h:15) is set. bit description 63:56 allowable opcode 7 ? r/w. see the description for bits 7:0 55:48 allowable opcode 6 ? r/w. see the description for bits 7:0 47:40 allowable opcode 5 ? r/w. see the description for bits 7:0 39:32 allowable opcode 4 ? r/w. see the description for bits 7:0 31:24 allowable opcode 3 ? r/w. see the description for bits 7:0 23:16 allowable opcode 2 ? r/w. see the description for bits 7:0 15:8 allowable opcode 1 ? r/w. see the description for bits 7:0 7:0 allowable opcode 0 ? r/w. software programs an spi opcode into this field for use when initiating spi commands through the control register.
datasheet 847 thermal sensor registers (d31:f6) 22 thermal sensor registers (d31:f6) 22.1 pci bus configuration registers table 22-1. thermal sensor register address map offset mnemonic register name default attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification 1c24h ro 04h?05h cmd command register 0000h r/w, ro 06h?07h sts device status 0010h r/wc, ro 08h rid revision id 00h ro 09h pi programming interface 00h ro 0ah scc sub class code 80h ro 0bh bcc base class code 11h ro 0ch cls cache line size 00h ro 0dh lt latency timer 00h ro 0eh htype header type 00h ro 10h?13h tbar thermal base address 00000004h r/w, ro 14h?17h tbarh thermal base address high dword 00000000h ro 2ch?2dh svid subsystem vendor identifier 0000h r/wo 2eh?2fh sid subsystem identifier 0000h r/wo 34h cap_ptr capabilities pointer 50h ro 3ch intln interrupt line 00h r/w 3dh intpn interrupt pin see description ro 40h?43h tbarb bios assigned therma l base address 00000004h r/w, ro 44h?47h tbarbh bios assigned thermal base high dword 00000000h r/w 50h?51h pid pci power management capability id 0001h ro 52h?53h pc power management capabilities 0023h ro 54h?57h pcs power management control and status 0008h r/w, ro
thermal sensor registers (d31:f6) 848 datasheet 22.1.1 vidvendor iden tification register offset address: 00h ? 01h attribute: ro default value: 8086h size: 16 bit lockable: no power well: core 22.1.2 diddevice iden tification register offset address: 02h ? 03h attribute: ro default value: 1c24h size: 16 bits 22.1.3 cmdcommand register address offset: 04h ? 05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:0 vendor id ? ro. this is a 16-bit value as signed to intel. intel vid = 8086h bit description 15:0 device id (did) ? ro. indicates the device number assigned by the sig. bit description 15:11 reserved 10 interrupt disable (id) ? r/w. enables the device to assert an intx#. 0 = when cleared, the intx# signal may be asserted. 1 = when set, the thermal logic?s intx# signal will be deasserted. 9 fbe (fast back to back enable) ? ro. hardwired to 0. 8 sen (serr enable) ? ro. hardwired to 0. 7 wcc (wait cycle control) ? ro. hardwired to 0. 6 per (parity error response) ? ro. hardwired to 0. 5 vps (vga palette snoop) ? ro. hardwired to 0. 4 mwi (memory write and invalidate enable) ? ro. hardwired to 0. 3 sce (special cycle enab le) ? ro. hardwired to 0. 2 bme (bus master enable) ? r/w. 0 = function disabled as bus master. 1 = function enabled as bus master. 1 memory space enable (mse) ? r/w. 0 = disable 1 = enable. enables memory space ac cesses to the thermal registers. 0 ios (i/o space) ? ro. the thermal logic does not implement io space; therefore, this bit is hardwired to 0.
datasheet 849 thermal sensor registers (d31:f6) 22.1.4 stsstatus register address offset: 06h ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits 22.1.5 ridrevision identification register address offset: 08h attribute: ro default value: 00h size: 8 bits 22.1.6 pi programmin g interface register address offset: 09h attribute: ro default value: 00h size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. this bit is set whenever a parity error is seen on the internal interface for this function, regardless of the setting of bit 6 in the command register. software cl ears this bit by writing a 1 to this bit location. 14 serr# status (serrs) ? ro. hardwired to 0. 13 received master abort (rma) ? ro. hardwired to 0. 12 received target abort (rta) ? ro. hardwired to 0. 11 signaled target-abort (sta) ? ro. hardwired to 0. 10:9 devsel# timing status (devt) ? ro. hardwired to 0. 8 master data parity error (mdpe) ? ro. hardwired to 0. 7 fast back to back capable (fbc) ? ro. hardwired to 0. 6reserved 5 66 mhz capable (c66) ? ro. hardwired to 0. 4 capabilities list exists (clist) ? ro. indicates that the controller contains a capabilities pointer list. the fi rst item is pointed to by l ooking at configuration offset 34h. 3 interrupt status (is) ? ro. reflects the state of the intx# signal at the input of the enable/disable circuit. this bit is a 1 when the intx# is asserted. this bit is a 0 after the interrupt is cleared (indep endent of the state of the interrupt disabl e bit in the command register). 2:0 reserved bit description 7:0 revision id (rid) ? ro. indicates the device sp ecific revision identifier. bit description 7:0 programming interface (pi) ? ro. the pch thermal logic has no standard programming interface.
thermal sensor registers (d31:f6) 850 datasheet 22.1.7 sccsub class code register address offset: 0ah attribute: ro default value: 80h size: 8 bits 22.1.8 bccbase class code register address offset: 0bh attribute: ro default value: 11h size: 8 bits 22.1.9 clscache line size register address offset: 0ch attribute: ro default value: 00h size: 8 bits 22.1.10 ltlatency timer register address offset: 0dh attribute: ro default value: 00h size: 8 bits 22.1.11 htypeheader type register address offset: 0eh attribute: ro default value: 00h size: 8 bits bit description 7:0 sub class code (scc) ? ro. value assigned to the pch thermal logic. bit description 7:0 base class code (bcc) ? ro. value assigned to the pch thermal logic. bit description 7:0 cache line size (cls) ? ro. does not apply to pci bus target-only devices. bit description 7:0 latency timer (lt) ? ro. does not apply to pci bus target-only devices. bit description 7 multi-function device (mfd) ? ro. this bit is 0 becaus e a multi-function device only needs to be marked as such in functi on 0, and the thermal registers are not in function 0. 6:0 header type (htype) ? ro. implements type 0 configuration header.
datasheet 851 thermal sensor registers (d31:f6) 22.1.12 tbarthermal base register address offset: 10h ? 13h attribute: r/w, ro default value: 00000004h size: 32 bits this bar creates 4k bytes of memory spac e to signify the base address of thermal memory mapped configuration registers. this memory space is active when the command (cmd) register memory space enable (mse) bit is set and either tbar[31:12] or tbarh are programmed to a non-zero address. this bar is owned by the operating system, and allows the os to locate the thermal registers in system memory space. 22.1.13 tbarhthermal base high dword register address offset: 14h ? 17h attribute: r/w, ro default value: 00000000h size: 32 bits this bar extension holds the high 32 bits of the 64 bit tbar. in conjunction with tbar, it creates 4 kb of memory space to sign ify the base address of thermal memory mapped configuration registers. 22.1.14 svidsubsystem vendor id register address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits this register should be implemented for any function that could be instantiated more than once in a given system. the svid regi ster, in combination with the subsystem id register, enables the operating environment to distinguish one subsystem from the other(s). software (bios) will write the value to this register. after that, the value can be read, but writes to the register will have no effect. the write to this register should be combined with the write to the sid to create one 32-bit write. this register is not affected by d3 hot to d0 reset. bit description 31:12 thermal base address (tba) ? r/w. this field provides the base a ddress for the thermal logic memory mapped configuration registers. 4 kb byte s are requested by hardwiring bits 11:4 to 0s. 11:4 reserved 3 prefetchable (pref) ? ro. indicates that this bar is not pre-fetchable. 2:1 address range (addrng) ? ro. indicates that this bar can be located anywhere in 64 bit address space. 0 space type (sptyp) ? ro. indicates that this bar is located in memory space. bit description 31:0 thermal base address high (tbah) ? r/w. tbar bits 61:32. bit description 15:0 svid (svid) ? r/wo. these r/wo bits have no pch functionality.
thermal sensor registers (d31:f6) 852 datasheet 22.1.15 sidsubsystem id register address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits this register should be implemented for any function that could be instantiated more than once in a given system. the sid register, in combination with the subsystem vendor id register make it possible for the operating environment to distinguish one subsystem from the other(s). software (bios) will write the value to this register. after that, the value can be read, but writes to the register will have no ef fect. the write to this register should be combined with the write to the svid to create one 32-bit write. this register is not affected by d3 hot to d0 reset. 22.1.16 cap_ptrcapabili ties pointer register address offset: 34h attribute: ro default value: 50h size: 8 bits 22.1.17 intlninterrupt line register address offset: 3ch attribute: r/w default value: 00h size: 8 bits 22.1.18 intpninterrupt pin register address offset: 3dh attribute: ro default value: see description size: 8 bits bit description 15:0 sid (said) ? r/wo. these r/wo bits have no pch functionality. bit description 7:0 capability pointer (cp) ? ro. indicates that the first capa bility pointer offset is offset 50h (power management capability). bit description 7:0 interrupt line ? r/w. pch hardware does not use th is field directly. it is used to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:4 reserved 3:0 interrupt pin ? ro. this reflects the value of the device 31 interrupt pin bits 27:24 (ttip) in chipset configuration space.
datasheet 853 thermal sensor registers (d31:f6) 22.1.19 tbarbbios assigned th ermal base address register address offset: 40h ? 43h attribute: r/w,ro default value: 00000004h size: 32 bits this bar creates 4 kb of memory space to signify the base address of thermal memory mapped configuration registers. this memory space is active when tbarb.sptypen is asserted. this bar is owned by the bios, an d allows the bios to locate the thermal registers in system memory space. if both tbar and tbarb are programmed, then the os and bios each have their own independ ent ?view? of the thermal registers, and must use the tsiu register to denote thermal registers ownership/availability. 22.1.20 tbarbhbios assigned thermal base high dword register address offset: 44h ? 47h attribute: r/w default value: 00000000h size: 32 bits this bar extension holds the high 32 bits of the 64 bit tbarb. 22.1.21 pidpci power manageme nt capability id register address offset: 50h ? 51h attribute: ro default value: 0001h size: 16 bits bit description 31:12 thermal base address (tba) ? r/w. this field provides th e base address for the thermal logic memory mapped configuration registers. 4k b byte s are requested by hardwiring bits 11:4 to 0s. 11:4 reserved 3 prefetchable (pref) ? ro. indicates that this bar is not pre-fetchable. 2:1 address range (addrng) ? ro. indicates that this bar can be located anywhere in 64 bit address space. 0 space type enable (sptypen) ? r/w. 0 = disable. 1 = enable. when set to 1b by software, enables the decode of this memory bar. bit description 31:0 thermal base address high (tbah) ? r/w. tbar bits 61:32. bit description 15:8 next capability (next) ? ro. indicates that this is the last capability structure in the list. 7:0 cap id (cap) ? ro. indicates that this pointer is a pci power management capability
thermal sensor registers (d31:f6) 854 datasheet 22.1.22 pcpower management capabilities register address offset: 52h ? 53h attribute: ro default value: 0023h size: 16 bits 22.1.23 pcspower management control and status register address offset: 54h ? 57h attribute: r/w, ro default value: 0008h size: 32 bits bit description 15:11 pme_support ? ro. indicates pme# is not supported 10 d2_support ? ro. the d2 state is not supported. 9 d1_support ? ro. the d1 state is not supported. 8:6 aux_current ? ro. pme# from d3cold state is not su pported, therefore this field is 000b. 5 device specific initialization (dsi) ? ro. indicates that device-specific initialization is required. 4 reserved 3 pme clock (pmec) ? ro. does not apply. hardwired to 0. 2:0 version (vs) ? ro. indicates support for revision 1.2 of the pci power management specification. bit description 31:24 data ? ro. does not apply. hardwired to 0s. 23 bus power/clock control enable (bpcce) ? ro. hardwired to 0. 22 b2/b3 support (b23) ? ro. does not apply. hardwired to 0. 21:16 reserved 15 pme status (pmes) ? ro. this bit is always 0, since this pci function does not generate pme#. 14:9 reserved 8 pme enable (pmee) ? ro. this bit is always zero, since this pci function does not generate pme#. 7:4 reserved 3 no soft reset ? ro. when set 1, this bit indicates that devices transitioning from d3 hot to d0 because of powerstate commands do not perform an internal reset. configuration context is preser ved. upon transition from d3 hot to d0 initialized state, no additional operating system intervention is required to preserve configuration context beyond writing the powerstate bits. 2 reserved 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the thermal controller and to set a new power state. the values are: 00 = d0 state 11 = d3 hot state if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. when in the d3 hot states, the thermal controller?s configuration space is available, but the i/o and memory spaces are not. additionally, inte rrupts are blocked. when software changes this value from the d3 hot state to the d0 st ate, no internal warm (soft) reset is generated.
datasheet 855 thermal sensor registers (d31:f6) 22.2 thermal memory mapped configuration registers (thermal sensor C d31:f26) the base memory for these thermal memory mapped configuration registers is specified in the tbarb (d31:f6:offset 40h). the individual registers are then accessible at tbarb + offset. table 22-2. thermal memory mapped co nfiguration register address map offset mnemonic register name default attribute 00h tsiu thermal sensor in use 00h ro,r/w 01h tse thermal sensor enable 00h r/w 02h tss thermal sensor status 00h r/w 03h tstr thermal sensor thermometer read ffh ro 04h tsttp thermal sensor temperature trip point 00000000h r/w 08h tsco thermal sensor catastrophic lock down 00h r/w 0ch tses thermal sensor error status 00h r/wc 0dh tsgpen thermal sensor general purpose event enable 00h r/w 0eh tspc thermal sensor policy control 00h r/w, ro 14h pta pch temperature adjust 0000h r/w 1ah trc thermal reporting control 0000h r/w 3fh ae alert enable 00h r/w 56h ptl processor temperature limit 0000h r/w 60h ptv processor temperature value 0000h ro 6ch tt thermal throttling 00000000h r/w 70h phl pch hot level 00h r/w 82h tspien thermal sensor pci interrupt event enable 00h r/w 83h tslock thermal sensor register lock control 00h r/w ach tc2 thermal compares 2 00000000h ro b0h dtv dimm temperature values 00000000h ro d8h itv internal temperature values 00000000h ro
thermal sensor registers (d31:f6) 856 datasheet 22.2.1 tsiuthermal sens or in use register offset address: tbarb+00h attribute: ro, r/w default value: 00h size: 8 bit 22.2.2 tsethermal sens or enable register offset address: tbarb+01h attribute: r/w default value: 00h size: 8 bit 22.2.3 tssthermal sens or status register offset address: tbarb+02h attribute: ro default value: 00h size: 8 bit bit description 7:1 reserved 0 thermal sensor in use (tsiu) ? r/w. this is a sw semaphore bit. after a core well reset, a read to this bit returns a 0. after the first read, subsequent reads will return a 1. a write of a 1 to this bit will reset the next read value to 0. writing a 0 to this bit has no effect. software can poll this bit until it reads a 0, and will then own the usage of the thermal sensor. this bit has no other effect on the hardware, and is only used as a semaphore among various independent so ftware threads that may need to use the thermal sensor. software that reads this register but does not intend to claim exclusive access of the thermal sensor must write a 1 to this bit if it reads a 0, in order to allow other software threads to claim it. bit description 7:0 thermal sensor enable (tse) ? r/w. bios programs this register to enable the thermal sensor. bit description 7 catastrophic trip indicator (cti) ? ro. 0 = the temperature is below the catastrophic setting. 1 = the temperature is above the catastrophic setting. 6 hot trip indicator (hti) ? ro. 0 = the temperature is below the hot setting. 1 = the temperature is above the hot setting. 5 auxiliary trip indicator (ati) ? ro. 0 = the temperature is below the auxiliary setting. 1 = the temperature is above the auxiliary setting. 4 reserved 3 auxiliary2 trip indicator (ati) ? ro. 0 = the temperature is below the auxiliary2 setting. 1 = the temperature is above the auxiliary2 setting. 2:0 reserved
datasheet 857 thermal sensor registers (d31:f6) 22.2.4 tstrthermal sensor thermometer read register offset address: tbarb+03h attribute: ro default value: ffh size: 8 bit this register generally provides the ca librated temperature from the thermometer circuit when the thermometer is enabled. 22.2.5 tsttpthermal sensor temperature trip point register offset address: tbarb+04h attribute: r/w default value: 00000000h size: 32 bit bit description 7:0 thermometer reading (tr) ? ro. value corresponds to the thermal sensor temperature. this register has a straight bi nary encoding that ranges from 0 to ffh. the value in this field is valid only if the tr value is between 00h and 7fh. bit description 31:24 auxiliary2 trip point setting (a2tps) ? r/w. these bits set the auxiliary2 trip point. these bits are lockable usin g programming the policy-lock down bit (bit 7) of tspc register. these bits may only be prog rammed from 0h to 7fh. setting bit 31 is illegal. 23:16 auxiliary trip point setting (atps) ? r/w. these bits set the auxiliary trip point. these bits are lockable using tslock bit 2 these bits may only be prog rammed from 0h to 7fh. setting bit 23 is illegal. 15:8 hot trip point setting (htps) ? r/w. these bits set the hot trip point. these bits are lockable usin g programming the policy-lock down bit (bit 7) of tspc register. these bits may only be prog rammed from 0h to 7fh. setting bit 15 is illegal. note: bios should program to 3ah for setting hot trip point to 108 c. 7:0 catastrophic trip point setting (ctps) ? r/w. these bits set the catastrophic trip point. these bits are lockable using tsco.bit 7. these bits may only be pr ogrammed from 0h to 7fh. setting bit 7 is illegal. note: bios should program to 2bh for setting catastrophic trip point to 120 c.
thermal sensor registers (d31:f6) 858 datasheet 22.2.6 tscothermal sensor catastrophic lock-down register offset address: tbarb+08h attribute: r/w default value: 00h size: 8 bit bit description 7 lock bit for catastrophic (lbc) ? r/w. 0 = catastrophic programmin g interface is unlocked 1 = locks the catastrophic programmin g interface including tsttp.bits[7:0]. this bit may only be set to a 0 by a host pa rtitioned reset (note that cf9 warm reset is a host partitioned rese t). writing a 0 to this bit has no effect. tsco.[7] is unlocked by default and can be locked through bios. 6:0 reserved
datasheet 859 thermal sensor registers (d31:f6) 22.2.7 tsesthermal sensor error status register offset address: tbarb+0ch attribute: r/wc default value: 00h size: 8 bit bit description 7 auxiliary2 high-to-lowevent ? r/wc. 0 = no trip occurs. 1 = indicates that an auxiliary2 thermal se nsor trip event occurre d based on a higher to lower temperature transition through the trip point. software must write a 1 to clear this status bit. 6 catastrophic high-to-lowevent ? r/wc. 0 = no trip occurs. 1 = indicates that a catastrophic thermal sensor trip event occurred based on a higher to lower temperature transition through the trip point. 1 = software must write a 1 to clear this status bit. 5 hot high-to-lowevent ? r/wc. 0 = no trip occurs. 1 = indicates that a hot thermal sensor tr ip event occurred based on a higher to lower temperature transition through the trip point. software must write a 1 to clear this status bit. 4 auxiliary high-to-lowevent ? r/wc. 0 = no trip occurs. 1 = indicates that an auxili ary thermal sensor trip event occurred based on a higher to lower temperature transition through the trip point. software must write a 1 to clear this status bit. 3 auxiliary2 low-to-high event ? r/wc. 0 = no trip occurs. 1 = indicates that an auxili ary2 thermal sensor trip ev ent occurred based on a lower to higher temperature transition through the trip point. software must write a 1 to clear this status bit. 2 catastrophic low-to-high event ? r/wc. 0 = no trip occurs. 1 = indicates that a catastrophic thermal se nsor trip event occurred based on a lower to higher temperature transition through the trip point. software must write a 1 to clear this status bit. 1 hot low-to-high event ? r/wc. 0 = no trip occurs. 1 = indicates that a hot thermal sensor trip event occurred based on a lower to higher temperature transition through the trip point. software must write a 1 to clear this status bit. 0 auxiliary low-to-high event ? r/wc. 0 = no trip occurs. 1 = indicates that an auxiliar y thermal sensor trip event oc curred based on a lower to higher temperature transition through the trip point. software must write a 1 to clear this status bit.
thermal sensor registers (d31:f6) 860 datasheet 22.2.8 tsgpentherma l sensor general purpose event enable register offset address: tbarb+0dh attribute: r/w default value: 00h size: 8 bit this register controls the conditions that result in general purpose events to be signalled from thermal sensor trip events. bit description 7 auxiliary2 high-to-low enable ? r/w. 0 = corresponding status bit does no t result in general purpose event. 1 = general purpose event is signaled when the corresponding status bit is set in the thermal error status register. 6 catastrophic high-to-low enable ? r/w. 0 = corresponding status bit does no t result in general purpose event. 1 = general purpose event is signaled when the corresponding status bit is set in the thermal error status register. 5 hot high-to-low enable ? r/w. 0 = corresponding status bit does no t result in general purpose event. 1 = general purpose event is signaled when the corresponding status bit is set in the thermal error status register. 4 auxiliary high-to-low enable ? r/w. 0 = corresponding status bit does no t result in general purpose event. 1 = general purpose event is signaled when the corresponding status bit is set in the thermal error status register. 3 auxiliary2 low-to-high enable ? r/w. 0 = corresponding status bit does no t result in general purpose event. 1 = general purpose event is signaled when the corresponding status bit is set in the thermal error status register. 2 catastrophic low-to-high enable ? r/w. 0 = corresponding status bit does no t result in general purpose event. 1 = general purpose event is signaled when the corresponding status bit is set in the thermal error status register. 1 hot low-to-high enable ? r/w. 0 = corresponding status bit does no t result in general purpose event. 1 = general purpose event is signaled when the corresponding status bit is set in the thermal error status register. 0 auxiliary low-to-high enable ? r/w. 0 = corresponding status bit does no t result in general purpose event. 1 = general purpose event is signaled when the corresponding status bit is set in the thermal error status register.
datasheet 861 thermal sensor registers (d31:f6) 22.2.9 tspcthermal sensor policy control register offset address: tbarb+0eh attribute: r/w, ro default value: 00h size: 8 bit bit description 7 policy lock-down bit ? r/w. 0 = this register can be programmed and modified. 1 = prevents writes to this register and tsttp.bits [31:16] (offset 04h). note: tsco.bit 7 (offset 08h) and tslock.bit2 (o ffset 83h) must also be 1 when this bit is set to 1. this bit is reset to 0 by a host partitioned reset (note th at cf9 warm reset is a host partitioned reset). writing a 0 to this bit has no effect. 6 catastrophic power-down enable ? r/w. when set to 1, the power management logic unconditionally transitions to the s5 state when a catastrophic temperature is detected by the sensor. note: bios should set this bit to 1 to enable catastrophic power-down. 5:4 reserved 3 smi enable on auxiliar y2 thermal sensor trip ? r/w. 0 = disables smi# assertion for au xiliary2 thermal sensor events. 1 = enables smi# assertions on auxiliary2 thermal sensor events for either low-to- high or high-to-low events. (both edges are enabled by this bit.) 2 smi enable on catastrophic thermal sensor trip ? r/w. 0 = disables smi# assertion for cata strophic thermal sensor events. 1 = enables smi# assertions on catastrophic thermal sensor events for either low-to- high or high-to-low events. (both edges are enabled by this bit.) 1 smi enable on hot thermal sensor trip ? r/w. 0 = disables smi# assertion for hot thermal sensor events. 1 = enables smi# assertions on hot thermal sensor events for either low-to-high or high-to-low events. (both edge s are enabled by this bit.) 0 smi enable on auxiliar y thermal sensor trip ? r/w. 0 = disables smi# assertion for au xiliary thermal sensor events. 1 = enables smi# assertions on auxiliary thermal sensor events for either low-to- high or high-to-low events. (both edges are enabled by this bit.)
thermal sensor registers (d31:f6) 862 datasheet 22.2.10 ptapch temperat ure adjust register offset address: tbarb+14h attribute: r/w default value: 0000h size: 16 bit 22.2.11 trcthermal repo rting control register offset address: tbarb+1ah attribute: r/w default value: 0000h size: 16 bit bit description 15:8 pch slope ? r/w. this field contains the pch sl ope for calculating pch temperature. the bits are locked by ae.bit7 (offset 3fh). note: when thermal reporting is enabled, bi os must write deh into this field. 7:0 offset ? r/w. this field contains the pch offs et for calculating pch temperature. the bits are locked by ae.bit7 (offset 3fh). note: when thermal reporting is enabled, bi os must write 87h into this field. bit description 15:13 reserved 12 thermal data reporting enable ? r/w. 0 = disable 1 = enable 11:6 reserved 5 pch temperature read enable ? r/w 0 = disables reads of the pch temperature. 1 = enables reads of the pch temperature. 4 reserved 3 dimm4 temperature read enable ? r/w 0 = disables reads of dimm4 temperature. 1 = enables reads of dimm4 temperature. 2 dimm3 temperature read enable ? r/w 0 = disables reads of dimm3 temperature. 1 = enables reads of dimm3 temperature. 1 dimm2 temperature read enable ? r/w 0 = disables reads of dimm2 temperature. 1 = enables reads of dimm2 temperature. 0 dimm1 temperature read enable ? r/w 0 = disables reads of dimm1 temperature. 1 = enables reads of dimm1 temperature.
datasheet 863 thermal sensor registers (d31:f6) 22.2.12 aealert enable register offset address: tbarb+3fh attribute: r/w default value: 00h size: 8 bit 22.2.13 ptlprocessor temperature limit register offset address: tbarb+56h attribute: r/w default value: 0000h size: 16 bit 22.2.14 ptv processor te mperature value register offset address: tbarb+60h attribute: ro default value: 0000h size: 16 bit bit description 7 lock enable ? r/w. 0 = lock disabled. 1 = lock enabled. this will lock this register (including this bit) this bit is reset by a host partitioned re set. note that cf9 wa rm reset is a host partitioned reset. 6:5 reserved 4 pch alert enable ? r/w. when this bit is set, it will assert the pch?s temp_alert# pin if the pch temperature is outside the temperature limits. this bit is lockable by bit 7 in this register. 3 dimm alert enable ? r/w. when this bit is set, it will assert the pch?s temp_alert# pin if dimm1-4 temperature is outside of the temperature limits. note that the actual dimms that are read an d used for the alert are enabled in the trc register (offset 1ah). this bit is lockable by bit 7 in this register. note: same upper and lower limits for tri ggering temp_alert# are used for all enabled dimms in the system. 2:0 reserved bit description 15:0 processor temperature limit ? r/w. these bits are programmed by bios. bit description 15:8 reserved 7:0 processor temperature value ? ro. these bits contain the processor package temperature
thermal sensor registers (d31:f6) 864 datasheet 22.2.15 ttthermal throttling register offset address: tbarb+6ch attribute: r/w default value: 00000000h size: 32 bit bios must program this field to 05161b20h. 22.2.16 phlpch hot level register offset address: tbarb+70h attribute: r/w default value: 00h size: 8 bit bit description 31:27 reserved 26 thermal throttle lock bit r/w. when set to ?1?, the thermal throttle (tt) register is locked and remains locked until the next platform reset. 25 reserved 24 thermal throttling enable r/w. when set to ?1?, pch thermal throttling is enabled. at reset, bios must set the t-st ate trip points defi ned by bits [23:0], followed by a separate write to enable this feature. if software wishes to change the trip point values, this bit must be cleared before the values in [23:0] are changed. when the new values have been entered, this bit must be set to re-enable the feature. 23:16 t3 trip point temperature r/w. when the temperature reading of thermal sensor thermometer read (tstr) is less th an or equal to this temperature, the system is in t3 state. (not e that the tstr reading of 00h is the hottest temperature and 7fh is the lowest temperature.) 15:8 t2 trip point temperature r/w. when the temperature reading of thermal sensor thermometer read (tstr) is less th an or equal to this temperature, the system is in t2 state. (not e that the tstr reading of 00h is the hottest temperature and 7fh is the lowest temperature.) 7:0 t1 trip point temperature r/w. when the temperature reading of thermal sensor thermometer read (tstr) is less than this temperature, the system is in t1 state. if tstr is greater than this, the system is in t0 state where no thermal throttling occurs. (note that the tstr reading of 00h is the hottest temperature and 7fh is the lowest temperature.) bit description 7:0 pch hot level (phl) ? r/w. when temperature reading in thermal sensor thermometer read (tstr) is less than phl programmed here, this will assert pchhot# (active low). (note that tstr reading of 00h is the hottest temperature and 7fh is the lowest temperature.) default state for this register is phl di sabled (00h). for ut ilizing the pchhot# functionality, a soft strap has to be conf igured and bios programs this phl value. please refer to the spi flash programming guide application note and intel me fw collaterals for information on enabling pchhot#.
datasheet 865 thermal sensor registers (d31:f6) 22.2.17 tspienthermal sensor pci interrupt enable register offset address: tbarb+82h attribute: r/w default value: 00h size: 8 bit this register controls the conditions that re sult in pci interrupts to be signalled from thermal sensor trip events. software (device driver) needs to ensure that it can support pci interrupts, even though bios may enable pci interrupt capability through this register. bit description 7 auxiliary2 high-to-low enable ? r/w. 0 = corresponding status bit does not result in pci interrupt. 1 = pci interrupt is signaled when the corresponding status bit is set in the thermal error status register. 6 catastrophic high-to-low enable ? r/w. 0 = corresponding status bit does not result in pci interrupt. 1 = pci interrupt is signaled when the corresponding status bit is set in the thermal error status register. 5 hot high-to-low enable ? r/w. 0 = corresponding status bit does not result in pci interrupt. 1 = pci interrupt is signaled when the corresponding status bit is set in the thermal error status register. 4 auxiliary high-to-low enable ? r/w. 0 = corresponding status bit does not result in pci interrupt. 1 = pci interrupt is signaled when the corresponding status bit is set in the thermal error status register. 3 auxiliary2 low-to-high enable ? r/w. 0 = corresponding status bit does not result in pci interrupt. 1 = pci interrupt is signaled when the corresponding status bit is set in the thermal error status register. 2 catastrophic low-to-high enable ? r/w. 0 = corresponding status bit does not result in pci interrupt. 1 = pci interrupt is signaled when the corresponding status bit is set in the thermal error status register. 1 hot low-to-high enable ? r/w. 0 = corresponding status bit does not result in pci interrupt. 1 = pci interrupt is signaled when the corresponding status bit is set in the thermal error status register. 0 auxiliary low-to-high enable ? r/w. 0 = corresponding status bit does not result in pci interrupt. 1 = pci interrupt is signaled when the corresponding status bit is set in the thermal error status register.
thermal sensor registers (d31:f6) 866 datasheet 22.2.18 tslockthermal sensor re gister lock control register offset address: tbarb+83h attribute: r/w default value: 00h size: 8 bit 22.2.19 tc2thermal compares 2 register offset address: tbarb+ach attribute: ro default value: 00000000h size: 32 bit bits [31:16] of this register are set when an external controller (such as ec) does the write dimm temp limits command. refer to section 5.21.3 for more information. bits [15:0] of this register are set when an external controller (such as ec) does the write pch temp limits command. refer to section 5.21.3 for more information. bit description 7:3 reserved 2 lock control ? r/w. this bit can only be set to a 0 by a host-partitioned reset. writing a 0 to this bit has no effect. note: cf9 warm reset is a ho st-partitioned reset. 1:0 reserved bit description 31:24 dimm thermal compare upper limit ro. this is the upper limit used to compare against the dimm?s temperature. if the dimm?s temperature is greater than this value, then the pch?s temp_ale rt# signal is asserted if enabled. 23:16 dimm thermal compar e lower limit ro. this is the lower limit used to compare against the dimm?s temperature. if the dimm?s temperature is lower than this value, then the pch?s temp_ale rt# signal is asserted if enabled. 15:8 pch thermal compare upper limit ro. this is the upper limit used to compare against the pch temperature. if the pch temperature is greater than this value, then the pch?s temp_alert# signal is asserted if enabled. 7:0 pch thermal compare lower limit ro. this is the lower limit used to compare against the pch temperature. if the pch temperature is lower than this value, then the pch?s temp_alert# signal is asserted if enabled.
datasheet 867 thermal sensor registers (d31:f6) 22.2.20 dtvdimm temper ature values register offset address: tbarb+b0h attribute: ro default value: 00000000h size: 32 bit 22.2.21 itvinternal temp erature values register offset address: tbarb+d8h attribute: ro default value: 00000000h size: 32 bit bit description 31:24 dimm3 temperature ? ro. the bits contain dimm3 te mperature data in absolute degrees celsius. these bits are data byte 8 provided to the external controller when it does a read over smlink1. refer to section 5.21.3 for more details 23:16 dimm2 temperature ? ro. the bits contain dimm2 te mperature data in absolute degrees celsius. these bits are data byte 7 provided to the external controller when it does a read over smlink1. refer to section 5.21.3 for more details 15:8 dimm1 temperature ? ro. the bits contain dimm1 te mperature data in absolute degrees celsius. these bits are data byte 6 provided to the external controller when it does a read over smlink1. refer to section 5.21.3 for more details 7:0 dimm0 temperature ? ro. the bits contain dimm0 te mperature data in absolute degrees celsius. these bits are data byte 5 provided to the external controller when it does a read over smlink1. refer to section 5.21.3 for more details bit description 31:24 reserved 23:16 sequence number ? ro. provides a sequence number which can be used by the host to detect if the me fw has hung. the value will roll over to 00h from ffh. the count is updated at approximately 200 ms. ho st sw can check this value and if it is not incriminated over a second or so, software should assume that the me fw is hung. note: if the me is reset, then this value will not change during the reset. after the reset is done, which may take up to 30 seconds, the me may be on again and this value will start incrementing, indicating that the thermal values are valid again. these bits are data byte 9 provided to the external controller when it does a read over smlink1. refer to section 5.21.3 for more details 15:8 reserved 7:0 pch temperature ? ro. the bits contain pch temper ature data in ab solute degrees celsius. these bits are data byte 1 provided to the external controller when it does a read over smlink1. refer to section 5.21.3 for more details
thermal sensor registers (d31:f6) 868 datasheet
datasheet 869 intel? management engine subsystem registers (d22:f[3:0]) 23 intel ? management engine subsystem registers (d22:f[3:0]) 23.1 first intel ? management engine interface (intel ? mei) configuration registers (intel ? mei 1 d22:f0) 23.1.1 pci configuration registers (intel ? mei 1d22:f0) table 23-1. intel ? mei 1 configuration registers address map (intel ? mei 1d22:f0) (sheet 1 of 2) offset mnemonic register name default attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h ro 08h rid revision identification see register description ro 09h?0bh cc class code 0c8000h ro 0eh htype header type 00h ro 10h?17h mei0_mbar mei0 mmio base address 000000000 0000004h r/w, ro 2ch?2dh svid subsystem vendor id 0000h r/wo 2eh?2fh sid subsystem id 0000h r/wo 34h capp capabilities list pointer 50h ro 3ch?3dh intr interrupt information 0400h r/w, ro 40h?43h hfs host firmware status 00000000h ro 44h?47h me_uma management engine uma register 00000000h ro 48h?4bh gmes general intel me status 00000000h ro 4ch?4fh h_gs host general status 00000000h ro 50h?51h pid pci power management capability id 6001h ro 52h?53h pc pci power manage ment capabilities c803h ro 54h?55h pmcs pci power management control and status 0008h r/wc, r/w, ro 8ch?8dh mid message signaled interrupt identifiers 0005h ro 8eh?8fh mc message signaled interrupt message control 0080h r/w, ro
intel? management engine subsystem registers (d22:f[3:0]) 870 datasheet 23.1.1.1 vidvendor identification register (intel ? mei 1d22:f0) address offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 23.1.1.2 diddevice identification register (intel ? mei 1d22:f0) address offset: 02h?03h attribute: ro default value: see bit description size: 16 bits 90h?93h ma message signaled interrupt message address 00000000h r/w, ro 94h?97h mua message signaled interrupt upper address 00000000h r/w 98h?99h md message signaled interrupt message data 0000h r/w a0h hidm intel mei interrupt delivery mode 00h r/w bch?bfh heres intel mei extended register status 40000000h ro c0h?dfh her[1:8] intel mei extended register dw[1:8] 00000000h ro table 23-1. intel ? mei 1 configuration registers address map (intel ? mei 1d22:f0) (sheet 2 of 2) offset mnemonic register name default attribute bit description 15:0 vendor id (vid) ? ro. this is a 16-bit value assigned to intel. bit description 15:0 device id (did) ? ro. this is a 16-bit value assigned to the intel management engine interface co ntroller. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the did register.
datasheet 871 intel? management engine subsystem registers (d22:f[3:0]) 23.1.1.3 pcicmdpci command register (intel ? mei 1d22:f0) address offset: 04h?05h attribute: r/w, ro default value: 0000h size: 16 bits 23.1.1.4 pcistspci status register (intel ? mei 1d22:f0) address offset: 06h ? 07h attribute: ro default value: 0010h size: 16 bits bit description 15:11 reserved 10 interrupt disable (id) ? r/w. disables this device from generating pci line based interrupts. this bit does not have any effect on msi operation. 9:3 reserved 2 bus master enable (bme) ? r/w. controls the intel mei host controller's abil ity to act as a system memory master for data transfers. when this bit is cleared, intel me bus master activity stops and any active dma engines return to an idle condit ion. this bit is made visible to firmware through the h_pci_csr register, and changes to this bit may be configured by the h_pci_csr register to generate an intel me msi. when this bit is 0, intel mei is blocked from generating msi to the host processor. note: this bit does not block intel mei accesses to intel me uma; that is, writes or reads to the host and intel me circular buffers through the read window and write window registers still cause intel me backbone transactions to intel me uma. 1 memory space enable (mse) ? r/w. controls access to the intel me's memory mapped register space. 0 = disable. memory cycles within the rang e specified by the memory base and limit registers are master aborted. 1 = enable. allows memory cycles within th e range specified by the memory base and limit registers accepted. 0 reserved bit description 15:5 reserved 4 capabilities list (cl) ? ro. indicates the pres ence of a capabilities list, hardwired to 1. 3 interrupt status (is) ? ro. indicates the interrupt status of the device. 0 = interrupt is deasserted. 1 = interrupt is asserted. 2:0 reserved
intel? management engine subsystem registers (d22:f[3:0]) 872 datasheet 23.1.1.5 ridrevision identification register (intel ? mei 1d22:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 23.1.1.6 ccclass code register (intel ? mei 1d22:f0) address offset: 09h ? 0bh attribute: ro default value: 078000h size: 24 bits 23.1.1.7 htypeheader type register (intel ? mei 1d22:f0) address offset: 0eh attribute: ro default value: 80h size: 8 bits 23.1.1.8 mei0_mbarmei0 mmi o base address register (intel ? mei 1d22:f0) address offset: 10h ? 17h attribute: r/w, ro default value: 0000000000000004h size: 64 bits this register allocates space for the mei0 memory mapped registers. bit description 7:0 revision id ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit description 23:16 base class code (bcc) ? ro. indicates the base class code of the intel mei device. 15:8 sub class code (scc) ? ro. indicates the sub class code of the intel mei device. 7:0 programming interface (pi) ? ro. indicates the programmi ng interface of the intel mei device. bit description 7 multi-function device (mfd) ? ro. indicates the intel mei host controller is part of a multifunction device. 6:0 header layout (hl) ? ro. indicates that the intel mei uses a target device layout. bit description 63:4 base address (ba) r/w . software programs this fiel d with the base address of this region. 3 prefetchable memory (pm) ? ro. indicates that this range is not pre-fetchable. 2:1 type (tp) ? ro. set to 10b to indicate that this range can be mapped anywhere in 64-bit address space. 0 resource type indicator (rte) ? ro. indicates a reques t for register memory space.
datasheet 873 intel? management engine subsystem registers (d22:f[3:0]) 23.1.1.9 svidsubsystem vendor id register (intel ? mei 1d22:f0) address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits 23.1.1.10 sidsubsystem id register (intel ? mei 1d22:f0) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits 23.1.1.11 cappcapabilities list pointer register (intel ? mei 1d22:f0) address offset: 34h attribute: ro default value: 50h size: 8 bits 23.1.1.12 intrinterrupt information register (intel ? mei 1d22:f0) address offset: 3ch?3dh attribute: r/w, ro default value: 0400h size: 16 bits bit description 15:0 subsystem vendor id (ssvid) ? r/wo. indicates the sub-system vendor identifier. this field should be programmed by bios during boot-up. once written, this register becomes read on ly. this field can only be cleared by pltrst#. note: register must be written as a word writ e or as a dword write with sid register. bit description 15:0 subsystem id (ssid) ? r/wo. indicates the sub-system identifier. this field should be programmed by bios during boot-up. on ce written, this register becomes read only. this field can only be cleared by pltrst#. note: register must be writte n as a word write or as a dword write with svid register. bit description 7:0 capabilities pointer (ptr) ? ro. indicates that the pointer for the first entry in the capabilities list is at 50h in configuration space. bit description 15:8 interrupt pin (ipin) ? ro. this indicates the interrupt pin the intel mei host controller uses. a value of 1h/2h/3h/4h indica tes that this function implements legacy interrupt on inta/intb/intc/intd, respectively. 7:0 interrupt line (iline) ? r/w. software written value to indicate which interrupt line (vector) the interrupt is conn ected to. no hardware action is taken on this register.
intel? management engine subsystem registers (d22:f[3:0]) 874 datasheet 23.1.1.13 hfshost firmware status register (intel ? mei 1d22:f0) address offset: 40h?43h attribute: ro default value: 00000000h size: 32 bits 23.1.1.14 me_umaintel ? management engine uma register (intel ? mei 1d22:f0) address offset: 44h?47h attribute: ro default value: 80000000h size: 32 bits bit description 31:0 host firmware status (hfs) ? ro. this register field is used by firmware to reflect the operating environment to the host. bit description 31 reserved ? ro. hardwired to 1. can be used by host software to di scover that this register is valid. 30:7 reserved 16 intel me uma size valid ro. this bit indicates that fw has written to the musz field. 15:6 reserved 5:0 intel me uma size (musz) ro. this field reflect intel me firmware?s desired size of intel me uma memory region. this field is se t by intel me firmware prior to core power bring up allowing bios to initialize memory. 000000b = 0 mb, no memory allocated to intel me uma 000001b = 1 mb 000010b = 2 mb 000100b = 4 mb 001000b = 8 mb 010000b = 16 mb 100000b = 32 mb
datasheet 875 intel? management engine subsystem registers (d22:f[3:0]) 23.1.1.15 gmesgeneral intel ? me status register (intel ? mei 1d22:f0) address offset: 48h?4bh attribute: ro default value: 00000000h size: 32 bits 23.1.1.16 h_gshost general status register (intel ? mei 1d22:f0) address offset: 4ch?4fh attribute: ro default value: 00000000h size: 32 bits 23.1.1.17 pidpci power manage ment capability id register (intel ? mei 1d22:f0) address offset: 50h?51h attribute: ro default value: 6001h size: 16 bits 23.1.1.18 pcpci power manage ment capabilities register (intel ? mei 1d22:f0) address offset: 52h ? 53h attribute: ro default value: c803h size: 16 bits bit description 31:0 general intel me status (me_gs) ? ro. this field is populated by intel me. bit description 31:0 host general status(h_gs) ? ro. general status of host, this field is not used by hardware bit description 15:8 next capabili ty (next) ? ro. value of 60h indicates the location of the next pointer. 7:0 capability id (cid) ? ro. indicates the linked list item is a pci power management register. bit description 15:11 pme_support (psup) ? ro. this five-bit field indicates the power states in which the function may assert pme#. in tel mei can assert pme# from any d-state except d1 or d2 which are not supported by intel mei. 10:9 reserved 8:6 aux_current (ac) ? ro. reports the maximum suspen d well current required when in the d3 cold state. value of 00b is reported. 5 device specific initialization (dsi) ? ro. indicates whet her device-specific initialization is required. 4 reserved 3 pme clock (pmec) ? ro. indicates that pci clock is not required to generate pme#. 2:0 version (vs) ? ro. hardwired to 011b to indicate support for revision 1.2 of the pci power management specification .
intel? management engine subsystem registers (d22:f[3:0]) 876 datasheet 23.1.1.19 pmcspci power management control and status register (intel ? mei 1d22:f0) address offset: 54h ? 55h attribute: r/wc, r/w, ro default value: 0008h size: 16 bits 23.1.1.20 midmessage signaled interrupt identifiers register (intel ? mei 1d22:f0) address offset: 8ch-8dh attribute: ro default value: 0005h size: 16 bits bit description 15 pme status (pmes) ? r/wc. bit is set by intel me firm ware. host software clears bit by writing ?1? to bit. this bit is reset when cl_rst1# asserted. 14:9 reserved 8 pme enable (pmee) ? r/w. this bit is read/write and is under the control of host sw. it does not directly have an effect on pme events. however, this bit is shadowed so intel me fw can monitor it. intel me fw will not cause the pmes bit to transition to 1 while the pmee bit is 0, indicating that host sw had disabled pme. this bit is reset wh en pltrst# asserted. 7:4 reserved 3 no_soft_reset (nsr) ? ro. this bit indicates that when the intel mei host controller is transitioning from d3 hot to d0 due to a power state command, it does not perform an internal reset. configurat ion context is preserved. 2reserved 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the intel mei host cont roller and to set a new po wer state. the values are: 00 = d0 state (default) 11 = d3 hot state the d1 and d2 states are not supported for the intel mei host controller. when in the d3 hot state, the intel me?s configuration space is available, but the register memory spaces are not. additional ly, interrupts are blocked. bit description 15:8 next pointer (next) ? ro. value of 00h indicates that this is the last item in the list. 7:0 capability id (cid) ? ro. capabilities id indicates msi.
datasheet 877 intel? management engine subsystem registers (d22:f[3:0]) 23.1.1.21 mcmessage signaled in terrupt message control register (intel ? mei 1d22:f0) address offset: 8eh?8fh attribute: r/w, ro default value: 0080h size: 16 bits 23.1.1.22 mamessage signaled in terrupt message address register (intel ? mei 1d22:f0) address offset: 90h?93h attribute: r/w, ro default value: 00000000h size: 32 bits 23.1.1.23 muamessage signaled interrupt upper address register (intel ? mei 1d22:f0) address offset: 94h?97h attribute: r/w default value: 00000000h size: 32 bits 23.1.1.24 mdmessage signaled in terrupt message data register (intel ? mei 1d22:f0) address offset: 98h?99h attribute: r/w default value: 0000h size: 16 bits bit description 15:8 reserved 7 64 bit address capable (c64) ? ro. specifies that function is capable of generating 64-bit messages. 6:1 reserved 0 msi enable (msie) ? r/w. if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. bit description 31:2 address (addr) ? r/w. lower 32 bits of the sy stem specified message address, always dw aligned. 1:0 reserved bit description 31:0 upper address (uaddr) ? r/w. upper 32 bits of th e system specified message address, always dw aligned. bit description 15:0 data (data) ? r/w. this 16-bit field is programm ed by system software if msi is enabled. its content is driven during the data phase of the msi memory write transaction.
intel? management engine subsystem registers (d22:f[3:0]) 878 datasheet 23.1.1.25 hidmmei interrupt delivery mode register (intel ? mei 1d22:f0) address offset: a0h attribute: r/w default value: 00h size: 8 bits 23.1.1.26 heresintel ? mei extend register status (intel ? mei 1d22:f0) address offset: bch?bfh attribute: ro default value: 00h size: 32 bits bit description 7:2 reserved 1 intel mei interrupt delivery mode (hidm) ? r/w. these bits control what type of interrupt the intel mei will send the host. they are interpreted as follows: 00 = generate legacy or msi interrupt 01 = generate sci 10 = generate smi 0 synchronous smi occurrence (ssmio) ? r/wc. this bit is used by firmware to indicate that a synchronous smi source ha s been triggered. host bios smm handler can use this bit as status indication and clear it once processing is completed. a write of 1 from host sw clears this status bit. note: it is possible that an async smi has oc curred prior to sync smi occurrence and when the bios enters the smm handler, it is possible that both bit 0 and bit 1 of this register could be set. bit description 31 extend register valid (erv). set by firmware after all firmwa re has been loaded. if era fi eld is sha-1, the result of the extend operation is in her:5-1. if era field is sha-256, the result of the extend operation is in her:8-1. 30 extend feature present (efp). this bit is hardwired to 1 to allow driver so ftware to easily dete ct the chipset supports the extend register fw measurement feature. 29:4 reserved 3:0 extend register algorithm (era). this field indicates the hash algorithm used in the fw measurement extend operations. encodings are: 0h = sha-1 2h = sha-256 other values = reserved.
datasheet 879 intel? management engine subsystem registers (d22:f[3:0]) 23.1.1.27 herxintel ? mei extend register dwx (intel ? mei 1d22:f0) address offset: her1: c0h?c3h attribute: ro her2: c4h?c7h her3: c8h?cbh her4: cch?cfh her5: d0h?d3h her6: d4h?d7h her7: d8h?dbh her8: dch?dfh default value: 00000000h size: 32 bits 23.1.2 mei0_mbarintel ? mei 1 mmio registers these mmio registers are accessible starting at the intel mei 1 mmio base address (mei0_mbar) which gets programmed into d22:f0:offset 10?17h. these registers are reset by pltrst# unless otherwise noted. 23.1.2.1 h_cb_wwhost circular buffer write window register (intel ? mei 1 mmio register) address offset: mei0_mbar + 00h attribute: ro default value: 00000000h size: 32 bits bit description 31:0 extend register dwx (erdwx). nth dword result of the extend operation. note: extend operation is her[5:1] if using sha-1. if using sha-2 then extend operation is her[8:1] table 23-2. intel ? mei 1 mmio register address map mei0_mbar+ offset mnemonic register name default attribute 00?03h h_cb_ww host circular buffer write window 00000000h ro 04h?07h h_csr host control status 02000000h ro, r/w, r/wc 08h?0bh me_cb_rw intel me circular buffer read window 00000000h ro 0ch?0fh me_csr_ha intel me control status host access 02000000h ro bit description 31:0 host circular buffer write window field (h_cb_wwf) . this bit field is for host to write into its circular buffer. the host's circular buffer is located at the intel me subsystem address specified in the host cb base address re gister. this field is write only, reads will return arbitrary data. writes to this register will increment the h_cbwp as long as me_rdy is 1. when me_rdy is 0, writes to this register have no effect and are not delivered to the h_cb, nor is h_cbwp incriminated.
intel? management engine subsystem registers (d22:f[3:0]) 880 datasheet 23.1.2.2 h_csrhost control status register (intel ? mei 1 mmio register) address offset: mei0_mbar + 04h attribute: ro, r/w, r/wc default value: 02000000h size: 32 bits bit description 31:24 host circular buff er depth (h_cbd) ? ro. this field indicates the maximum number of 32 bit entries available in the host circular buffer (h_cb). host software uses this field along with the h_cbrp and h_cbwp fields to calculate the number of valid entries in the h_cb to read or # of entries available for write. this field is implemented with a "1-hot" sche me. only one bit will be set to a "1" at a time. each bit position represents the value n of a buffe r depth of (2^n). for example, when bit# 1 is 1, the buffer de pth is 2; when bit#2 is 1, th e buffer depth is 4, etc. the allowed buffer depth values are 2, 4, 8, 16, 32, 64 and 128. 23:16 host cb write pointer (h_cbwp) ? ro. points to next location in the h_cb for host to write the data. software uses this field along with h_cbrp and h_cbd fields to calculate the number of valid entries in the h_cb to read or number of entries available for write. 15:8 host cb read pointer (h_cbrp) ? ro. points to next location in the h_cb where a valid data is available for embedded controll er to read. software uses this field along with h_cbwr and h_cbd fields to calculate th e number of valid entries in the host cb to read or number of entries available for write. 7:5 reserved note: for writes to this register, these bits shall be written as 000b. 4 host reset (h_rst) ? r/w. setting this bit to 1 will initiate a intel mei reset sequence to get the circular buffers into a known good state for host and intel me communication. when this bit transitions fro m 0 to 1, hardware will clear the h_rdy and me_rdy bits. 3 host ready (h_rdy) ? r/w. this bit indicates that the host is ready to process messages. 2 host interrupt generate (h_ig) ? r/w. once message(s) are written into its cb, the host sets this bit to one for the hw to set the me_is bit in the me_csr and to generate an interrupt message to intel me. hw will send the interrupt message to intel me only if the me_ie is enabled. hw then clears this bit to 0. 1 host interrupt status (h_is) ? r/wc. hardware sets this bit to 1 when me_ig bit is set to 1. host clears this bit to 0 by writing a 1 to this bit position. h_ie has no effect on this bit. 0 host interrupt enable (h_ie) ? r/w. host sets this bi t to 1 to enable the host interrupt (intr# or msi) to be asserted when h_is is set to 1.
datasheet 881 intel? management engine subsystem registers (d22:f[3:0]) 23.1.2.3 me_cb_rwintel ? me circular buffer read window register (intel ? mei 1 mmio register) address offset: mei0_mbar + 08h attribute: ro default value: ffffffffh size: 32 bits 23.1.2.4 me_csr_haintel ? me control status host access register (intel ? mei 1 mmio register) address offset: mei0_mbar + 0ch attribute: ro default value: 02000000h size: 32 bits bit description 31:0 intel me circular buffer read window field (me_cb_rwf) . this bit field is for host to read from the intel me circular buffer. the intel me's circular buffer is located at the intel me subsystem address specified in th e intel me cb base ad dress register. this field is read only, writes have no effect. reads to this register will increment the me_cbrp as long as me_rdy is 1. when me_rd y is 0, reads to this register have no effect, all 1s are returned, an d me_cbrp is not incremented. bit description 31:24 intel me circular buffer depth host read access (me_cbd_hra) . host read only access to me_cbd. 23:16 intel me cb write pointer host read access (me_cbwp_hra) . host read only access to me_cbwp. 15:8 intel me cb read pointer host read access (me_cbrp_hra) . host read only access to me_cbrp. 7:5 reserved 4 intel me reset host re ad access (me_rst_hra) . host read access to me_rst. 3 intel me ready host re ad access (me_rdy_hra): host read access to me_rdy. 2 intel me interrupt generate host read access (me_ig_hra) . host read only access to me_ig. 1 intel me interrupt status host read access (me_is_hra) . host read only access to me_is. 0 intel me interrupt enable host read access (me_ie_hra) . host read only access to me_ie.
intel? management engine subsystem registers (d22:f[3:0]) 882 datasheet 23.2 second intel ? management engine interface (intel ? mei 2) configuration registers (intel ? mei 2d22:f1) 23.2.1 pci configuration registers (intel ? mei 2d22:f2) table 23-3. intel ? mei 2 configuration registers address map (intel ? mei 2d22:f1) (sheet 1 of 2) offset mnemonic register name default attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h r/w, ro 06h?07h pcists pci status 0010h ro 08h rid revision identification see register description ro 09h?0bh cc class code 0c8000h ro 0eh htype header type 00h ro 10h?17h mei_mbar mei0 mmio base address 00000000000 00004h r/w, ro 2ch?2dh svid subsystem vendor id 0000h r/wo 2eh?2fh sid subsystem id 0000h r/wo 34h capp capabilities list pointer 50h ro 3ch?3dh intr interrupt information 0000h r/w, ro 40h?43h hfs host firmware status 00000000h ro 48h?4bh gmes general intel me status 00000000h ro 4ch?4fh h_gs host general status 00000000h ro 50h?51h pid pci power management capability id 6001h ro 52h?53h pc pci power management capabilities c803h ro 54h?55h pmcs pci power management control and status 0008h r/wc, r/w, ro 8ch?8dh mid message signaled interrupt identifiers 0005h ro 8eh?8fh mc message signaled interrupt message control 0080h r/w, ro 90h?93h ma message signaled interrupt message address 00000000h r/w, ro 94h?97h mua message signaled interrupt upper address 00000000h r/w 98h?99h md message signaled interrupt message data 0000h r/w
datasheet 883 intel? management engine subsystem registers (d22:f[3:0]) 23.2.1.1 vidvendor identification register (intel ? mei 2d22:f1) address offset: 00h ? 01h attribute: ro default value: 8086h size: 16 bits 23.2.1.2 diddevice identification register (intel ? mei 2d22:f1) address offset: 02h?03h attribute: ro default value: see bit description size: 16 bits a0h hidm intel mei interrupt delivery mode 00h r/w bc?bfh heres intel mei extended register status 40000000h ro c0?dfh her[1:8] intel mei extended register dw[1:8] 00000000h ro table 23-3. intel ? mei 2 configuration registers address map (intel ? mei 2d22:f1) (sheet 2 of 2) offset mnemonic register name default attribute bit description 15:0 vendor id (vid) ? ro. this is a 16-bit value assigned to intel. bit description 15:0 device id (did) ? ro. this is a 16-bit value assigned to the intel management engine interface controller. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the did register.
intel? management engine subsystem registers (d22:f[3:0]) 884 datasheet 23.2.1.3 pcicmdpci command register (intel ? mei 2d22:f1) address offset: 04h?05h attribute: r/w, ro default value: 0000h size: 16 bits 23.2.1.4 pcistspci status register (intel ? mei 2d22:f1) address offset: 06h ? 07h attribute: ro default value: 0010h size: 16 bits bit description 15:11 reserved 10 interrupt disable (id) ? r/w. disables this device from generating pci line based interrupts. this bit does not have any effect on msi operation. 9:3 reserved 2 bus master enable (bme) ? r/w. controls the intel mei host controller's ability to act as a system memory master fo r data transfers. when this bit is cleared, intel mei bus master activity stops and any active dma engines return to an idle condition. this bit is made visible to firmware through the h_pci_ csr register, and chan ges to this bit may be configured by the h_pci_csr register to generate an intel me msi. when this bit is 0, intel mei is blocked from genera ting msi to the host processor. note: this bit does not block intel mei accesses to intel me uma; that is, writes or reads to the host and intel me circular buffers through the read window and write window registers still cause intel me backbone transactions to intel me uma. 1 memory space enable (mse) ? r/w. controls access to the intel me's memory mapped register space. 0 = disable. memory cycles within the rang e specified by the memory base and limit registers are master aborted. 1 = enable. allows memory cycles within th e range specified by the memory base and limit registers accepted. 0 reserved bit description 15:5 reserved 4 capabilities list (cl) ? ro. indicates the pres ence of a capabilities list, hardwired to 1. 3 interrupt status ? ro. indicates the interrupt status of the device. 0 = interrupt is deasserted. 1 = interrupt is asserted. 2:0 reserved
datasheet 885 intel? management engine subsystem registers (d22:f[3:0]) 23.2.1.5 ridrevision identification register (intel ? mei 2d22:f1) offset address: 08h attribute: ro default value: see bit description size: 8 bits 23.2.1.6 ccclass code register (intel ? mei 2d22:f1) address offset: 09h ? 0bh attribute: ro default value: 078000h size: 24 bits 23.2.1.7 htypeheader type register (intel ? mei 2d22:f1) address offset: 0eh attribute: ro default value: 80h size: 8 bits 23.2.1.8 mei_mbarintel ? mei mmio base address register (intel ? mei 2d22:f1) address offset: 10h ? 17h attribute: r/w, ro default value: 0000000000000004h size: 64 bits this register allocates space for th e intel mei memory mapped registers. bit description 7:0 revision id ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit description 23:16 base class code (bcc) ? ro. indicates the base class code of the intel mei device. 15:8 sub class code (scc) ? ro. indicates the sub class code of the intel mei device. 7:0 programming interface (pi) ? ro. indicates the programming interface of the intel mei device. bit description 7 multi-function device (mfd) ? ro. indicates the intel mei host controller is part of a multifunction device. 6:0 header layout (hl) ? ro. indicates that the intel mei uses a target device layout. bit description 63:4 base address (ba) r/w . software programs this fiel d with the base address of this region. 3 prefetchable memory (pm) ? ro. indicates that this range is not pre-fetchable. 2:1 type (tp) ? ro. set to 10b to indicate that this range can be mapped anywhere in 64-bit address space. 0 resource type indicator (rte) ? ro. indicates a reques t for register memory space.
intel? management engine subsystem registers (d22:f[3:0]) 886 datasheet 23.2.1.9 svidsubsystem vendor id register (intel ? mei 2d22:f1) address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits 23.2.1.10 sidsubsystem id register (intel ? mei 2d22:f1) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits 23.2.1.11 cappcapabilities list pointer register (intel ? mei 2d22:f1) address offset: 34h attribute: ro default value: 50h size: 8 bits 23.2.1.12 intrinterrup t information register (intel ? mei 2d22:f1) address offset: 3ch?3dh attribute: r/w, ro default value: 0100h size: 16 bits bit description 15:0 subsystem vendor id (ssvid) ? r/wo. indicates the sub-system vendor identifier. this field should be programmed by bios during boot-up. once written, this register becomes read only. this fiel d can only be cleared by pltrst#. note: register must be written as a word writ e or as a dword write with sid register. bit description 15:0 subsystem id (ssid) ? r/wo. indicates the sub-system identifier. this field should be programmed by bios during boot-up. on ce written, this register becomes read only. this field can only be cleared by pltrst#. note: register must be written as a word write or as a dword write with svid register. bit description 7:0 capabilities pointer (ptr) ? ro. indicates that the pointe r for the first entry in the capabilities list is at 50h in configuration space. bit description 15:8 interrupt pin (ipin) ? ro. this field indi cates the interrupt pin the intel mei host controller uses. a value of 1h/2h/3h/4h indica tes that this function implements legacy interrupt on inta/intb/in tc/intd, respectively. 7:0 interrupt line (iline) ? r/w. software written value to indicate which interrupt line (vector) the interrupt is conne cted to. no hardware action is taken on this register.
datasheet 887 intel? management engine subsystem registers (d22:f[3:0]) 23.2.1.13 hfshost firmware status register (intel ? mei 2d22:f1) address offset: 40h?43h attribute: ro default value: 00000000h size: 32 bits 23.2.1.14 gmesgeneral intel ? me status register (intel ? mei 2d22:f1) address offset: 48h?4bh attribute: ro default value: 00000000h size: 32 bits 23.2.1.15 h_gshost general status register (intel ? mei 2d22:f1) address offset: 4ch?4fh attribute: ro default value: 00000000h size: 32 bits bit description 31:0 host firmware status (hfs) ? ro. this register field is used by firmware to reflect the operating environment to the host. bit description 31:0 general intel me status (me_gs) ? ro. this field is populated by intel me. bit description 31:0 host general status(h_gs) ? ro. general status of host, this field is not used by hardware
intel? management engine subsystem registers (d22:f[3:0]) 888 datasheet 23.2.1.16 pidpci power management capability id register (intel ? mei 2d22:f1) address offset: 50h?51h attribute: ro default value: 6001h size: 16 bits 23.2.1.17 pcpci power manage ment capabilities register (intel ? mei 2d22:f1) address offset: 52h ? 53h attribute: ro default value: c803h size: 16 bits 23.2.1.18 pmcspci power management control and status register (intel ? mei 2d22:f1) address offset: 54h ? 55h attribute: r/wc, r/w, ro default value: 0008h size: 16 bits bit description 15:8 next capability (next) ? ro. value of 60h indicates the location of the next pointer. 7:0 capability id (cid) ? ro. indicates the linked list item is a pci power management register. bit description 15:11 pme_support (psup) ? ro. this five-bit field indicates the power states in which the function may assert pme#. in tel mei can assert pme# from any d-state except d1 or d2 which are not supported by intel mei. 10:9 reserved 8:6 aux_current (ac) ? ro. reports the maximum suspen d well current required when in the d3 cold state. value of 00b is reported. 5 device specific initialization (dsi) ? ro. indicates whet her device-specific initialization is required. 4reserved 3 pme clock (pmec) ? ro. indicates that pci clock is not required to generate pme#. 2:0 version (vs) ? ro. hardwired to 011b to indicate support for revision 1.2 of the pci power management specification . bit description 15 pme status (pmes) ? r/wc. bit is set by intel me firm ware. host software clears bit by writing 1 to bit. this bit is reset when cl_rst1# is asserted. 14:9 reserved 8 pme enable (pmee) ? r/w. this bit is read/write and is under the control of host sw. it does not directly have an effect on pme events. however, this bit is shadowed so intel me fw can monitor it. intel me fw will not cause the pmes bit to transition to 1 while the pmee bit is 0, indicating that host sw had disabled pme. this bit is reset wh en pltrst# asserted. 7:4 reserved
datasheet 889 intel? management engine subsystem registers (d22:f[3:0]) 23.2.1.19 midmessage signaled interrupt identifiers register (intel ? mei 2d22:f1) address offset: 8ch-8dh attribute: ro default value: 0005h size: 16 bits 23.2.1.20 mcmessage signaled in terrupt message control register (intel ? mei 2d22:f1) address offset: 8eh?8fh attribute: r/w, ro default value: 0080h size: 16 bits 23.2.1.21 mamessage signaled in terrupt message address register (intel ? mei 2d22:f1) address offset: 90h?93h attribute: r/w, ro default value: 00000000h size: 32 bits 3 no_soft_reset (nsr) ? ro. this bit indicates that when the intel mei host controller is transitioning from d3 hot to d0 due to a power state co mmand, it does not perform an internal reset. configurat ion context is preserved. 2 reserved 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the intel mei host controller and to set a new power state. the values are: 00 = d0 state (default) 11 = d3 hot state the d1 and d2 states are not supported for the intel mei host controller. when in the d3 hot state, the intel me?s configuration spac e is available, but the register memory spaces are not. additionally, interrupts are blocked. bit description bit description 15:8 next pointer (next) ? ro. value of 00h indicates that this is the last item in the list. 7:0 capability id (cid) ? ro. capabilities id indicates msi. bit description 15:8 reserved 7 64 bit address capable (c64) ? ro. specifies that function is capable of generating 64-bit messages. 6:1 reserved 0 msi enable (msie) ? r/w. if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. bit description 31:2 address (addr) ? r/w. lower 32 bits of the sy stem specified message address, always dw aligned. 1:0 reserved
intel? management engine subsystem registers (d22:f[3:0]) 890 datasheet 23.2.1.22 muamessage signaled interrupt upper address register (intel ? mei 2d22:f1) address offset: 94h?97h attribute: r/w default value: 00000000h size: 32 bits 23.2.1.23 mdmessage signaled in terrupt message data register (intel ? mei 2d22:f1) address offset: 98h?99h attribute: r/w default value: 0000h size: 16 bits 23.2.1.24 hidmintel ? mei interrupt delivery mode register (intel ? mei 2d22:f1) address offset: a0h attribute: r/w default value: 00h size: 8 bits bit description 31:0 upper address (uaddr) ? r/w. upper 32 bits of the system specified message address, always dw aligned. bit description 15:0 data (data) ? r/w. this 16-bit field is programmed by system software if msi is enabled. its content is driven during the data phase of the msi memory write transaction. bit description 7:2 reserved 1 intel mei interrupt delivery mode (hidm) ? r/w. these bits control what type of interrupt the intel mei will send the host. they are interpreted as follows: 00 = generate legacy or msi interrupt 01 = generate sci 10 = generate smi 0 synchronous smi occurrence (ssmio) ? r/wc. this bit is used by firmware to indicate that a synchronous smi source ha s been triggered. host bios smm handler can use this bit as status indication and clear it once processing is completed. a write of 1 from host sw clears this status bit. note: it is possible that an async smi has oc curred prior to sync smi occurrence and when the bios enters the smm handler, it is possible that both bit 0 and bit 1 of this register could be set.
datasheet 891 intel? management engine subsystem registers (d22:f[3:0]) 23.2.1.25 heresintel ? mei extend register status (intel ? mei 2d22:f1) address offset: bch?bfh attribute: ro default value: 00h size: 32 bits 23.2.1.26 herxintel ? mei extend register dwx (intel ? mei 2d22:f1) address offset: her1: c0h?c3h attribute: ro her2: c4h?c7h her3: c8h?cbh her4: cch?cfh her5: d0h?d3h her6: d4h?d7h her7: d8h?dbh her8: dch?dfh default value: 00000000h size: 32 bits bit description 31 extend register valid (erv). set by firmware after all fi rmware has been loaded. if era field is sha-1, the result of the extend operation is in her:5-1. if era field is sha- 256, the result of the exte nd operation is in her:8-1. 30 extend feature present (efp). this bit is hardwired to 1 to allow driver software to easily detect the chipset supports the ex tend register fw measurement feature. 29:4 reserved 3:0 extend register algorithm (era). this field indicates the ha sh algorithm used in the fw measurement extend operations. encodings are: 0h = sha-1 2h = sha-256 other values = reserved bit description 31:0 extend register dwx (erdwx): xth dword result of the extend operation. note: extend operation is her[5:1] if using sha-1. if using sha-2, then extend operation is her[8:1].
intel? management engine subsystem registers (d22:f[3:0]) 892 datasheet 23.2.2 mei1_mbarintel ? mei 2 mmio registers these mmio registers are accessible starting at the intel mei 2 mmio base address (mei1_mbar) which gets programmed into d22:f1:offset 10?17h. these registers are reset by pltrst# unless otherwise noted. 23.2.2.1 h_cb_wwhost circular buffer write window (intel ? mei 2 mmio register) address offset: mei1_mbar + 00h attribute: ro default value: 00000000h size: 32 bits table 23-4. intel ? mei 2 mmio register address map mei1_mbar + offset mnemonic register name default attribute 00?03h h_cb_ww host circular buffer write window 00000000h ro 04h?07h h_csr host control status 02000000h r/w, r/wc, ro 08h?0bh me_cb_rw intel me circular buffer read window 00000000h ro 0ch?0fh me_csr_ha intel me control status host access 02000000h ro bit description 31:0 host circular buffer write window field (h_cb_wwf) . this bit field is for host to write into its circular buffer. the host's circular buffer is located at the intel me subsystem address specified in the host cb base address register. this field is write only, reads will return arbitrar y data. writes to this register will increment the h_cbwp as long as me_rdy is 1. when me_rdy is 0, writes to this register have no effect and are not delivered to the h_cb, nor is h_cbwp incremented.
datasheet 893 intel? management engine subsystem registers (d22:f[3:0]) 23.2.2.2 h_csrhost control status register (intel ? mei 2 mmio register) address offset: mei1_mbar + 04h attribute: ro, r/w, r/wc default value: 02000000h size: 32 bits bit description 31:24 host circular buff er depth (h_cbd) ? ro. this field indicates the maximum number of 32 bit entries available in the host circular buffer (h_cb) . host software uses this field along with the h_cbrp and h_cbwp fields to calculate the number of valid entries in the h_cb to read or # of entries available for write. this field is implemented with a "1-hot" sche me. only one bit will be set to a "1" at a time. each bit position represents the value n of a buffer depth of (2^n). for example, when bit# 1 is 1, the buffer de pth is 2; when bit#2 is 1, the buffer depth is 4, etc. the allowed buffer depth values are 2, 4, 8, 16, 32, 64 and 128. 23:16 host cb write pointer (h_cbwp) ? ro. points to next location in the h_cb for host to write the data. software uses this fiel d along with h_cbrp and h_cbd fields to calculate the number of valid entries in the h_cb to read or number of entries available for write. 15:8 host cb read pointer (h_cbrp) ? ro. points to next location in the h_cb where a valid data is available for em bedded controller to read. soft ware uses this field along with h_cbwr and h_cbd fields to calculate the number of valid entries in the host cb to read or number of entries available for write. 7:5 reserved note: for writes to this register, these bits shall be written as 000b. 4 host reset (h_rst) ? r/w. setting this bit to 1 will initiate a intel mei reset sequence to get the circular buffers into a known good state for host and intel me communication. when this bit transitions fro m 0 to 1, hardware will clear the h_rdy and me_rdy bits. 3 host ready (h_rdy) ? r/w. this bit indicates that the host is ready to process messages. 2 host interrupt generate (h_ig) ? r/w. once message(s) are written into its cb, the host sets this bit to one for the hw to set the me_is bit in the me_csr and to generate an interrupt message to intel me. hw will send the interrupt message to intel me only if the me_ie is enabled. hw then clears this bit to 0. 1 host interrupt status (h_is) ? r/wc. hardware sets this bit to 1 when me_ig bit is set to 1. host clears this bit to 0 by writing a 1 to this bit position. h_ie has no effect on this bit. 0 host interrupt enable (h_ie) ? r/w. host sets this bit to 1 to enable the host interrupt (intr# or msi) to be asserted when h_is is set to 1.
intel? management engine subsystem registers (d22:f[3:0]) 894 datasheet 23.2.2.3 me_cb_rwintel ? me circular buffer read window register (intel ? mei 2 mmio register) address offset: mei1_mbar + 08h attribute: ro default value: ffffffffh size: 32 bits 23.2.2.4 me_csr_haintel ? me control status host access register (intel ? mei 2 mmio register) address offset: mei1_mbar + 0ch attribute: ro default value: 02000000h size: 32 bits bit description 31:0 intel me circular buffer read window field (me_cb_rwf) . this bit field is for host to read from the intel me ci rcular buffer. the in tel me's circular buffer is located at the intel me subsystem address specified in th e intel me cb base address register. this field is read only, writes have no effect. reads to this register will increment the me_cbrp as long as me_rdy is 1. when me_rdy is 0, reads to this register have no effect, all 1s are returned, and me_cbrp is not incremented. bit description 31:24 intel me circular buffer depth host read access (me_cbd_hra) . host read only access to me_cbd. 23:16 intel me cb write pointer host read access (me_cbwp_hra) . host read only access to me_cbwp. 15:8 intel me cb read pointer host read access (me_cbrp_hra) . host read only access to me_cbrp. 7:5 reserved 4 intel me reset host re ad access (me_rst_hra) . host read access to me_rst. 3 intel me ready host read access (me_rdy_hra) . host read access to me_rdy. 2 intel me interrupt generate host read access (me_ig_hra) . host read only access to me_ig. 1 intel me interrupt status host read access (me_is_hra) . host read only access to me_is. 0 intel me interrupt enable host read access (me_ie_hra) . host read only access to me_ie.
datasheet 895 intel? management engine subsystem registers (d22:f[3:0]) 23.3 ide redirect ider registers (ider d22:f2) 23.3.1 pci configuration registers (iderd22:f2) table 23-5. ide redirect functi on ider register address map address offset register symbol register name default value attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h pcicmd pci command 0000h ro, r/w 06h?07h pcists pci status 00b0h ro 08h rid revision id see register description ro 09h?0bh cc class codes 010185h ro 0ch cls cache line size 00h ro 10h?13h pcmdba primary command block io bar 00000001h ro, r/w 14h?17h pctlba primary control block base address 00000001h ro, r/w 18h?1bh scmdba secondary command bl ock base address 00000001h ro, r/w 1ch?1fh sctlba secondary control block base address 00000001h ro, r/w 20h?23h lbar legacy bus master base address 00000001h ro, r/w 2ch?2dh svid subsystem vendor id 0000h r/wo 2eh?2fh sid subsystem id 8086h r/wo 34h capp capabiliti es pointer c8h ro 3ch?3dh intr interrupt information 0300h r/w, ro c8h?c9h pid pci power management capability id d001h ro cah?cbh pc pci power management capabilities 0023h ro cch?cfh pmcs pci power management control and status 00000000h ro, r/w, ro/v d0h?d1h mid message signaled interrupt capability id 0005h ro d2h?d3h mc message signaled interrupt message control 0080h ro, r/w d4h?d7h ma message signaled interrupt message address 00000000h r/w, ro d8h?dbh mau message signaled interrupt message upper address 00000000h ro, r/w dc?ddh md message signaled interrupt message data 0000h r/w
intel? management engine subsystem registers (d22:f[3:0]) 896 datasheet 23.3.1.1 vidvendor identification register (iderd22:f2) address offset: 00?01h attribute: ro default value: 8086h size: 16 bits 23.3.1.2 diddevice identification register (iderd22:f2) address offset: 02?03h attribute: ro default value: see bit description size: 16 bits 23.3.1.3 pcicmd pci command register (iderd22:f2) address offset: 04?05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:0 vendor id (vid) ? ro. this is a 16-bit value assigned by intel. bit description 15:0 device id (did) ? ro. this is a 16-bit value assigned to the pch ider controller. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the did register. bit description 15:11 reserved 10 interrupt disable (id) ?r/w . this disables pin-based in tx# interrupts. this bit has no effect on msi operation. when se t, internal intx# messages will not be generated. when cleared, internal intx# messages are generated if there is an interrupt and msi is not enabled. 9:3 reserved 2 bus master enable (bme) ?ro. this bit controls the pt function's ability to act as a master for data transfers. this bit does no t impact the generation of completions for split transaction commands. 1 memory space enable (mse) ?ro. pt function does not contain target memory space. 0 i/o space enable (iose) ?ro. this bit controls access to the pt function's target i/o space.
datasheet 897 intel? management engine subsystem registers (d22:f[3:0]) 23.3.1.4 pcistspci device status register (iderd22:f2) address offset: 06?07h attribute: ro default value: 00b0h size: 16 bits 23.3.1.5 ridrevision identification register (iderd22:f2) address offset: 08h attribute: ro default value: see bit description size: 8 bits 23.3.1.6 ccclass codes re gister (iderd22:f2) address offset: 09?0bh attribute: ro default value: 010185h size: 24 bits 23.3.1.7 clscache line size register (iderd22:f2) address offset: 0ch attribute: ro default value: 00h size: 8 bits bit description 15:11 reserved 10:9 devsel# timing status (devt) ?ro. this bit controls the de vice select time for the pt function's pci interface. 8:5 reserved 4 capabilities list (cl) ?ro. this bit indicates that ther e is a capabili ties pointer implemented in the device. 3 interrupt status (is) ?ro. this bit reflects the state of the interrupt in the function. setting of the interrupt disable bit to 1 has no affect on this bit. only when this bit is a 1 and id bi t is 0 is the intc interru pt asserted to the host. 2:0 reserved bit description 7:0 revision id ?ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit description 23:16 base class code (bcc) ?ro this field indicates the base class code of the ider host controller device. 15:8 sub class code (scc) ?ro this field indicates the sub cl ass code of the ider host controller device. 7:0 programming interface (pi) ?ro this field indicates the programming interface of the ider host controller device. bit description 7:0 cache line size (cls) ?ro. all writes to system memory are memory writes.
intel? management engine subsystem registers (d22:f[3:0]) 898 datasheet 23.3.1.8 pcmdbaprimary command block io bar register (iderd22:f2) address offset: 10?13h attribute: ro, r/w default value: 00000001h size: 32 bits 23.3.1.9 pctlbaprimary control block base address register (iderd22:f2) address offset: 14?17h attribute: ro, r/w default value: 00000001h size: 32 bits 23.3.1.10 scmdbasecondary command block base address register (iderd22:f2) address offset: 18?1bh attribute: ro, r/w default value: 00000001h size: 32 bits bit description 31:16 reserved 15:3 base address (bar) ?r/w base address of the bar0 i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ?ro. this bit indicates a request for i/o space. bit description 31:16 reserved 15:2 base address (bar) ?r/w. base address of the bar1 i/o space (4 consecutive i/o locations) 1 reserved 0 resource type indicator (rte) ?ro. this bit indicates a request for i/o space bit description 31:16 reserved 15:3 base address (bar) ?r/w. base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ?ro. this bit indicates a request for i/o space.
datasheet 899 intel? management engine subsystem registers (d22:f[3:0]) 23.3.1.11 sctlbasecondary control block base address register (iderd22:f2) address offset: 1c?1fh attribute: ro, r/w default value: 00000001h1 size: 32 bits 23.3.1.12 lbarlegacy bus mast er base address register (iderd22:f2) address offset: 20?23h attribute: ro, r/w default value: 00000001h size: 32 bits 23.3.1.13 svidsubsystem vendor id register (iderd22:f2) address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits 23.3.1.14 sidsubsystem id register (iderd22:f2) address offset: 2eh ? 2fh attribute: r/wo default value: 8086h size: 16 bits bit description 31:16 reserved 15:2 base address (bar) ?r/w. base address of the i/o space (4 consecutive i/o locations). 1reserved 0 resource type indicator (rte) ?ro. this bit indicates a request for i/o space. bit description 31:16 reserved 15:4 base address (ba) ?r/w. base address of the i/o space (16 consecutive i/o locations). 3:1 reserved 0 resource type indicator (rte) ?ro. this bit indicates a request for i/o space. bit description 15:0 subsystem vendor id (ssvid) ? r/wo. indicates the sub-system vendor identifier. this field should be programmed by bios during boot-up. once written, this register becomes read on ly. this field can only be cleared by pltrst#. note: register must be written as a dword write with sid register. bit description 15:0 subsystem id (ssid) ? r/wo. indicates the sub-system identifier. this field should be programmed by bios during boot-up. on ce written, this register becomes read only. this field can only be cleared by pltrst#. note: register must be written as a dword write with svid register.
intel? management engine subsystem registers (d22:f[3:0]) 900 datasheet 23.3.1.15 cappcapabilities list pointer register (iderd22:f2) address offset: 34h attribute: ro default value: c8h size: 8 bits 23.3.1.16 intrinterrupt information register (iderd22:f2) address offset: 3c?3dh attribute: r/w, ro default value: 0300h size: 16 bits 23.3.1.17 pidpci power management capability id register (iderd22:f2) address offset: c8?c9h attribute: ro default value: d001h size: 16 bits bit description 7:0 capability pointer (cp) ? r/wo. this field indicates that th e first capability pointer is offset c8h (the powe r management capability). bit description 15:8 interrupt pin (ipin) ? ro. a value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on inta/intb/intc/intd, respectively functionvalueintx (2 ide)03hintc 7:0 interrupt line (iline) ? r/w. the value written in this register indicates which input of the system interrupt controller, the device's interrupt pin is connected to. this value is used by the os and the de vice driver, and has no affect on the hardware. bit description 15:8 next capability (next) ? ro. its value of d0h points to the msi capability. 7:0 cap id (cid) ? ro. this field indicates that this po inter is a pci power management.
datasheet 901 intel? management engine subsystem registers (d22:f[3:0]) 23.3.1.18 pcpci power manage ment capabilities register (iderd22:f2) address offset: ca?cbh attribute: ro default value: 0023h size: 16 bits 23.3.1.19 pmcspci power management control and status register (iderd22:f2) address offset: cc-cfh attribute: ro, r/w default value: 00000000h size: 32 bits bit description 15:11 pme_support (psup) ? ro. this five-bit field indi cates the power states in which the function may assert pme#. ider can assert pme# from any d-state except d1 or d2 which are not supported by ider. 10:9 reserved 8:6 aux_current (ac) ? ro. reports the maximum su spend well current required when in the d3 cold state. value of 00b is reported. 5 device specific initialization (dsi) ? ro. indicates whet her device-specific initialization is required. 4reserved 3 pme clock (pmec) ? ro. indicates that pci clock is not required to generate pme#. 2:0 version (vs) ? ro. hardwired to 011b to indicate support for revision 1.2 of the pci power management specification . bit description 31:4 reserved 3 no soft reset (nsr) ? ro. 0 = devices do perform an in ternal reset upon transition ing from d3hot to d0 using software control of the po werstate bits. configuration context is lost when performing the soft reset. up on transition from the d3hot to the d0 state, full re- initialization sequence is needed to return the device to d0 initialized. 1 = this bit indicates that devices transitioning from d3hot to d0 because of powerstate commands do not perform an in ternal reset. configuration context is preserved. upon transition from the d3hot to the d0 initialized state, no additional operating system intervention is required to preserve configuration context beyond writing the powerstate bits. 2reserved 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the pt function and to se t a new power state. the values are: 00 = d0 state 11 = d3 hot state when in the d3 hot state, the controller's configurat ion space is available, but the i/o and memory spaces are not. additionally, in terrupts are blocked. if software attempts to write a '10' or '01' to these bits, the write will be ignored.
intel? management engine subsystem registers (d22:f[3:0]) 902 datasheet 23.3.1.20 midmessage signaled interrupt capability id register (iderd22:f2) address offset: d0?d1h attribute: ro default value: 0005h size: 16 bits 23.3.1.21 mcmessage signaled interrupt message control register (iderd22:f2) address offset: d2?d3h attribute: ro, r/w default value: 0080h size: 16 bits 23.3.1.22 mamessage signaled interrupt message address register (iderd22:f2) address offset: d4?d7h attribute: r/w, ro default value: 00000000h size: 32 bits 23.3.1.23 maumessage signaled interrupt message upper address register (iderd22:f2) address offset: d8?dbh attribute: ro, r/w default value: 00000000h size: 32 bits bit description 15:8 next pointer (next) ? ro. this value indicates this is the last item in the capabilities list. 7:0 capability id (cid) ? ro. the capabilities id value indi cates device is capable of generating an msi. bit description 15:8 reserved 7 64 bit address capable (c64) ? ro. capable of generating 64-bit and 32-bit messages. 6:4 multiple message enable (mme) ? r/w. these bits are r/w for software compatibility, but only one message is ever sent by the pt function. 3:1 multiple message capable (mmc) ? ro. only one message is required. 0 msi enable (msie) ? r/w. if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. bit description 31:2 address (addr) ? r/w. this field contains the lowe r 32 bits of the system specified message address, always dword aligned 1:0 reserved bit description 31:4 reserved 3:0 address (addr) ? r/w. this field contains the upper 4 bits of the system specified message address.
datasheet 903 intel? management engine subsystem registers (d22:f[3:0]) 23.3.1.24 mdmessage signaled interrupt message data register (iderd22:f2) address offset: dc?ddh attribute: r/w default value: 0000h size: 16 bits 23.3.2 ider bar0 registers bit description 15:0 data (data) ? r/w. this content is driven onto the lower word of the data bus of the msi memory write transaction. table 23-6. ider bar0 register address map address offset register symbol register name default value attribute 0h idedata ide data register 00h r/w 1h ideerd1 ide error register dev1 00h r/w 1h ideerd0 ide error register dev0 00h r/w 1h idefr ide features register 00h r/w 2h idescir ide sector count in register 00h r/w 2h idescor1 ide sector count out register device 1 00h r/w 2h idescor0 ide sector count out register device 0 00h r/w 3h idesnor0 ide sector number out register device 0 00h r/w 3h idesnor1 ide sector number out register device 1 00h r/w 3h idesnir ide sector number in register 00h r/w 4h ideclir ide cylinder low in register 00h r/w 4h idclor1 ide cylinder low out register device 1 00h r/w 4h idclor0 ide cylinder low out register device 0 00h r/w 5h idchor0 ide cylinder high out register device 0 00h r/w 5h idchor1 ide cylinder high out register device 1 00h r/w 5h idechir ide cylinder high in re gister 00h r/w 6h idedhir ide drive/head in register 00h r/w 6h iddhor1 ide drive head out register device 1 00h r/w 6h iddhor0 ide drive head out register device 0 00h r/w
intel? management engine subsystem registers (d22:f[3:0]) 904 datasheet 23.3.2.1 idedataide data register (iderd22:f2) address offset: 0h attribute: r/w default value: 00h size: 8 bits the ide data interface is a special interface that is implemented in the hw. this data interface is mapped to io space from the host and takes read and write cycles from the host targeting master or slave device. writes from host to this register result in the data being written to intel me memory. reads from host to this register result in the data being fetched from intel me memory. data is typically written/ read in words. in tel me fw must enable hardware to allow it to accept host initiated read/ write cycles, else the cycles are dropped. 23.3.2.2 ideerd1ide error register dev1 (iderd22:f2) address offset: 01h attribute: r/w default value: 00h size: 8 bits this register implements the error register of the command block of the ide function. this register is read only by the host interface when dev = 1 (slave device). 7h idesd0r ide status device 0 register 80h r/w 7h idesd1r ide status device 1 register 80h r/w 7h idecr ide command register 00h r/w table 23-6. ider bar0 register address map address offset register symbol register name default value attribute bit description 7:0 ide data register (idedr) ? r/w. data register implements the data interface for ide. all writes and reads to this register translate in to one or more corresponding write/reads to intel me memory bit description 7:0 ide error data (ideed) ? r/w. drive reflects its error/ di agnostic code to the host using this register at different times.
datasheet 905 intel? management engine subsystem registers (d22:f[3:0]) 23.3.2.3 ideerd0ide error register dev0 (iderd22:f2) address offset: 01h attribute: r/w default value: 00h size: 8 bits this register implements the error register of the command block of the ide function. this register is read only by the host interface when dev = 0 (master device). 23.3.2.4 idefride features register (iderd22:f2) address offset: 01h attribute: r/w default value: 00h size: 8 bits this register implements the feature register of the command block of the ide function. this register can be written only by the host. when the host reads the same address, it reads the error register of device 0 or device 1 depending on the device_select bit (bit 4 of the drive/head register). 23.3.2.5 idesciride sector count in register (iderd22:f2) address offset: 02h attribute: r/w default value: 00h size: 8 bits this register implements the sector count register of the command block of the ide function. this register can be written only by the host. when host writes to this register, all 3 registers (idescir, idescor0, idescor1) are updated with the written value. a host read to this register address reads the ide sector count out register idescor0 if dev=0 or idescor1 if dev=1 bit description 7:0 ide error data (ideed) ? r/w. drive reflects its error/ di agnostic code to the host using this register at different times. bit description 7:0 ide feature data (idefd) ? r/w. ide drive specific data written by the host bit description 7:0 ide sector count data (idescd) ? r/w. host writes the number of sectors to be read or written.
intel? management engine subsystem registers (d22:f[3:0]) 906 datasheet 23.3.2.6 idescor1ide sector co unt out register device 1 register (iderd22:f2) address offset: 02h attribute: r/w default value: 00h size: 8 bits this register is read by the host interface if dev = 1. intel me firmware writes to this register at the end of a command of the selected device. when the host writes to this address, the id e sector count in register (idescir), this register is updated. 23.3.2.7 idescor0ide sector count out register device 0 register (iderd22:f2) address offset: 02h attribute: r/w default value: 00h size: 8 bits this register is read by the host interface if dev = 0. intel me firmware writes to this register at the end of a command of the selected device. when the host writes to this address, the id e sector count in register (idescir), this register is updated. 23.3.2.8 idesnor0ide sector number out register device 0 register (iderd22:f2) address offset: 03h attribute: r/w default value: 00h size: 8 bits this register is read by the host if dev = 0. intel me firmware writes to this register at the end of a command of the selected device. when the host writes to the ide sector number in register (idesnir), this register is updated with that value. bit description 7:0 ide sector count ou t dev1 (iscod1) ? r/w. sector count register for slave device (that is, device 1) bit description 7:0 ide sector count ou t dev0 (iscod0) ? r/w. sector count register for master device (that is, device 0). bit description 7:0 ide sector number out dev 0 (idesno0) ? r/w. sector number out register for master device.
datasheet 907 intel? management engine subsystem registers (d22:f[3:0]) 23.3.2.9 idesnor1ide sector number out register device 1 register (iderd22:f2) address offset: 03h attribute: r/w default value: 00h size: 8 bits this register is read by the host if dev = 1. intel me firmware writes to this register at the end of a command of the selected device. when the host writes to the ide sector number in register (idesnir), this register is updated with that value. 23.3.2.10 idesniride sector number in register (iderd22:f2) address offset: 03h attribute: r/w default value: 00h size: 8 bits this register implements the sector number register of the command block of the ide function. this register can be written only by the host. when host writes to this register, all 3 registers (idesnir, idesnor0, idesnor1) are updated with the written value. host read to this register address reads the ide sector number out register idesnor0 if dev=0 or idesnor1 if dev=1. 23.3.2.11 idecliride cylinder low in register (iderd22:f2) address offset: 04h attribute: r/w default value: 00h size: 8 bits this register implements the cylinder low register of the command block of the ide function. this register can be written only by the host. when host writes to this register, all 3 registers (ideclir, ideclor0 , ideclor1) are updated with the written value. host read to this register address reads the ide cylinder low out register ideclor0 if dev=0 or ideclor1 if dev=1. bit description 7:0 ide sector number out dev 1 (idesno1) ? r/w. sector number out register for slave device. bit description 7:0 ide sector number data (idesnd) ? r/w. this register cont ains the number of the first sector to be transferred. bit description 7:0 ide cylinder low data (idecld) ? r/w. cylinder low register of the command block of the ide function.
intel? management engine subsystem registers (d22:f[3:0]) 908 datasheet 23.3.2.12 idclor1ide cylinder low out register device 1 register (iderd22:f2) address offset: 04h attribute: r/w default value: 00h size: 8 bits this register is read by the host if dev = 1. intel me firmware writes to this register at the end of a command of the selected device . when the host writes to the ide cylinder low in register (ideclir), this re gister is updated with that value. 23.3.2.13 idclor0ide cylinder low out register device 0 register (iderd22:f2) address offset: 04h attribute: r/w default value: 00h size: 8 bits this register is read by the host if dev = 0. intel me firmware writes to this register at the end of a command of the selected device . when the host writes to the ide cylinder low in register (ideclir), this re gister is updated with that value. 23.3.2.14 idchor0ide cylinder high out register device 0 register (iderd22:f2) address offset: 05h attribute: r/w default value: 00h size: 8 bits this register is read by the host if device = 0. intel me firmware writes to this register at the end of a command of the selected device. when the host writes to the ide cylinder high in register (idechir), this register is updated with that value. bit description 7:0 ide cylinder low out dev 1. (ideclo1) ? r/w. cylinder low out register for slave device. bit description 7:0 ide cylinder low out dev 0. (ideclo0) ? r/w. cylinder low out register for master device. bit description 7:0 ide cylinder high out dev 0 (idecho0) ? r/w. cylinder high out register for master device.
datasheet 909 intel? management engine subsystem registers (d22:f[3:0]) 23.3.2.15 idchor1ide cylinder high out register device 1 register (iderd22:f2) address offset: 05h attribute: r/w default value: 00h size: 8 bits this register is read by the host if device = 1. intel me firmware writes to this register at the end of a command of the selected device. when the host writes to the ide cylinder high in register (idechir), this register is updated with that value. 23.3.2.16 idechiride cylinder high in register (iderd22:f2) address offset: 05h attribute: r/w default value: 00h size: 8 bits this register implements the cylinder high register of the command block of the ide function. this register can be written only by the host. when host writes to this register, all 3 registers (idechir, idechor0 , idechor1) are updated with the written value. host read to this register address reads the ide cylinder high out register idechor0 if dev=0 or idechor1 if dev=1. 23.3.2.17 idedhiride drive/head in register (iderd22:f2) address offset: 06h attribute: r/w default value: 00h size: 8 bits this register implements the drive/head re gister of the command block of the ide. this register can be written only by the host. when host writes to this register, all 3 registers (idedhir, idedhor0, idedhor1 ) are updated with the written value. host read to this register address reads the ide drive/head out register (idedhor0) if dev=0 or idedhor1 if dev=1. bit 4 of this register is the dev (master/slave) bit. this bit is cleared by hardware on ide software reset (s_rst toggles to '1') in addition to host system reset and d3->d0 transition of the function. bit description 7:0 ide cylinder high out dev 1 (idecho1) ? r/w. cylinder high out register for slave device. bit description 7:0 ide cylinder high data (idechd) ? r/w. cylinder high data register for ide command block. bit description 7:0 ide drive/head data (idedhd) ? r/w. register defines the drive number, head number and addressing mode.
intel? management engine subsystem registers (d22:f[3:0]) 910 datasheet 23.3.2.18 iddhor1ide drive he ad out register device 1 register (iderd22:f2) address offset: 06h attribute: r/w default value: 00h size: 8 bits this register is read only by the host. host read to this drive/head in register address reads the ide drive/head out register (idedhor0) if dev=1 bit 4 of this register is the dev (master/slav e) bit. this bit is cleared by hardware on ide software reset (s_rst toggles to '1') in addition to the host system reset and d3 to d0 transition of the ide function. when the host writes to this address, it updates the value of the idedhir register. 23.3.2.19 iddhor0ide drive he ad out register device 0 register (iderd22:f2) address offset: 06h attribute: r/w default value: 00h size: 8 bits this register is read only by the host. host read to this drive/head in register address reads the ide drive/head out register (idedhor0) if dev=0. bit 4 of this register is the dev (master/slav e) bit. this bit is cleared by hardware on ide software reset (s_rst toggles to 1) in addition to the host system reset and d3 to d0 transition of the ide function. when the host writes to this address, it updates the value of the idedhir register. bit description 7:0 ide drive head out dev 1 (idedho1) ? r/w. drive/head out register of slave device. bit description 7:0 ide drive head out dev 0 (idedho0) ? r/w. drive/head out register of master device.
datasheet 911 intel? management engine subsystem registers (d22:f[3:0]) 23.3.2.20 idesd0ride status device 0 register (iderd22:f2) address offset: 07h attribute: r/w default value: 80h size: 8 bits this register implements the status regist er of the master device (dev = 0). this register is read only by the host. host read of this register clears the master device's interrupt. when the host writes to the same address it writes to the command register the bits description is for ata mode. bit description 7 busy (bsy) ? r/w. this bit is set by hw when the idecr is being written and dev=0, or when srst bit is asserted by host or host system reset or d3-to-d0 transition of the ide function. this bit is cleared by fw write of 0. 6 drive ready (drdy) ? r/w. when set, this bit indicates drive is ready for command. 5 drive fault (df) ? r/w. indicates error on the drive. 4 drive seek complete (dsc) ? r/w. indicates heads are positioned over the desired cylinder. 3 data request (drq) ? r/w. set when, the drive wants to exchange data with the host using the data register. 2 corrected data (corr) ? r/w. when set, this bit indicate s a correctable read error has occurred. 1 index (idx) ? r/w. this bit is set once per rotation of the medium when the index mark passes under the read/write head. 0 error (err) ? r/w. when set, this bit indicates an error occurred in the process of executing the previous command. the error register of the selected device contains the error information.
intel? management engine subsystem registers (d22:f[3:0]) 912 datasheet 23.3.2.21 idesd1ride status device 1 register (iderd22:f2) address offset: 07h attribute: r/w default value: 80h size: 8 bits this register implements the status register of the slave device (dev = 1). this register is read only by the host. host read of this register clears the slave device's interrupt. when the host writes to the same address it writes to the command register. the bits description is for ata mode. 23.3.2.22 idecride command register (iderd22:f2) address offset: 07h attribute: r/w default value: 00h size: 8 bits this register implements the command register of the command block of the ide function. this register can be written only by the host. when the host reads the same address it re ads the status register dev0 if dev=0 or status register dev1 if dev=1 (drive/head register bit [4]). bit description 7 busy (bsy) ? r/w. this bit is set by hardware when the idecr is being written and dev=0, or when srst bit is asserted by the host or host system reset or d3-to-d0 transition of the ide function. this bit is cleared by fw write of 0. 6 drive ready (drdy) ? r/w. when set, indicates driv e is ready for command. 5 drive fault (df) ? r/w. indicates error on the drive. 4 drive seek complete (dsc) r/w. indicates heads are positioned over the desired cylinder. 3 data request (drq) r/w. set when the drive wants to exchange data with the host using the data register. 2 corrected data (corr) r/w. when set indicates a correctable read error has occurred. 1 index (idx) r/w. this bit is set once per rotation of the medium when the index mark passes under the read/write head. 0 error (err) r/w. when set, this bit indicates an error occurred in the process of executing the previous command. the error register of the selected device contains the error information bit description 7:0 ide command data (idecd) r/w. host sends the commands (read/ write, etc.) to the drive using this register.
datasheet 913 intel? management engine subsystem registers (d22:f[3:0]) 23.3.3 ider bar1 registers 23.3.3.1 iddcride device control register (iderd22:f2) address offset: 2h attribute: wo default value: 00h size: 8 bits this register implements the device control register of the control block of the ide function. this register is write only by the host. when the host reads to the same address it reads the alternate status register. 23.3.3.2 idasride alternate status register (iderd22:f2) address offset: 2h attribute: ro default value: 00h size: 8 bits this register implements the alternate status register of the control block of the ide function. this register is a mirror register to the status register in the command block. reading this register by the host does not clear the ide interrupt of the dev selected device host read of this register when dev=0 (master), host gets the mirrored data of idesd0r register. host read of this register when dev=1 (slave), host gets the mirrored data of idesd1r register. table 23-7. ider bar1 register address map address offset register symbol register name default value attribute 2h iddcr ide device control register 00h ro, wo 2h idasr ide alternate status register 00h ro bit description 7:3 reserved 2 software reset (s_rst) ? wo. when this bit is set by th e host, it forces a reset to the device. 1 host interrupt disable (nien) ? wo. when set, this bit disables hardware from sending interrupt to the host. 0reserved bit description 7:0 ide alternate status register (ideasr) ? ro. this field mirrors the value of the dev0/ dev1 status register, depending on the state of the dev bit on host reads.
intel? management engine subsystem registers (d22:f[3:0]) 914 datasheet 23.3.4 ider bar4 registers table 23-8. ider bar4 register address map address offset register symbol register name default value attribute 0h idepbmcr ide primary bus master command register 00h ro, r/w 1h idepbmds0r ide primary bus master device specific 0 register 00h r/w 2h idepbmsr ide primary bus master status register 80h ro, r/w 3h idepbmds1r ide primary bus master device specific 1 register 00h r/w 4h idepbmdtpr0 ide primary bus master descriptor table pointer register byte 0 00h r/w 5h idepbmdtpr1 ide primary bus master descriptor table pointer register byte 1 00h r/w 6h idepbmdtpr2 ide primary bus master descriptor table pointer register byte 2 00h r/w 7h idepbmdtpr3 ide primary bus master descriptor table pointer register byte 3 00h r/w 8h idesbmcr ide secondary bus master command register 00h ro, r/w 9h idesbmds0r ide secondary bus master device specific 0 register 00h r/w ah idesbmsr ide secondary bus master status register 00h r/w, ro bh idesbmds1r ide secondary bus master device specific 1 register 00h r/w ch idesbmdtpr0 ide secondary bus master descriptor table pointer register byte 0 00h r/w dh idesbmdtpr1 ide secondary bus master descriptor table pointer register byte 1 00h r/w eh idesbmdtpr2 ide secondary bus master descriptor table pointer register byte 2 00h r/w fh idesbmdtpr3 ide secondary bus master descriptor table pointer register byte 3 00h r/w
datasheet 915 intel? management engine subsystem registers (d22:f[3:0]) 23.3.4.1 idepbmcride primary bus master command register (iderd22:f2) address offset: 00h attribute: ro, r/w default value: 00h size: 8 bits this register implements the bus master command register of the primary channel. this register is programmed by the host. 23.3.4.2 idepbmds0ride primary bus master device specific 0 register (iderd22:f2) address offset: 01h attribute: r/w default value: 00h size: 8 bits bit description 7:4 reserved 3 read write command (rwc) ? r/w. this bit sets the dire ction of bus master transfer. 0 = reads are performed from system memory 1 = writes are performed to system memory. this bit should not be changed when the bus master function is active. 2:1 reserved 0 start/stop bus master (ssbm) ? r/w . this bit gates the bus master operation of ide function when 0. writing 1 enables the bus master operation. bus master operation can be halted by writing a 0 to this bit. operation ca nnot be stopped and resumed. this bit is cleared after data transfer is co mplete as indicated by either the bmia bit or the int bit of the bus master stat us register is se t or both are set. bit description 7:0 device specific data0 (dsd0) ? r/w . device specific
intel? management engine subsystem registers (d22:f[3:0]) 916 datasheet 23.3.4.3 idepbmsride primary bus master status register (iderd22:f2) address offset: 02h attribute: ro, r/w default value: 80h size: 8 bits 23.3.4.4 idepbmds1ride primary bus master device specific 1 register (iderd22:f2) address offset: 03h attribute: r/w default value: 00h size: 8 bits 23.3.4.5 idepbmdtpr0ide primary bus master descriptor table pointer byte 0 register (iderd22:f2) address offset: 04h attribute: r/w default value: 00h size: 8 bits bit description 7 simplex only (so) ? ro. value indicates whether both bus master channels can be operated at the same time or not. 0 = both can be oper ated independently 1 = only one can be operated at a time. 6 drive 1 dma capable (d1dc) ? r/w . this bit is read/write by the host (not write 1 clear). 5 drive 0 dma capable (d0dc) ? r/w . this bit is read/write by the host (not write 1 clear). 4:3 reserved 2 interrupt (int) ? r/w . this bit is set by the hardware when it detects a positive transition in the interrupt logic (refer to ide host interrupt generation diagram).the hardware will clear this bit when the host sw writes 1 to it. 1 error (er) ? r/w . bit is typically set by fw. hardwa re will clear this bit when the host sw writes 1 to it. 0 bus master ide active (bmia) ? ro. this bit is set by hardware when ssbm register is set to 1 by the host. when the bus master operation ends (for the whole command) this bit is cleared by fw. this bit is not cleared when the host writes 1 to it. bit description 7:0 device specific data1 (dsd1) ? r/w. device specific data. bit description 7:0 descriptor table pointer byte 0 (dtpb0) ? r/w. this register implements the byte 0 (1 of 4 bytes) of the descriptor ta ble pointer (four i/o byte addresses) for bus master operation of the primary channel. th is register is read/write by the host interface.
datasheet 917 intel? management engine subsystem registers (d22:f[3:0]) 23.3.4.6 idepbmdtpr1ide primary bus master descriptor table pointer byte 1 register (iderd22:f2) address offset: 05h attribute: r/w default value: 00h size: 8 bits 23.3.4.7 idepbmdtpr2ide primary bus master descriptor table pointer byte 2 register (iderd22:f2) address offset: 06h attribute: r/w default value: 00h size: 8 bits 23.3.4.8 idepbmdtpr3ide primary bus master descriptor table pointer byte 3 register (iderd22:f2) address offset: 07h attribute: r/w default value: 00h size: 8 bits bit description 7:0 descriptor table pointer byte 1 (dtpb1) ? r/w. this register implements the byte 1 (of four bytes) of the descriptor ta ble pointer (four i/o by te addresses) for bus master operation of the primary channel. th is register is programmed by the host. bit description 7:0 descriptor table pointer byte 2 (dtpb2) ? r/w. this register implements the byte 2 (of four bytes) of the descriptor ta ble pointer (four i/o byte addresses) for bus master operation of the primary channel. th is register is programmed by the host. bit description 7:0 descriptor table pointer byte 3 (dtpb3) ? r/w. this register implements the byte 3 (of four bytes) of the descriptor ta ble pointer (four i/o byte addresses) for bus master operation of the primary channel. th is register is programmed by the host.
intel? management engine subsystem registers (d22:f[3:0]) 918 datasheet 23.3.4.9 idesbmcride secondary bus master command register (iderd22:f2) address offset: 08h attribute: r/w default value: 00h size: 8 bits 23.3.4.10 idesbmds0ride secondary bus master device specific 0 register (iderd22:f2) address offset: 09h attribute: r/w default value: 00h size: 8 bits bit description 7:4 reserved 3 read write command (rwc) ? r/w. this bit sets the direction of bus master transfer. when 0, reads are performed from system memory; when 1, writes are performed to system memory. this bit shou ld not be changed when the bus master function is active. 2:1 reserved 0 start/stop bus master (ssbm) ? r/w. this bit gates the bus master operation of ide function when zero. writing 1 enables the bus master operation. bus master operation can be halted by writing a 0 to this bit. operatio n cannot be sto pped and resumed. this bit is cleared after data transfer is complete as indi cated by either the bmia bit or the int bit of the bus master status register is set or both are set. bit description 7:0 device specific data0 (dsd0) ? r/w. this register implements the bus master device specific 1 register of the secondary channel. this register is programmed by the host.
datasheet 919 intel? management engine subsystem registers (d22:f[3:0]) 23.3.4.11 idesbmsride secondary bus master status register (iderd22:f2) address offset: 0ah attribute: r/w, ro default value: 80h size: 8 bits 23.3.4.12 idesbmds1ride secondary bus master device specific 1 register (iderd22:f2) address offset: 0bh attribute: r/w default value: 00h size: 8 bits 23.3.4.13 idesbmdtpr0ide secondary bus master descriptor table pointer byte 0 register (iderd22:f2) address offset: 0ch attribute: r/w default value: 00h size: 8 bits bit description 7 simplex only (so) ? r/w. this bit indicates whether both bus master channels can be operated at the same time or not. 0 = both can be operated independently 1 = only one can be operated at a time. 6 drive 1 dma capable (d1dc) ? r/w. this bit is read/write by the host. 5 drive 0 dma capable (d0dc) ? r/w. this bit is read/write by the host. 4:0 reserved bit description 7:0 device specific data1 (dsd1) ? r/w. this register implements the bus master device specific 1 register of the secondary channel. this register is programmed by the host for device specific data if any. bit description 7:0 descriptor table pointer byte 0 (dtpb0) ? r/w. this register implements the byte 0 (1 of 4 bytes) of the descriptor ta ble pointer (four i/o byte addresses) for bus master operation of the secondary channel. this register is read/write by the host interface.
intel? management engine subsystem registers (d22:f[3:0]) 920 datasheet 23.3.4.14 idesbmdtpr1ide secondary bus master descriptor table pointer byte 1 register (iderd22:f2) address offset: 0dh attribute: r/w default value: 00h size: 8 bits 23.3.4.15 idesbmdtpr2ide secondary bus master descriptor table pointer byte 2 register (iderd22:f2) address offset: 0eh attribute: r/w default value: 00h size: 8 bits 23.3.4.16 idesbmdtpr3ide secondary bus master descriptor table pointer byte 3 register (iderd22:f2) address offset: 0fh attribute: r/w default value: 00h size: 8 bits bit description 7:0 descriptor table pointer byte 1 (dtpb1) ? r/w. this register implements the byte 1 (of four bytes) of the descriptor tabl e pointer (four i/o byte addresses) for bus master operation of the secondary channel. this register is programmed by the host. bit description 7:0 descriptor table pointer byte 2 (dtpb2) ? r/w. this register implements the byte 2 (of four bytes) of the descriptor ta ble pointer (four i/o by te addresses) for bus master operation of the secondary channel. this register is programmed by the host. bit description 7:0 descriptor table pointer byte 3 (dtpb3) ? r/w. this register implements the byte 3 (of four bytes) of the descriptor ta ble pointer (four i/o by te addresses) for bus master operation of the secondary channel. this register is programmed by the host.
datasheet 921 intel? management engine subsystem registers (d22:f[3:0]) 23.4 serial port for remote keyboard and text (kt) redirection (kt d22:f3) 23.4.1 pci configuration registers (kt d22:f3) table 23-9. serial port for remote keyboard and text (kt) redirection register address map address offset register symbol register name default value attribute 00h?01h vid vendor identification 8086h ro 02h?03h did device identification see register description ro 04h?05h cmd command register 0000h ro, r/w 06h?07h sts device status 00b0h ro 08h rid revision id see register description ro 09h?0bh cc class codes 070002h ro 0ch cls cache line size 00h ro 10h?13h ktiba kt io block base address 00000001h ro, r/w 14h?17h ktmba kt memory block base address 00000000h ro, r/w 2ch?2dh svid subsystem vendor id 0000h r/wo 2eh?2fh sid subsystem id 8086h r/wo 34h cap capabilities pointer c8h ro 3ch?3dh intr interrupt information 0200h r/w, ro c8h?c9h pid pci power management capability id d001h ro cah?cbh pc pci power management capabilities 0023h ro d0h?d1h mid message signaled in terrupt capability id 0005h ro d2h?d3h mc message signaled interrupt message control 0080h ro, r/w d4h?d7h ma message signaled interrupt message address 00000000h ro, r/w d8h?dbh mau message signaled interrupt message upper address 00000000h ro, r/w dch?ddh md message signaled interrupt message data 0000h r/w
intel? management engine subsystem registers (d22:f[3:0]) 922 datasheet 23.4.1.1 vidvendor identification register (ktd22:f3) address offset: 00?01h attribute: ro default value: 8086h size: 16 bits 23.4.1.2 diddevice identification register (ktd22:f3) address offset: 02?03h attribute: ro default value: see bit description size: 16 bits 23.4.1.3 cmdcommand register (ktd22:f3) address offset: 04?05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:0 vendor id (vid) ? ro. this is a 16-bit value assigned by intel. bit description 15:0 device id (did) ? ro. this is a 16-bit value assigned to the pch kt controller. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the did register. bit description 15:11 reserved 10 interrupt disable (id) ? r/w. this bit disables pin-based intx# interrupts. this bit has no effect on msi operation. 1 = internal intx# messages will not be generated. 0 = internal intx# messages are generated if there is an interrupt and msi is not enabled. 9:3 reserved 2 bus master enable (bme) ? r/w. this bit controls the kt function's ability to act as a master for data transfers. this bit does not impact the generation of completions for split transaction commands. for kt, the only bus mastering activity is msi generation. 1 memory space enable (mse) ? r/w. this bit controls access to the pt function's target memory space. 0 i/o space enable (iose) ? r/w. this bit controls access to the pt function's target i/o space.
datasheet 923 intel? management engine subsystem registers (d22:f[3:0]) 23.4.1.4 stsdevice status register (ktd22:f3) address offset: 06?07h attribute: ro default value: 00b0h size: 16 bits 23.4.1.5 ridrevision id register (ktd22:f3) address offset: 08h attribute: ro default value: see bit description size: 8 bits 23.4.1.6 ccclass codes register (ktd22:f3) address offset: 09?0bh attribute: ro default value: 070002h size: 24 bits bit description 15:11 reserved 10:9 devsel# timing status (devt) ? ro. this field controls the device select time for the pt function's pci interface. 8:5 reserved 4 capabilities list (cl) ? ro. this bit indicates that ther e is a capabili ties pointer implemented in the device. 3 interrupt status (is) ? ro. this bit reflects the state of the interrupt in the function. setting of the interrupt disable bit to 1 has no affe ct on this bit. only when this bit is a 1 and id bit is 0 is the intb interru pt asserted to the host. 2:0 reserved bit description 7:0 revision id (rid) ? ro. see the intel ? 6 series chipset and intel ? c200 series chipset specification update for the value of the rid register. bit description 23:16 base class code (bcc) ?ro this field indicates the base class code of the kt host controller device. 15:8 sub class code (scc) ?ro this field indicates the sub class code of the kt host controller device. 7:0 programming interface (pi) ?ro this field indicates the programming interface of the kt host controller device.
intel? management engine subsystem registers (d22:f[3:0]) 924 datasheet 23.4.1.7 clscache line size register (ktd22:f3) address offset: 0ch attribute: ro default value: 00h size: 8 bits this register defines the system cache line size in dword increments. mandatory for master which use the memory-write and invalidate command. 23.4.1.8 ktibakt io block base address register (ktd22:f3) address offset: 10?13h attribute: ro, r/w default value: 00000001h size: 32 bits 23.4.1.9 ktmbakt memory block base address register (ktd22:f3) address offset: 14?17h attribute: ro, r/w default value: 00000000h size: 32 bits bit description 7:0 cache line size (cls) ? ro. all writes to system memory are memory writes. bit description 31:16 reserved 15:3 base address (bar) ? r/w. this field provides the base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. this bit indicates a request for i/o space bit description 31:12 base address (bar) ? r/w. this field provides the base address for memory mapped i,o bar. bits 31:12 corre spond to address signals 31:12. 11:4 reserved 3 prefetchable (pf) ? ro. this bit indicates that this range is not pre-fetchable. 2:1 type (tp) ? ro. this field indicates that this ra nge can be mapped anywhere in 32- bit address space. 0 resource type indicator (rte) ? ro. this bit indicates a request for register memory space.
datasheet 925 intel? management engine subsystem registers (d22:f[3:0]) 23.4.1.10 svidsubsystem vendor id register (ktd22:f3) address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits 23.4.1.11 sidsubsystem id register (ktd22:f3) address offset: 2eh ? 2fh attribute: r/wo default value: 8086h size: 16 bits 23.4.1.12 capcapabilities pointer register (ktd22:f3) address offset: 34h attribute: ro default value: c8h size: 8 bits this optional register is used to point to a linked list of new capabilities implemented by the device. 23.4.1.13 intrinterrupt information register (ktd22:f3) address offset: 3c?3dh attribute: r/w, ro default value: 0200h size: 16 bits bit description 15:0 subsystem vendor id (ssvid) ? r/wo. indicates the sub-system vendor identifier. this field should be programmed by bios during boot-up. once written, this register becomes read on ly. this field can only be cleared by pltrst#. note: register must be written as a dword write with sid register. bit description 15:0 subsystem id (ssid) ? r/wo. indicates the sub-system identifier. this field should be programmed by bios during boot-up. on ce written, this register becomes read only. this field can only be cleared by pltrst#. note: register must be written as a dword write with svid register. bit description 7:0 capability pointer (cp) ? ro. this field indicates that the first capability pointer is offset c8h (the power management capability). bit description 15:8 interrupt pin (ipin) ? ro. a value of 1h/2h/3h/4h indi cates that this function implements legacy inte rrupt on inta/intb/intc/intd, respectively functionvalueintx (3 kt/serial port)02hintb 7:0 interrupt line (iline) ? r/w. the value written in this register tells which input of the system interrupt controller , the device's inte rrupt pin is connected to. this value is used by the os and the device driv er, and has no affect on the hardware.
intel? management engine subsystem registers (d22:f[3:0]) 926 datasheet 23.4.1.14 pidpci power management capability id register (ktd22:f3) address offset: c8?c9h attribute: ro default value: d001h size: 16 bits 23.4.1.15 pcpci power manageme nt capabilities id register (ktd22:f3) address offset: ca?cbh attribute: ro default value: 0023h size: 16 bits bit description 15:8 next capability (next) ? ro. a value of d0h points to the msi capability. 7:0 cap id (cid) ? ro. this field indicates that this pointer is a pci power management. bit description 15:11 pme support (pme) ? ro.this field indicates no pme# in the pt function. 10:6 reserved 5 device specific initialization (dsi) ? ro. this bit indicates that no device-specific initialization is required. 4 reserved 3 pme clock (pmec) ? ro. this bit indicates that pci clock is not required to generate pme# 2:0 version (vs) ? ro. this field indicates support for the pci power management specification, revision 1.2 .
datasheet 927 intel? management engine subsystem registers (d22:f[3:0]) 23.4.1.16 midmessage signal ed interrupt capability id register (ktd22:f3) address offset: d0?d1h attribute: ro default value: 0005h size: 16 bits message signalled interrupt is a feature that allows the device/function to generate an interrupt to the host by performing a dw ord memory write to a system specified address with system specified data. this register is used to identify and configure an msi capable device. 23.4.1.17 mcmessage signaled interrupt message control register (ktd22:f3) address offset: d2?d3h attribute: ro, r/w default value: 0080h size: 16 bits 23.4.1.18 mamessage signaled interrupt message address register (ktd22:f3) address offset: d4?d7h attribute: ro, r/w default value: 00000000h size: 32 bits this register specifies the dword aligned a ddress programmed by system software for sending msi. bit description 15:8 next pointer (next) ? ro. this value indicates this is the last item in the list. 7:0 capability id (cid) ? ro. this field value of capabiliti es id indicate s device is capable of generating msi. bit description 15:8 reserved 7 64 bit address capable (c64) ? ro. capable of generating 64-bit and 32-bit messages. 6:4 multiple message enable (mme) ? r/w.these bits are r/w for software compatibility, but only one message is ever sent by the pt function. 3:1 multiple message capable (mmc) ? ro. only one message is required. 0 msi enable (msie) ? r/w. if set, msi is enabled and traditional interrupt pins are not used to generate interrupts. bit description 31:2 address (addr) ? r/w. lower 32 bits of the system specified mess age address, always dword aligned. 1:0 reserved
intel? management engine subsystem registers (d22:f[3:0]) 928 datasheet 23.4.1.19 maumessage signaled interrupt message upper address register (ktd22:f3) address offset: d8?dbh attribute: ro, r/w default value: 00000000h size: 32 bits 23.4.1.20 mdmessage signaled interrupt message data register (ktd22:f3) address offset: dc?ddh attribute: r/w default value: 0000h size: 16 bits this 16-bit field is programmed by system software if msi is enabled 23.4.2 kt io/memory mapp ed device registers bit description 31:4 reserved 3:0 address (addr) ? r/w. upper 4 bits of the system specified message address. bit description 15:0 data (data) ? r/w. this msi data is driven onto th e lower word of the data bus of the msi memory write transaction. table 23-10. kt io/memory mapped device register address map address offset register symbol register name default value attribute 0h ktrxbr kt receive buffer register 00h ro 0h ktthr kt transmit holding register 00h wo 0h ktdllr kt divisor latch lsb register 00h r/w 1h ktier kt interrupt enab le register 00h r/w, ro 1h ktdlmr kt divisor latch msb register 00h r/w 2h ktiir kt interrupt identification register 01h ro 2h ktfcr kt fifo control register 00h wo 3h ktlcr kt line control register 03h r/w 4h ktmcr kt modem control register 00h ro, r/w 5h ktlsr kt line status register 00h ro 6h ktmsr kt modem status register 00h ro
datasheet 929 intel? management engine subsystem registers (d22:f[3:0]) 23.4.2.1 ktrxbrkt receive bu ffer register (ktd22:f3) address offset: 00h attribute: ro default value: 00h size: 8 bits this implements the kt receiver data regist er. host access to this address, depends on the state of the dlab bit (ktlcr[7]). it must be 0 to access the ktrxbr. rxbr: host reads this register when fw provides it the receive data in non-fifo mode. in fifo mode, host reads to this register transl ate into a read from intel me memory (rbr fifo). 23.4.2.2 ktthrkt transmit ho lding register (ktd22:f3) address offset: 00h attribute: ro default value: 00h size: 8 bits this implements the kt transmit data register. host access to this address, depends on the state of the dlab bit (ktlcr[7]). it must be 0 to access the ktthr. thr: when host wants to transmit data in the non-fifo mode, it writes to this register. in fifo mode, writes by host to this addre ss cause the data byte to be written by hardware to intel me memory (thr fifo). 23.4.2.3 ktdllrkt divisor latch lsb register (ktd22:f3) address offset: 00h attribute: r/w default value: 00h size: 8 bits this register implements the kt dll register. host can read/write to this register only when the dlab bit (ktlcr[7]) is 1. when this bit is 0, host accesses the ktthr or the ktrbr depending on read or write. this is the standard serial port divisor latch register. this register is only for software compatibility and does not affect performance of the hardware. bit description 7:0 receiver buffer register (rbr) ? ro. implements the data register of the serial interface. if the host does a read, it reads from the receive data buffer. bit description 7:0 transmit holding register (thr) ? wo. implements the transmit data register of the serial interface. if the host does a write, it writes to the transmit holding register. bit description 7:0 divisor latch lsb (dll) ? r/w. implements the dll register of the serial interface.
intel? management engine subsystem registers (d22:f[3:0]) 930 datasheet 23.4.2.4 ktierkt interrupt enable register (ktd22:f3) address offset: 01h attribute: r/w default value: 00h size: 8 bits this implements the kt interrupt enable regi ster. host access to this address, depends on the state of the dlab bit (ktlcr[7]). it mu st be "0" to access this register. the bits enable specific events to interrupt the host. 23.4.2.5 ktdlmrkt divisor latch msb register (ktd22:f3) address offset: 01h attribute: r/w default value: 00h size: 8 bits host can read/write to this register only when the dlab bit (ktlcr[7]) is 1. when this bit is 0, host accesses the ktier. this is the standard serial interface's divisor latch register's msb. this register is only for sw compatibility and does not af fect performance of the hardware. bit description 7:4 reserved 3 msr (ier2) ? r/w. when set, this bit enables bits in the modem stat us register to cause an interrupt to the host. 2 lsr (ier1) ? r/w.when set, this bit enables bits in the receiver line status register to cause an interrupt to the host. 1 thr (ier1) ? r/w. when set, this bit enables an interrupt to be sent to the host when the transmit hold ing register is empty. 0 dr (ier0) ? r/w. when set, the received data re ady (or receive fifo timeout) interrupts are enabled to be sent to host. bit description 7:0 divisor latch msb (dlm) ? r/w. implements the divisor latch msb register of the serial interface.
datasheet 931 intel? management engine subsystem registers (d22:f[3:0]) 23.4.2.6 ktiirkt interrupt identification register (ktd22:f3) address offset: 02h attribute: ro default value: 00h size: 8 bits the kt iir register prioritizes the interrupts from the function into 4 levels and records them in the iir_stat field of the register. when host accesses the iir, hardware freezes all interrupts and provides the prio rity to the host. hardware continues to monitor the interrupts but does not change its current indication until the host read is over. table in the host interrupt generation section shows the contents. 23.4.2.7 ktfcrkt fifo control register (ktd22:f3) address offset: 02h attribute: wo default value: 00h size: 8 bits when host writes to this address, it writes to the ktfcr. the fifo control register of the serial interface is used to enable the fi fos, set the receiver fifo trigger level and clear fifos under the direction of the host. when host reads from this address, it reads the ktiir. bit description 7 fifo enable (fien1) ? ro. this bit is connected by ha rdware to bit 0 in the fcr register. 6 fifo enable (fien0) ? ro. this bit is connected by ha rdware to bit 0 in the fcr register. 5:4 reserved 3:1 iir status (iirsts) ? ro. these bits are asserted by the hardware according to the source of the interrupt and the priority level. 0 interrupt status (intsts) ? ro. 0 = pending interrupt to host 1 = no pending interrupt to host bit description 7:6 receiver trigger level (rtl) ? wo. trigger level in bytes for the rcv fifo. once the trigger level number of bytes is reac hed, an interrupt is sent to the host. 00 = 01 01 = 04 10 = 08 11 = 14 5:3 reserved 2 xmt fifo clear (xfic) ? wo. when the host writes one to this bit, the hardware will clear the xmt fifo. this bit is self-cleared by hardware. 1 rcv fifo clear (rfic) ? wo. when the host writes one to this bit, the hardware will clear the rcv fifo. this bit is self-cleared by hardware. 0 fifo enable (fie) ? wo.when set, this bit indicates that the kt interface is working in fifo node. when this bi t value is changed the rcv and xmt fifo are cleared by hardware.
intel? management engine subsystem registers (d22:f[3:0]) 932 datasheet 23.4.2.8 ktlcrkt line control register (ktd22:f3) address offset: 03h attribute: r/w default value: 00h size: 8 bits the line control register specifies the format of the asynchronous data communications exchange and sets the dlab bit. most bits in this register have no affect on hardware and are only used by the fw. 23.4.2.9 ktmcrkt modem control register (ktd22:f3) address offset: 04h attribute: r/w default value: 00h size: 8 bits the modem control register controls the interface with the modem. since the fw emulates the modem, the host communicates to the fw using this register. register has impact on hardware when the loopback mode is on. bit description 7 divisor latch address bit (dlab) ? r/w. this bit is set when the host wants to read/write the divisor latch lsb and msb regi sters. this bit is cleared when the host wants to access the receive buffer register or the transmit holding register or the interrupt enable register. 6 break control (bc) ? r/w. this bit has no affect on hardware. 5:4 parity bit mode (pbm) ? r/w. this bit has no affect on hardware. 3 parity enable (pe) ? r/w.this bit has no affect on hardware. 2 stop bit select (sbs) ? r/w. this bit has no affect on hardware. 1:0 word select byte (wsb) ? r/w. this bit has no affect on hardware. bit description 7:5 reserved 4 loop back mode (lbm) ? r/w. when set by the host, this bit indicates that the serial port is in loop back mode. this mean s that the data that is transmitted by the host should be received. help s in debug of the interface. 3 output 2 (out2) ? r/w. this bit has no affect on hard ware in normal mode. in loop back mode the value of this bit is written by hardware to the mo dem status register bit 7. 2 output 1 (out1) ? r/w. this bit has no affect on hard ware in normal mode. in loop back mode the value of this bit is written by hardware to modem status register bit 6. 1 request to send out (rtso) ? r/w. this bit has no affect on hardware in normal mode. in loopback mode, the value of this bi t is written by hardware to modem status register bit 4. 0 data terminal ready out (drto) ? r/w. this bit has no affect on hardware in normal mode. in loopback mode, the value in this bit is written by hardware to modem status register bit 5.
datasheet 933 intel? management engine subsystem registers (d22:f[3:0]) 23.4.2.10 ktlsrkt line status register (ktd22:f3) address offset: 05h attribute: wo default value: 00h size: 8 bits this register provides status information of the data transfer to the host. error indication, etc. are provided by the hw/fw to the host using this register. bit description 7 rx fifo error (rxfer) ? ro. this bit is cleared in no n fifo mode. this bit is connected to bi bit in fifo mode. 6 transmit shift register empty (temt) ? ro. this bit is connected by hw to bit 5 (thre) of this register. 5 transmit holding register empty (thre) ? ro. this bit is always set when the mode (fifo/non-fifo) is chan ged by the host. this bit is active only when the thr operation is enabled by the fw. this bit ha s acts differently in the different modes: non fifo : this bit is cleared by hardware when the host writes to the thr registers and set by hardware when th e fw reads the thr register. fifo mode : this bit is set by hardware when th e thr fifo is empty, and cleared by hardware when the thr fifo is not empty. this bit is reset on host syst em reset or d3->d0 transition. 4 break interrupt (bi) ? ro. this bit is cleared by hardware when the lsr register is being read by the host. 3:2 reserved 1 overrun error (oe): this bit is cleared by hardware when the lsr register is being read by the host. the fw typi cally sets this bit, but it is cleared by hardware when the host reads the lsr. 0 data ready (dr) ? ro. non-fifo mode: this bit is set when the fw writes to the rbr register and cleared by hardware when the rbr regist er is being read by the host. fifo mode: this bit is set by hardware when the rbr fifo is no t empty and cleared by hardware when th e rbr fifo is empty. this bit is reset on host system reset or d3->d0 transition.
intel? management engine subsystem registers (d22:f[3:0]) 934 datasheet 23.4.2.11 ktmsrkt modem status register (ktd22:f3) address offset: 06h attribute: ro default value: 00h size: 8 bits the functionality of the modem is emulated by the fw. this register provides the status of the current state of the control lines from the modem. bit description 7 data carrier detect (dcd) ? ro. in loop back mode this bit is connected by hardware to the value of mcr bit 3. 6 ring indicator (ri) ? ro. in loop back mode this bit is connected by hardware to the value of mcr bit 2. 5 data set ready (dsr) ? ro. in loop back mode this bit is connected by hardware to the value of mcr bit 0. 4 clear to send (cts) ? ro. in loop back mode this bit is connected by hardware to the value of mcr bit 1. 3 delta data carrier detect (ddcd) ? ro. this bit is set when bit 7 is changed. this bit is cleared by hard ware when the msr register is being read by the host driver. 2 trailing edge of read detector (teri) ? ro. this bit is set when bit 6 is changed from 1 to 0. this bit is cleared by hardware when the msr register is being read by the host driver. 1 delta data set ready (ddsr) ? ro. this bit is set when bit 5 is changed. this bit is cleared by hardware when the msr regi ster is being read by the host driver. 0 delta clear to send (dcts) ? ro. this bit is set when bit 4 is changed. this bit is cleared by hardware when the msr regist er is being read by the host driver.

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